!<arch>
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libpmc_pmu_util.o/

libpmc.o/       0           0     0     100644  220276    `
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hwpmcINSTR_RETIRED_ANYCPU_CLK_UNHALTED_CORECPU_CLK_UNHALTED_REFTSCFP_DISPATCHED_FPU_OPSFP_CYCLES_WITH_NO_FPU_OPS_RETIREDFP_DISPATCHED_FPU_FAST_FLAG_OPSLS_SEGMENT_REGISTER_LOADLS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODELS_MICROARCHITECTURAL_RESYNC_BY_SNOOPLS_BUFFER2_FULLLS_LOCKED_OPERATIONLS_MICROARCHITECTURAL_LATE_CANCELLS_RETIRED_CFLUSH_INSTRUCTIONSLS_RETIRED_CPUID_INSTRUCTIONSDC_ACCESSDC_MISSDC_REFILL_FROM_L2DC_REFILL_FROM_SYSTEMDC_COPYBACKDC_L1_DTLB_MISS_AND_L2_DTLB_HITDC_L1_DTLB_MISS_AND_L2_DTLB_MISSDC_MISALIGNED_DATA_REFERENCEDC_MICROARCHITECTURAL_LATE_CANCELDC_MICROARCHITECTURAL_EARLY_CANCELDC_ONE_BIT_ECC_ERRORDC_DISPATCHED_PREFETCH_INSTRUCTIONSDC_DCACHE_ACCESSES_BY_LOCKSBU_CPU_CLK_UNHALTEDBU_INTERNAL_L2_REQUESTBU_FILL_REQUEST_L2_MISSBU_FILL_INTO_L2IC_FETCHIC_MISSIC_REFILL_FROM_L2IC_REFILL_FROM_SYSTEMIC_L1_ITLB_MISS_AND_L2_ITLB_HITIC_L1_ITLB_MISS_AND_L2_ITLB_MISSIC_MICROARCHITECTURAL_RESYNC_BY_SNOOPIC_INSTRUCTION_FETCH_STALLIC_RETURN_STACK_HITIC_RETURN_STACK_OVERFLOWFR_RETIRED_X86_INSTRUCTIONSFR_RETIRED_UOPSFR_RETIRED_BRANCHESFR_RETIRED_BRANCHES_MISPREDICTEDFR_RETIRED_TAKEN_BRANCHESFR_RETIRED_TAKEN_BRANCHES_MISPREDICTEDFR_RETIRED_FAR_CONTROL_TRANSFERSFR_RETIRED_RESYNCSFR_RETIRED_NEAR_RETURNSFR_RETIRED_NEAR_RETURNS_MISPREDICTEDFR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPAREFR_RETIRED_FPU_INSTRUCTIONSFR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSFR_INTERRUPTS_MASKED_CYCLESFR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESFR_TAKEN_HARDWARE_INTERRUPTSFR_DECODER_EMPTYFR_DISPATCH_STALLSFR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIREFR_DISPATCH_STALL_FOR_SERIALIZATIONFR_DISPATCH_STALL_FOR_SEGMENT_LOADFR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULLFR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULLFR_DISPATCH_STALL_WHEN_FPU_IS_FULLFR_DISPATCH_STALL_WHEN_LS_IS_FULLFR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIETFR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDINGFR_FPU_EXCEPTIONSFR_NUMBER_OF_BREAKPOINTS_FOR_DR0FR_NUMBER_OF_BREAKPOINTS_FOR_DR1FR_NUMBER_OF_BREAKPOINTS_FOR_DR2FR_NUMBER_OF_BREAKPOINTS_FOR_DR3NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENTNB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWNB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDNB_MEMORY_CONTROLLER_TURNAROUNDNB_MEMORY_CONTROLLER_BYPASS_SATURATIONNB_SIZED_COMMANDSNB_PROBE_RESULTNB_HT_BUS0_BANDWIDTHNB_HT_BUS1_BANDWIDTHNB_HT_BUS2_BANDWIDTHPMNC_SW_INCRL1_ICACHE_REFILLITLB_REFILLL1_DCACHE_REFILLL1_DCACHE_ACCESSDTLB_REFILLMEM_READMEM_WRITEEXC_TAKENEXC_EXECUTEDCID_WRITEPC_WRITEPC_IMM_BRANCHMEM_UNALIGNED_ACCESSPC_BRANCH_MIS_PREDCLOCK_CYCLESPC_BRANCH_PREDINSTR_EXECUTEDPC_PROC_RETURNMEM_ACCESSL1_ICACHE_ACCESSL1_DCACHE_WBL2_CACHE_ACCESSL2_CACHE_REFILLL2_CACHE_WBBUS_ACCESSMEM_ERRORINSTR_SPECTTBR_WRITEBUS_CYCLESCPU_CYCLESWRITE_BUF_FULLL2_STORE_MERGEDL2_STORE_BUFFERABLEL2_ACCESSL2_CACHE_MISSAXI_READAXI_WRITEMEM_REPLAY_EVTMEM_UNALIGNED_ACCESS_REPLAYL1_DCACHE_HASH_MISSL1_ICACHE_HASH_MISSL1_CACHE_PAGECOL_ALIASL1_DCACHE_NEON_ACCESSL1_DCACHE_NEON_CACHEABLEL2_CACHE_NEON_MEM_ACCESSL2_CACHE_NEON_HITL1_CACHE_ACCESS_NOCP15RET_STACK_MISPREDICTBRANCH_DIR_MISPREDICTPRED_BRANCH_PRED_TAKENPRED_BRANCH_EXEC_TAKENOPS_ISSUEDCYCLES_NO_INSTRUCTIONINSTRUCTIONS_ISSUED_CYCLECYCLES_STALLED_NEON_MRCCYCLES_STALLED_NEON_FULLQCYCLES_NONIDLE_NEON_INTPMUEXTIN0_EVTPMUEXTIN1_EVTPMUEXTIN_EVTJAVA_BYTECODESOFTWARE_JAVA_BYTECODEJAZELLE_BACKWARD_BRANCHCOHERENT_LINEFILL_MISSCCOHERENT_LINEFILL_HITCINSTR_CACHE_DEPENDENT_STALLDATA_CACHE_DEPENDENT_STALLMAIN_TLB_MISS_STALLSTREX_PASSEDSTREX_FAILEDDATA_EVICTIONISSUE_DNOT_DISPATCH_ANY_INSTRISSUE_IS_EMPTYINSTR_RENAMEDPREDICTABLE_FUNCTION_RETURNMAIN_EXECUTION_UNIT_PIPESECOND_EXECUTION_UNIT_PIPELOAD_STORE_PIPEFLOATING_POINT_INSTR_RENAMEDNEON_INSTRS_RENAMEDPLD_STALLWRITE_STALLINSTR_MAIN_TLB_MISS_STALLDATA_MAIN_TLB_MISS_STALLINSTR_MICRO_TLB_MISS_STALLDATA_MICRO_TLB_MISS_STALLDMB_STALLINTEGER_CORE_CLOCK_ENABLEDDATA_ENGINE_CLOCK_ENABLEDISBDSBDMBEXTERNAL_INTERRUPTPLE_CACHE_LINE_REQ_COMPLETEDPLE_CACHE_LINE_REQ_SKIPPEDPLE_FIFO_FLUSHPLE_REQUEST_COMPLETEDPLE_FIFO_OVERFLOWPLE_REQUEST_PROGRAMMEDSW_INCRL1I_CACHE_REFILLL1I_TLB_REFILLL1D_CACHE_REFILLL1D_CACHEL1D_TLB_REFILLINST_RETIREDEXC_RETURNCID_WRITE_RETIREDBR_MIS_PREDBR_PREDL1I_CACHEL1D_CACHE_WBL2D_CACHEL2D_CACHE_REFILLL2D_CACHE_WBMEMORY_ERRORCHAINBUS_ACCESS_LDBUS_ACCESS_STBR_INDIRECT_SPECEXC_IRQEXC_FIQLD_RETIREDST_RETIREDPC_WRITE_RETIREDBR_IMMED_RETIREDBR_RETURN_RETIREDUNALIGNED_LDST_RETIREDINST_SPECTTBR_WRITE_RETIREDL1D_CACHE_LDL1D_CACHE_STL1D_CACHE_REFILL_LDL1D_CACHE_REFILL_STL1D_CACHE_WB_VICTIML1D_CACHE_WB_CLEANL1D_CACHE_INVALL1D_TLB_REFILL_LDL1D_TLB_REFILL_STL2D_CACHE_LDL2D_CACHE_STL2D_CACHE_REFILL_LDL2D_CACHE_REFILL_STL2D_CACHE_WB_VICTIML2D_CACHE_WB_CLEANL2D_CACHE_INVALMEM_ACCESS_LDMEM_ACCESS_STUNALIGNED_LD_SPECUNALIGNED_ST_SPECUNALIGNED_LDST_SPECLDREX_SPECSTREX_PASS_SPECSTREX_FAIL_SPECLD_SPECST_SPECLDST_SPECDP_SPECASE_SPECVFP_SPECPC_WRITE_SPECCRYPTO_SPECBR_IMMED_SPECBR_RETURN_SPECISB_SPECDSB_SPECDMB_SPECEXC_UNDEFEXC_SVCEXC_PABORTEXC_DABORTEXC_SMCEXC_HVCEXC_TRAP_PABORTEXC_TRAP_DABORTEXC_TRAP_OTHEREXC_TRAP_IRQEXC_TRAP_FIQRC_LD_SPECRC_ST_SPECBUS_ACCESS_SHAREDBUS_ACCESS_NOT_SHAREDBUS_ACCESS_NORMALBUS_ACCESS_PERIPHL2D_CACHE_ALLOCATEBR_RETIREDBR_MIS_PRED_RETIREDSTALL_FRONTENDSTALL_BACKENDL1D_TLBL1I_TLBL3D_CACHE_ALLOCATEL3D_CACHE_REFILLL3D_CACHEL2D_TLB_REFILLL2D_TLBREMOTE_ACCESSDTLB_WALKITLB_WALKLL_CACHE_RDLL_CACHE_MISS_RDL1D_CACHE_REFILL_INNERL1D_CACHE_REFILL_OUTERL1D_TLB_RDL1D_TLB_WRL2D_TLB_REFILL_RDL2D_TLB_REFILL_WRL2D_TLB_RDL2D_TLB_WRSTREX_SPECL3_CACHE_RDCYCLEINSTINST_USERINST_KERNELIMPRECISE_SETBOUNDSUNREPRESENTABLE_CAPSITLB_MISSDTLB_MISSICACHE_WRITE_HITICACHE_WRITE_MISSICACHE_READ_HITICACHE_READ_MISSICACHE_EVICTDCACHE_WRITE_HITDCACHE_WRITE_MISSDCACHE_READ_HITDCACHE_READ_MISSDCACHE_EVICTDCACHE_SET_TAG_WRITEDCACHE_SET_TAG_READL2CACHE_WRITE_HITL2CACHE_WRITE_MISSL2CACHE_READ_HITL2CACHE_READ_MISSL2CACHE_EVICTL2CACHE_SET_TAG_WRITEL2CACHE_SET_TAG_READMEM_BYTE_READMEM_BYTE_WRITEMEM_HWORD_READMEM_HWORD_WRITEMEM_WORD_READMEM_WORD_WRITEMEM_DWORD_READMEM_DWORD_WRITEMEM_CAP_READMEM_CAP_WRITEMEM_CAP_READ_TAG_SETMEM_CAP_WRITE_TAG_SETTAGCACHE_WRITE_HITTAGCACHE_WRITE_MISSTAGCACHE_READ_HITTAGCACHE_READ_MISSTAGCACHE_EVICTL2CACHEMASTER_READ_REQL2CACHEMASTER_WRITE_REQL2CACHEMASTER_WRITE_REQ_FLITL2CACHEMASTER_READ_RSPL2CACHEMASTER_READ_RSP_FLITL2CACHEMASTER_WRITE_RSPTAGCACHEMASTER_READ_REQTAGCACHEMASTER_WRITE_REQTAGCACHEMASTER_WRITE_REQ_FLITTAGCACHEMASTER_READ_RSPTAGCACHEMASTER_READ_RSP_FLITTAGCACHEMASTER_WRITE_RSPBRANCH_COMPLETEDBRANCH_MISPREDRETURNRETURN_MISPREDRETURN_NOT_31RETURN_NOTPREDITLB_ACCESSDTLB_ACCESSJTLB_IACCESSJTLB_IMISSJTLB_DACCESSJTLB_DMISSDC_LOADSTOREDC_WRITEBACKSTORE_MISSLOAD_MISSINTEGER_COMPLETEDFP_COMPLETEDLOAD_COMPLETEDSTORE_COMPLETEDBARRIER_COMPLETEDMIPS16_COMPLETEDNOP_COMPLETEDINTEGER_MULDIV_COMPLETEDRF_STALLINSTR_REFETCHSTORE_COND_COMPLETEDSTORE_COND_FAILEDICACHE_REQUESTSICACHE_HITL2_WRITEBACKL2_MISSL2_ERR_CORRECTEDEXCEPTIONSRF_CYCLES_STALLEDIFU_CYCLES_STALLEDALU_CYCLES_STALLEDUNCACHED_LOADUNCACHED_STORECP2_REG_TO_REG_COMPLETEDMFTC_COMPLETEDIC_BLOCKED_CYCLESDC_BLOCKED_CYCLESL2_IMISS_STALL_CYCLESL2_DMISS_STALL_CYCLESDMISS_CYCLESL2_MISS_CYCLESUNCACHED_BLOCK_CYCLESMDU_STALL_CYCLESFPU_STALL_CYCLESCP2_STALL_CYCLESCOREXTEND_STALL_CYCLESISPRAM_STALL_CYCLESDSPRAM_STALL_CYCLESCACHE_STALL_CYCLESLOAD_TO_USE_STALLSBASE_MISPRED_STALLSCPO_READ_STALLSBRANCH_MISPRED_CYCLESIFETCH_BUFFER_FULLFETCH_BUFFER_ALLOCATEDEJTAG_ITRIGGEREJTAG_DTRIGGERFSB_LT_QUARTERFSB_QUARTER_TO_HALFFSB_GT_HALFFSB_FULL_PIPELINE_STALLSLDQ_LT_QUARTERLDQ_QUARTER_TO_HALFLDQ_GT_HALFLDQ_FULL_PIPELINE_STALLSWBB_LT_QUARTERWBB_QUARTER_TO_HALFWBB_GT_HALFWBB_FULL_PIPELINE_STALLSREQUEST_LATENCYREQUEST_COUNTCYCLESPREDICTED_JR_31JR_31_MISPREDICTIONSREDIRECT_STALLSJR_31_NO_PREDICTIONSITLB_ACCESSESITLB_MISSESJTLB_INSN_MISSESICACHE_ACCESSESICACHE_MISSESICACHE_MISS_STALLSUNCACHED_IFETCH_STALLSPDTRACE_BACK_STALLSIFU_REPLAYSKILLED_FETCH_SLOTSIFU_IDU_MISS_PRED_UPSTREAM_CYCLESIFU_IDU_NO_FETCH_CYCLESIFU_IDU_CLOGED_DOWNSTREAM_CYCLESDDQ0_FULL_DR_STALLSDDQ1_FULL_DR_STALLSALCB_FULL_DR_STALLSAGCB_FULL_DR_STALLSCLDQ_FULL_DR_STALLSIODQ_FULL_DR_STALLSALU_EMPTY_CYCLESAGEN_EMPTY_CYCLESALU_OPERANDS_NOT_READY_CYCLESAGEN_OPERANDS_NOT_READY_CYCLESALU_NO_ISSUES_CYCLESAGEN_NO_ISSUES_CYCLESALU_BUBBLE_CYCLESAGEN_BUBBLE_CYCLESSINGLE_ISSUE_CYCLESDUAL_ISSUE_CYCLESOOO_ALU_ISSUE_CYCLESOOO_AGEN_ISSUE_CYCLESJALR_JALR_HB_INSNSDCACHE_LINE_REFILL_REQUESTSDCACHE_LOAD_ACCESSESDCACHE_ACCESSESDCACHE_WRITEBACKSDCACHE_MISSESJTLB_DATA_ACCESSESJTLB_DATA_MISSESLOAD_STORE_REPLAYSVA_TRANSALTION_CORNER_CASESLOAD_STORE_BLOCKED_CYCLESLOAD_STORE_NO_FILL_REQUESTSL2_CACHE_WRITEBACKSL2_CACHE_ACCESSESL2_CACHE_MISSESL2_CACHE_MISS_CYCLESFSB_FULL_STALLSFSB_OVER_50_FULLLDQ_FULL_STALLSLDQ_OVER_50_FULLWBB_FULL_STALLSWBB_OVER_50_FULLLOAD_MISS_CONSUMER_REPLAYSCP1_CP2_LOAD_INSNSJR_NON_31_INSNSMISPREDICTED_JR_31_INSNSBRANCH_INSNSCP1_CP2_COND_BRANCH_INSNSBRANCH_LIKELY_INSNSMISPREDICTED_BRANCH_LIKELY_INSNSCOND_BRANCH_INSNSMISPREDICTED_BRANCH_INSNSINTEGER_INSNSFPU_INSNSLOAD_INSNSSTORE_INSNSJ_JAL_INSNSMIPS16_INSNSNOP_INSNSNT_MUL_DIV_INSNSDSP_INSNSALU_DSP_SATURATION_INSNSDSP_BRANCH_INSNSMDU_DSP_SATURATION_INSNSUNCACHED_LOAD_INSNSUNCACHED_STORE_INSNSEJTAG_INSN_TRIGGERSCP1_BRANCH_MISPREDICTIONSSC_INSNSFAILED_SC_INSNSPREFETCH_INSNSCACHE_HIT_PREFETCH_INSNSNO_INSN_CYCLESLOAD_MISS_INSNSONE_INSN_CYCLESTWO_INSNS_CYCLESGFIFO_BLOCKED_CYCLESCP1_CP2_STORE_INSNSMISPREDICTION_STALLSMISPREDICTED_BRANCH_INSNS_CYCLESEXCEPTIONS_TAKENGRADUATION_REPLAYSCOREEXTEND_EVENTSISPRAM_EVENTSDSPRAM_EVENTSL2_CACHE_SINGLE_BIT_ERRORSSYSTEM_EVENT_0SYSTEM_EVENT_1SYSTEM_EVENT_2SYSTEM_EVENT_3SYSTEM_EVENT_4SYSTEM_EVENT_5SYSTEM_EVENT_6SYSTEM_EVENT_7OCP_ALL_REQUESTSOCP_ALL_CACHEABLE_REQUESTSOCP_READ_REQUESTSOCP_READ_CACHEABLE_REQUESTSOCP_WRITE_REQUESTSOCP_WRITE_CACHEABLE_REQUESTSFSB_LESS_25_FULLFSB_25_50_FULLLDQ_LESS_25_FULLLDQ_25_50_FULLWBB_LESS_25_FULLWBB_25_50_FULLCLKISSUERETNISSUESISSUEDISSUEIFIBRBRMISJJMISREPLAYIUNATRAPUULOADUUSTOREULOADUSTOREECMCCCCSRCCFETCHCPREFICAIIIPCIMISSWBUFWDATWBUFLDWBUFFLWBUFTRBADDBADDL2BFILLDDIDSIDIDSDIDNALDSLMLDSIOLDSDMLDSSTSLMSTSIOSTSIOBDMADTLBDTLBADITLBSYNCSYNCIOBSYNCWINSTR_COMPLETEDTLB_BIT_TRANSITIONSINSTR_DISPATCHEDPMON_EXCEPTPMON_SIGVPU_INSTR_COMPLETEDVFPU_INSTR_COMPLETEDVIU1_INSTR_COMPLETEDVIU2_INSTR_COMPLETEDMTVSCR_INSTR_COMPLETEDMTVRSAVE_INSTR_COMPLETEDVPU_INSTR_WAIT_CYCLESVFPU_INSTR_WAIT_CYCLESVIU1_INSTR_WAIT_CYCLESVIU2_INSTR_WAIT_CYCLESMFVSCR_SYNC_CYCLESVSCR_SAT_SETSTORE_INSTR_COMPLETEDL1_INSTR_CACHE_MISSESL1_DATA_SNOOPSUNRESOLVED_BRANCHESSPEC_BUFFER_CYCLESBRANCH_UNIT_STALL_CYCLESTRUE_BRANCH_TARGET_HITSBRANCH_LINK_STAC_PREDICTEDGPR_ISSUE_QUEUE_DISPATCHESCYCLES_THREE_INSTR_DISPATCHEDTHRESHOLD_INSTR_QUEUE_ENTRIES_CYCLESTHRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLESCYCLES_NO_COMPLETED_INSTRSIU2_INSTR_COMPLETEDBRANCHES_COMPLETEDEIEIO_INSTR_COMPLETEDMTSPR_INSTR_COMPLETEDSC_INSTR_COMPLETEDLS_LM_COMPLETEDITLB_HW_TABLE_SEARCH_CYCLESDTLB_HW_SEARCH_CYCLES_OVER_THRESHOLDL1_INSTR_CACHE_ACCESSESINSTR_BKPT_MATCHESL1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLDL1_DATA_SNOOP_HIT_ON_MODIFIEDLOAD_MISS_ALIASLOAD_MISS_ALIAS_ON_TOUCHTOUCH_ALIASL1_DATA_SNOOP_HIT_CASTOUT_QUEUEL1_DATA_SNOOP_HIT_CASTOUTL1_DATA_SNOOP_HITSWRITE_THROUGH_STORESCACHE_INHIBITED_STORESL1_DATA_LOAD_HITL1_DATA_TOUCH_HITL1_DATA_STORE_HITL1_DATA_TOTAL_HITSDST_INSTR_DISPATCHEDREFRESHED_DSTSSUCCESSFUL_DST_TABLE_SEARCHESDSS_INSTR_COMPLETEDDST_STREAM_0_CACHE_LINE_FETCHESVTQ_SUSPENDS_DUE_TO_CTX_CHANGEVTQ_LINE_FETCH_HITVEC_LOAD_INSTR_COMPLETEDFP_STORE_INSTR_COMPLETED_IN_LSUFPU_RENORMALIZATIONFPU_DENORMALIZATIONFP_STORE_CAUSES_STALL_IN_LSULD_ST_TRUE_ALIAS_STALLLSU_INDEXED_ALIAS_STALLLSU_ALIAS_VS_FSQ_WB0_WB1LSU_ALIAS_VS_CSQLSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1LSU_TOUCH_ALIAS_VS_CSQLSU_LMQ_FULL_STALLFP_LOAD_INSTR_COMPLETED_IN_LSUFP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSUFP_LOAD_DOUBLE_COMPLETED_IN_LSULSU_RA_LATCH_STALLLSU_LOAD_VS_STORE_QUEUE_ALIAS_STALLLSU_LMQ_INDEX_ALIASLSU_STORE_QUEUE_INDEX_ALIASLSU_CSQ_FORWARDINGLSU_MISALIGNED_LOAD_FINISHLSU_MISALIGN_STORE_COMPLETEDLSU_MISALIGN_STALLFP_ONE_QUARTER_FPSCR_RENAMES_BUSYFP_ONE_HALF_FPSCR_RENAMES_BUSYFP_THREE_QUARTERS_FPSCR_RENAMES_BUSYFP_ALL_FPSCR_RENAMES_BUSYFP_DENORMALIZED_RESULTL1_DATA_TOTAL_MISSESDISPATCHES_TO_FPR_ISSUE_QUEUELSU_INSTR_COMPLETEDLOAD_INSTR_COMPLETEDSS_SM_INSTR_COMPLETEDTLBIE_INSTR_COMPLETEDLWARX_INSTR_COMPLETEDMFSPR_INSTR_COMPLETEDREFETCH_SERIALIZATIONCOMPLETION_QUEUE_ENTRIES_OVER_THRESHOLDCYCLES_ONE_INSTR_DISPATCHEDCYCLES_TWO_INSTR_COMPLETEDITLB_NON_SPECULATIVE_MISSESCYCLES_WAITING_FROM_L1_INSTR_CACHE_MISSL1_DATA_LOAD_ACCESS_MISSL1_DATA_TOUCH_MISSL1_DATA_STORE_MISSL1_DATA_TOUCH_MISS_CYCLESL1_DATA_CYCLES_USEDDST_STREAM_1_CACHE_LINE_FETCHESVTQ_STREAM_CANCELED_PREMATURELYVTQ_RESUMES_DUE_TO_CTX_CHANGEVTQ_LINE_FETCH_MISSVTQ_LINE_FETCHTLBIE_SNOOPSL1_INSTR_CACHE_RELOADSL1_DATA_CACHE_RELOADSL1_DATA_CACHE_CASTOUTS_TO_L2STORE_MERGE_GATHERCACHEABLE_STORE_MERGE_TO_32_BYTESDATA_BKPT_MATCHESFALL_THROUGH_BRANCHES_PROCESSEDFIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYSECOND_SPECULATION_BUFFER_ACTIVEBPU_STALL_ON_LR_DEPENDENCYBTIC_MISSBRANCH_LINK_STACK_CORRECTLY_RESOLVEDFPR_ISSUE_STALLEDSWITCHES_BETWEEN_PRIV_USERLSU_COMPLETES_FP_STORE_SINGLEVR_ISSUE_QUEUE_DISPATCHESVR_STALLSGPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLDFPR_ISSUE_QUEUE_ENTRIESFPU_INSTR_COMPLETEDSTWCX_INSTR_COMPLETEDLS_LM_INSTR_PIECESITLB_HW_SEARCH_CYCLES_OVER_THRESHOLDDTLB_MISSESCANCELLED_L1_INSTR_CACHE_MISSESL1_DATA_CACHE_OP_HITL1_DATA_LOAD_MISS_CYCLESL1_DATA_PUSHESL1_DATA_TOTAL_MISSVT2_FETCHESTAKEN_BRANCHES_PROCESSEDBRANCH_FLUSHESSECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYTHIRD_SPECULATION_BUFFER_ACTIVEBRANCH_UNIT_STALL_ON_CTR_DEPENDENCYFAST_BTIC_HITBRANCH_LINK_STACK_MISPREDICTEDCYCLES_THREE_INSTR_COMPLETEDCYCLES_NO_INSTR_DISPATCHEDGPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLDGPR_ISSUE_QUEUE_STALLEDIU1_INSTR_COMPLETEDDSSALL_INSTR_COMPLETEDTLBSYNC_INSTR_COMPLETEDSYNC_INSTR_COMPLETEDSS_SM_INSTR_PIECESDTLB_HW_SEARCH_CYCLESSNOOP_RETRIESSUCCESSFUL_STWCXDST_STREAM_3_CACHE_LINE_FETCHESTHIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYMISPREDICTED_BRANCHESFOLDED_BRANCHESFP_STORE_DOUBLE_COMPLETES_IN_LSUL2_CACHE_HITSL3_CACHE_HITSL2_INSTR_CACHE_MISSESL3_INSTR_CACHE_MISSESL2_DATA_CACHE_MISSESL3_DATA_CACHE_MISSESL2_LOAD_HITSL2_STORE_HITSL3_LOAD_HITSL3_STORE_HITSL2_TOUCH_HITSL3_TOUCH_HITSSNOOP_MODIFIEDSNOOP_VALIDINTERVENTIONL3_CACHE_MISSESL2_CACHE_CASTOUTSL3_CACHE_CASTOUTSL2SQ_FULL_CYCLESL3SQ_FULL_CYCLESRAQ_FULL_CYCLESWAQ_FULL_CYCLESL1_EXTERNAL_INTERVENTIONSL2_EXTERNAL_INTERVENTIONSL3_EXTERNAL_INTERVENTIONSEXTERNAL_INTERVENTIONSEXTERNAL_PUSHESEXTERNAL_SNOOP_RETRYDTQ_FULL_CYCLESBUS_RETRYL2_VALID_REQUESTBORDQ_FULLBUS_TAS_FOR_READSBUS_TAS_FOR_WRITESBUS_READS_NOT_RETRIEDBUS_WRITES_NOT_RETRIEDBUS_READS_WRITES_NOT_RETRIEDBUS_RETRY_DUE_TO_L1_RETRYBUS_RETRY_DUE_TO_PREVIOUS_ADJACENTBUS_RETRY_DUE_TO_COLLISIONBUS_RETRY_DUE_TO_INTERVENTION_ORDERINGSNOOP_REQUESTSPREFETCH_ENGINE_REQUESTPREFETCH_ENGINE_COLLISION_VS_LOADPREFETCH_ENGINE_COLLISION_VS_STOREPREFETCH_ENGINE_COLLISION_VS_INSTR_FETCHPREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCHPREFETCH_ENGINE_FULLMARKED_GROUP_DISPATCHMARKED_STORE_COMPLETEDGCT_EMPTYRUN_CYCLESOVERFLOWTHRESHOLD_TIMEOUTGROUP_DISPATCHBR_MARKED_INSTR_FINISHGCT_EMPTY_BY_SRQ_FULLSTOP_COMPLETIONLSU_EMPTYMARKED_STORE_WITH_INTRCYCLES_IN_SUPERVPU_MARKED_INSTR_COMPLETEDFXU0_IDLE_FXU1_BUSYSRQ_EMPTYMARKED_GROUP_COMPLETEDCR_MARKED_INSTR_FINISHDISPATCH_SUCCESSFXU0_IDLE_FXU1_IDLEONE_PLUS_INSTR_COMPLETEDGROUP_MARKED_IDUMARKED_GROUP_COMPLETE_TIMEOUTFXU0_BUSY_FXU1_BUSYMARKED_STORE_SENT_TO_STSFXU_MARKED_INSTR_FINISHEDMARKED_GROUP_ISSUEDFXU0_BUSY_FXU1_IDLEGROUP_COMPLETEDFPU_MARKED_INSTR_COMPLETEDMARKED_INSTR_FINISH_ANY_UNITGROUP_DISPATCH_REJECTLSU_MARKED_INSTR_FINISHTIMEBASE_EVENTLSU_COMPLETION_STALLFXU_COMPLETION_STALLDCACHE_MISS_COMPLETION_STALLFPU_COMPLETION_STALLFXU_LONG_INSTR_COMPLETION_STALLREJECT_COMPLETION_STALLFPU_LONG_INSTR_COMPLETION_STALLGCT_EMPTY_BY_ICACHE_MISSREJECT_COMPLETION_STALL_ERAT_MISSGCT_EMPTY_BY_BRANCH_MISS_PREDICTBUS_HIGHBUS_LOWADDERCYCLES_WITH_INSTRS_COMPLETEDERAT_INSTR_MISSCYCLES_IDLECYCLES_WITH_ANY_THREAD_RUNNINGCYCLES_RUNNINGERAT_DATA_MISSBRANCH_TAKENL1_INSTR_MISSL2_LOAD_MISSSTORE_NO_REAL_ADDRINSTR_COMPLETED_WITH_ALL_THREADS_RUNNINGL1_LOAD_MISSL3_INSTR_MISSTLB_DATA_MISSL3_LOAD_MISSLOAD_NO_REAL_ADDRCYCLES_WITH_INSTRS_DISPATCHEDCYCLES_RUNNING_PURR_INCBRANCH_MISPREDICTEDPREFETCHED_INSTRS_DISCARDEDINSTR_COMPLETED_RUNNINGTLB_INSTR_MISSCACHE_LOAD_MISSUOPS_COMPLETEDINSTR_FETCHEDUOPS_DECODEDPM_EVENT_TRANSITIONSPM_EVENT_CYCLESBRANCH_INSTRS_COMPLETEDLOAD_UOPS_COMPLETEDSTORE_UOPS_COMPLETEDCQ_REDIRECTSBRANCHES_FINISHEDTAKEN_BRANCHES_FINISHEDFINISHED_UNCOND_BRANCHES_MISS_BTBBTB_BRANCH_MISPRED_FROM_DIRECTIONBTB_HITS_PSEUDO_HITSCYCLES_DECODE_STALLEDCYCLES_ISSUE_STALLEDCYCLES_BRANCH_ISSUE_STALLEDCYCLES_SU1_SCHED_STALLEDCYCLES_SU2_SCHED_STALLEDCYCLES_MU_SCHED_STALLEDCYCLES_LRU_SCHED_STALLEDCYCLES_BU_SCHED_STALLEDTOTAL_TRANSLATEDLOADS_TRANSLATEDSTORES_TRANSLATEDTOUCHES_TRANSLATEDCACHEOPS_TRANSLATEDCACHE_INHIBITED_ACCESS_TRANSLATEDGUARDED_LOADS_TRANSLATEDWRITE_THROUGH_STORES_TRANSLATEDMISALIGNED_LOAD_STORE_ACCESS_TRANSLATEDTOTAL_ALLOCATED_TO_DLFBLOADS_TRANSLATED_ALLOCATED_TO_DLFBSTORES_COMPLETED_ALLOCATED_TO_DLFBTOUCHES_TRANSLATED_ALLOCATED_TO_DLFBSTORES_COMPLETEDDATA_L1_CACHE_LOCKSDATA_L1_CACHE_RELOADSDATA_L1_CACHE_CASTOUTSLOAD_MISS_DLFB_FULLLOAD_MISS_LDQ_FULLLOAD_GUARDED_MISSSTORE_TRANSLATE_WHEN_QUEUE_FULLADDRESS_COLLISIONDATA_MMU_MISSDATA_MMU_BUSYPART2_MISALIGNED_CACHE_ACCESSLOAD_MISS_DLFB_FULL_CYCLESLOAD_MISS_LDQ_FULL_CYCLESLOAD_GUARDED_MISS_CYCLESSTORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLESADDRESS_COLLISION_CYCLESDATA_MMU_MISS_CYCLESDATA_MMU_BUSY_CYCLESPART2_MISALIGNED_CACHE_ACCESS_CYCLESINSTR_L1_CACHE_LOCKSINSTR_L1_CACHE_RELOADSINSTR_L1_CACHE_FETCHESINSTR_MMU_TLB4K_RELOADSINSTR_MMU_VSP_RELOADSDATA_MMU_TLB4K_RELOADSDATA_MMU_VSP_RELOADSL2MMU_MISSESBIU_MASTER_REQUESTSBIU_MASTER_INSTR_SIDE_REQUESTSBIU_MASTER_DATA_SIDE_REQUESTSBIU_MASTER_DATA_SIDE_CASTOUT_REQUESTSBIU_MASTER_RETRIESSNOOP_HITSSNOOP_PUSHESDLFB_LOAD_MISS_CYCLESILFB_FETCH_MISS_CYCLESEXT_INPU_INTR_LATENCY_CYCLESCRIT_INPUT_INTR_LATENCY_CYCLESEXT_INPUT_INTR_PENDING_LATENCY_CYCLESCRIT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC0_OVERFLOWPMC1_OVERFLOWPMC2_OVERFLOWPMC3_OVERFLOWINTERRUPTS_TAKENEXT_INPUT_INTR_TAKENCRIT_INPUT_INTR_TAKENSYSCALL_TRAP_INTRL2_LINEFILL_BUFFERLV2_VSCASTOUTS_RELEASEDINTV_ALLOCATIONSDLFB_RETRIES_TO_MBARSTORE_RETRIESSTASH_L1_HITSSTASH_L2_HITSSTASH_BUSY_1STASH_BUSY_2STASH_BUSY_3STASH_HITSSTASH_HIT_DLFBSTASH_REQUESTSSTASH_REQUESTS_L1STASH_REQUESTS_L2STALLS_NO_CAQ_OR_COBL2_HIT_CACHE_ACCESSESL2_CACHE_DATA_ACCESSESL2_CACHE_DATA_HITSL2_CACHE_INSTR_ACCESSESL2_CACHE_INSTR_HITSL2_CACHE_ALLOCATIONSL2_CACHE_DATA_ALLOCATIONSL2_CACHE_DIRTY_DATA_ALLOCATIONSL2_CACHE_INSTR_ALLOCATIONSL2_CACHE_UPDATESL2_CACHE_CLEAN_UPDATESL2_CACHE_DIRTY_UPDATESL2_CACHE_CLEAN_REDUNDANT_UPDATESL2_CACHE_DIRTY_REDUNDANT_UPDATESL2_CACHE_LOCKSL2_CACHE_DATA_DIRTY_HITSINSTR_LFB_WENT_HIGH_PRIORITYSNOOP_THROTTLING_TURNED_ONL2_CLEAN_LINE_INVALIDATIONSL2_INCOHERENT_LINE_INVALIDATIONSL2_COHERENT_LINE_INVALIDATIONSCOHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHESIAC1S_DETECTEDIAC2S_DETECTEDDAC1S_DTECTEDDAC2S_DTECTEDDVT0_DETECTEDDVT1_DETECTEDDVT2_DETECTEDDVT3_DETECTEDDVT4_DETECTEDDVT5_DETECTEDDVT6_DETECTEDDVT7_DETECTEDCYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULLFPU_DOUBLE_PUMPFPU_FINISHFPU_DIVIDE_CYCLESFPU_DENORM_INPUT_CYCLESFPU_RESULT_STALL_CYCLESFPU_FPSCR_FULL_STALLFPU_PIPE_SYNC_STALLSFPU_INPUT_DATA_STALLSDECORATED_LOADSDECORATED_STORESLOAD_RETRIESSTWCX_SUCCESSESSTWCX_FAILURESSOFT-TSC-branchesk8-fr-retired-taken-branchesbranch-mispredictsk8-fr-retired-taken-branches-mispredictedcyclestscdc-missesk8-dc-missic-missesk8-ic-missinstructionsk8-fr-retired-x86-instructionsinterruptsk8-fr-taken-hardware-interruptsunhalted-cyclesk8-bu-cpu-clk-unhaltedK8-count=edgeinvmask=osusradd-pipe-excluding-junk-opsmultiply-pipe-excluding-junk-opsstore-pipe-excluding-junk-opsadd-pipe-junk-opsmultiply-pipe-junk-opsstore-pipe-junk-opsescsssdsfsgshslocked-instructionscycles-in-requestcycles-to-completeinvalidsharedexclusiveownermodifiedscrubberpiggybackloadst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intPMC_EV_TSC__BLOCK_STARTPMC_EV_TSC_TSCPMC_EV_IAF__BLOCK_STARTPMC_EV_IAF_INSTR_RETIRED_ANYPMC_EV_IAF_CPU_CLK_UNHALTED_COREPMC_EV_IAF_CPU_CLK_UNHALTED_REFPMC_EV_K7__BLOCK_STARTPMC_EV_K7_DC_ACCESSESPMC_EV_K7_DC_MISSESPMC_EV_K7_DC_REFILLS_FROM_L2PMC_EV_K7_DC_REFILLS_FROM_SYSTEMPMC_EV_K7_DC_WRITEBACKSPMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITSPMC_EV_K7_L1_AND_L2_DTLB_MISSESPMC_EV_K7_MISALIGNED_REFERENCESPMC_EV_K7_IC_FETCHESPMC_EV_K7_IC_MISSESPMC_EV_K7_L1_ITLB_MISSESPMC_EV_K7_L1_L2_ITLB_MISSESPMC_EV_K7_RETIRED_INSTRUCTIONSPMC_EV_K7_RETIRED_OPSPMC_EV_K7_RETIRED_BRANCHESPMC_EV_K7_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_TAKEN_BRANCHESPMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K7_RETIRED_RESYNC_BRANCHESPMC_EV_K7_INTERRUPTS_MASKED_CYCLESPMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K7_HARDWARE_INTERRUPTSPMC_EV_K8__BLOCK_STARTPMC_EV_K8_FP_DISPATCHED_FPU_OPSPMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIREDPMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPSPMC_EV_K8_LS_SEGMENT_REGISTER_LOADPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODEPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_LS_BUFFER2_FULLPMC_EV_K8_LS_LOCKED_OPERATIONPMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONSPMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONSPMC_EV_K8_DC_ACCESSPMC_EV_K8_DC_MISSPMC_EV_K8_DC_REFILL_FROM_L2PMC_EV_K8_DC_REFILL_FROM_SYSTEMPMC_EV_K8_DC_COPYBACKPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HITPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISSPMC_EV_K8_DC_MISALIGNED_DATA_REFERENCEPMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCELPMC_EV_K8_DC_ONE_BIT_ECC_ERRORPMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONSPMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKSPMC_EV_K8_BU_CPU_CLK_UNHALTEDPMC_EV_K8_BU_INTERNAL_L2_REQUESTPMC_EV_K8_BU_FILL_REQUEST_L2_MISSPMC_EV_K8_BU_FILL_INTO_L2PMC_EV_K8_IC_FETCHPMC_EV_K8_IC_MISSPMC_EV_K8_IC_REFILL_FROM_L2PMC_EV_K8_IC_REFILL_FROM_SYSTEMPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HITPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISSPMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_IC_INSTRUCTION_FETCH_STALLPMC_EV_K8_IC_RETURN_STACK_HITPMC_EV_K8_IC_RETURN_STACK_OVERFLOWPMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_UOPSPMC_EV_K8_FR_RETIRED_BRANCHESPMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHESPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K8_FR_RETIRED_RESYNCSPMC_EV_K8_FR_RETIRED_NEAR_RETURNSPMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPAREPMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSPMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLESPMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTSPMC_EV_K8_FR_DECODER_EMPTYPMC_EV_K8_FR_DISPATCH_STALLSPMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIREPMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATIONPMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOADPMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIETPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDINGPMC_EV_K8_FR_FPU_EXCEPTIONSPMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENTPMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWPMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDPMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUNDPMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATIONPMC_EV_K8_NB_SIZED_COMMANDSPMC_EV_K8_NB_PROBE_RESULTPMC_EV_K8_NB_HT_BUS0_BANDWIDTHPMC_EV_K8_NB_HT_BUS1_BANDWIDTHPMC_EV_K8_NB_HT_BUS2_BANDWIDTHPMC_EV_MIPS24K__BLOCK_STARTPMC_EV_MIPS24K_CYCLEPMC_EV_MIPS24K_INSTR_EXECUTEDPMC_EV_MIPS24K_BRANCH_COMPLETEDPMC_EV_MIPS24K_BRANCH_MISPREDPMC_EV_MIPS24K_RETURNPMC_EV_MIPS24K_RETURN_MISPREDPMC_EV_MIPS24K_RETURN_NOT_31PMC_EV_MIPS24K_RETURN_NOTPREDPMC_EV_MIPS24K_ITLB_ACCESSPMC_EV_MIPS24K_ITLB_MISSPMC_EV_MIPS24K_DTLB_ACCESSPMC_EV_MIPS24K_DTLB_MISSPMC_EV_MIPS24K_JTLB_IACCESSPMC_EV_MIPS24K_JTLB_IMISSPMC_EV_MIPS24K_JTLB_DACCESSPMC_EV_MIPS24K_JTLB_DMISSPMC_EV_MIPS24K_IC_FETCHPMC_EV_MIPS24K_IC_MISSPMC_EV_MIPS24K_DC_LOADSTOREPMC_EV_MIPS24K_DC_WRITEBACKPMC_EV_MIPS24K_DC_MISSPMC_EV_MIPS24K_STORE_MISSPMC_EV_MIPS24K_LOAD_MISSPMC_EV_MIPS24K_INTEGER_COMPLETEDPMC_EV_MIPS24K_FP_COMPLETEDPMC_EV_MIPS24K_LOAD_COMPLETEDPMC_EV_MIPS24K_STORE_COMPLETEDPMC_EV_MIPS24K_BARRIER_COMPLETEDPMC_EV_MIPS24K_MIPS16_COMPLETEDPMC_EV_MIPS24K_NOP_COMPLETEDPMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETEDPMC_EV_MIPS24K_RF_STALLPMC_EV_MIPS24K_INSTR_REFETCHPMC_EV_MIPS24K_STORE_COND_COMPLETEDPMC_EV_MIPS24K_STORE_COND_FAILEDPMC_EV_MIPS24K_ICACHE_REQUESTSPMC_EV_MIPS24K_ICACHE_HITPMC_EV_MIPS24K_L2_WRITEBACKPMC_EV_MIPS24K_L2_ACCESSPMC_EV_MIPS24K_L2_MISSPMC_EV_MIPS24K_L2_ERR_CORRECTEDPMC_EV_MIPS24K_EXCEPTIONSPMC_EV_MIPS24K_RF_CYCLES_STALLEDPMC_EV_MIPS24K_IFU_CYCLES_STALLEDPMC_EV_MIPS24K_ALU_CYCLES_STALLEDPMC_EV_MIPS24K_UNCACHED_LOADPMC_EV_MIPS24K_UNCACHED_STOREPMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETEDPMC_EV_MIPS24K_MFTC_COMPLETEDPMC_EV_MIPS24K_IC_BLOCKED_CYCLESPMC_EV_MIPS24K_DC_BLOCKED_CYCLESPMC_EV_MIPS24K_L2_IMISS_STALL_CYCLESPMC_EV_MIPS24K_L2_DMISS_STALL_CYCLESPMC_EV_MIPS24K_DMISS_CYCLESPMC_EV_MIPS24K_L2_MISS_CYCLESPMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLESPMC_EV_MIPS24K_MDU_STALL_CYCLESPMC_EV_MIPS24K_FPU_STALL_CYCLESPMC_EV_MIPS24K_CP2_STALL_CYCLESPMC_EV_MIPS24K_COREXTEND_STALL_CYCLESPMC_EV_MIPS24K_ISPRAM_STALL_CYCLESPMC_EV_MIPS24K_DSPRAM_STALL_CYCLESPMC_EV_MIPS24K_CACHE_STALL_CYCLESPMC_EV_MIPS24K_LOAD_TO_USE_STALLSPMC_EV_MIPS24K_BASE_MISPRED_STALLSPMC_EV_MIPS24K_CPO_READ_STALLSPMC_EV_MIPS24K_BRANCH_MISPRED_CYCLESPMC_EV_MIPS24K_IFETCH_BUFFER_FULLPMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATEDPMC_EV_MIPS24K_EJTAG_ITRIGGERPMC_EV_MIPS24K_EJTAG_DTRIGGERPMC_EV_MIPS24K_FSB_LT_QUARTERPMC_EV_MIPS24K_FSB_QUARTER_TO_HALFPMC_EV_MIPS24K_FSB_GT_HALFPMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_LDQ_LT_QUARTERPMC_EV_MIPS24K_LDQ_QUARTER_TO_HALFPMC_EV_MIPS24K_LDQ_GT_HALFPMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_WBB_LT_QUARTERPMC_EV_MIPS24K_WBB_QUARTER_TO_HALFPMC_EV_MIPS24K_WBB_GT_HALFPMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_REQUEST_LATENCYPMC_EV_MIPS24K_REQUEST_COUNTPMC_EV_OCTEON__BLOCK_STARTPMC_EV_OCTEON_CLKPMC_EV_OCTEON_ISSUEPMC_EV_OCTEON_RETPMC_EV_OCTEON_NISSUEPMC_EV_OCTEON_SISSUEPMC_EV_OCTEON_DISSUEPMC_EV_OCTEON_IFIPMC_EV_OCTEON_BRPMC_EV_OCTEON_BRMISPMC_EV_OCTEON_JPMC_EV_OCTEON_JMISPMC_EV_OCTEON_REPLAYPMC_EV_OCTEON_IUNAPMC_EV_OCTEON_TRAPPMC_EV_OCTEON_UULOADPMC_EV_OCTEON_UUSTOREPMC_EV_OCTEON_ULOADPMC_EV_OCTEON_USTOREPMC_EV_OCTEON_ECPMC_EV_OCTEON_MCPMC_EV_OCTEON_CCPMC_EV_OCTEON_CSRCPMC_EV_OCTEON_CFETCHPMC_EV_OCTEON_CPREFPMC_EV_OCTEON_ICAPMC_EV_OCTEON_IIPMC_EV_OCTEON_IPPMC_EV_OCTEON_CIMISSPMC_EV_OCTEON_WBUFPMC_EV_OCTEON_WDATPMC_EV_OCTEON_WBUFLDPMC_EV_OCTEON_WBUFFLPMC_EV_OCTEON_WBUFTRPMC_EV_OCTEON_BADDPMC_EV_OCTEON_BADDL2PMC_EV_OCTEON_BFILLPMC_EV_OCTEON_DDIDSPMC_EV_OCTEON_IDIDSPMC_EV_OCTEON_DIDNAPMC_EV_OCTEON_LDSPMC_EV_OCTEON_LMLDSPMC_EV_OCTEON_IOLDSPMC_EV_OCTEON_DMLDSPMC_EV_OCTEON_STSPMC_EV_OCTEON_LMSTSPMC_EV_OCTEON_IOSTSPMC_EV_OCTEON_IOBDMAPMC_EV_OCTEON_DTLBPMC_EV_OCTEON_DTLBADPMC_EV_OCTEON_ITLBPMC_EV_OCTEON_SYNCPMC_EV_OCTEON_SYNCIOBPMC_EV_OCTEON_SYNCWPMC_EV_MIPS74K__BLOCK_STARTPMC_EV_MIPS74K_CYCLESPMC_EV_MIPS74K_INSTR_EXECUTEDPMC_EV_MIPS74K_PREDICTED_JR_31PMC_EV_MIPS74K_JR_31_MISPREDICTIONSPMC_EV_MIPS74K_REDIRECT_STALLSPMC_EV_MIPS74K_JR_31_NO_PREDICTIONSPMC_EV_MIPS74K_ITLB_ACCESSESPMC_EV_MIPS74K_ITLB_MISSESPMC_EV_MIPS74K_JTLB_INSN_MISSESPMC_EV_MIPS74K_ICACHE_ACCESSESPMC_EV_MIPS74K_ICACHE_MISSESPMC_EV_MIPS74K_ICACHE_MISS_STALLSPMC_EV_MIPS74K_UNCACHED_IFETCH_STALLSPMC_EV_MIPS74K_PDTRACE_BACK_STALLSPMC_EV_MIPS74K_IFU_REPLAYSPMC_EV_MIPS74K_KILLED_FETCH_SLOTSPMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLESPMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLESPMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLESPMC_EV_MIPS74K_DDQ0_FULL_DR_STALLSPMC_EV_MIPS74K_DDQ1_FULL_DR_STALLSPMC_EV_MIPS74K_ALCB_FULL_DR_STALLSPMC_EV_MIPS74K_AGCB_FULL_DR_STALLSPMC_EV_MIPS74K_CLDQ_FULL_DR_STALLSPMC_EV_MIPS74K_IODQ_FULL_DR_STALLSPMC_EV_MIPS74K_ALU_EMPTY_CYCLESPMC_EV_MIPS74K_AGEN_EMPTY_CYCLESPMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLESPMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLESPMC_EV_MIPS74K_ALU_BUBBLE_CYCLESPMC_EV_MIPS74K_AGEN_BUBBLE_CYCLESPMC_EV_MIPS74K_SINGLE_ISSUE_CYCLESPMC_EV_MIPS74K_DUAL_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLESPMC_EV_MIPS74K_JALR_JALR_HB_INSNSPMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTSPMC_EV_MIPS74K_DCACHE_LOAD_ACCESSESPMC_EV_MIPS74K_DCACHE_ACCESSESPMC_EV_MIPS74K_DCACHE_WRITEBACKSPMC_EV_MIPS74K_DCACHE_MISSESPMC_EV_MIPS74K_JTLB_DATA_ACCESSESPMC_EV_MIPS74K_JTLB_DATA_MISSESPMC_EV_MIPS74K_LOAD_STORE_REPLAYSPMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASESPMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLESPMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTSPMC_EV_MIPS74K_L2_CACHE_WRITEBACKSPMC_EV_MIPS74K_L2_CACHE_ACCESSESPMC_EV_MIPS74K_L2_CACHE_MISSESPMC_EV_MIPS74K_L2_CACHE_MISS_CYCLESPMC_EV_MIPS74K_FSB_FULL_STALLSPMC_EV_MIPS74K_FSB_OVER_50_FULLPMC_EV_MIPS74K_LDQ_FULL_STALLSPMC_EV_MIPS74K_LDQ_OVER_50_FULLPMC_EV_MIPS74K_WBB_FULL_STALLSPMC_EV_MIPS74K_WBB_OVER_50_FULLPMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYSPMC_EV_MIPS74K_CP1_CP2_LOAD_INSNSPMC_EV_MIPS74K_JR_NON_31_INSNSPMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNSPMC_EV_MIPS74K_BRANCH_INSNSPMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNSPMC_EV_MIPS74K_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_COND_BRANCH_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNSPMC_EV_MIPS74K_INTEGER_INSNSPMC_EV_MIPS74K_FPU_INSNSPMC_EV_MIPS74K_LOAD_INSNSPMC_EV_MIPS74K_STORE_INSNSPMC_EV_MIPS74K_J_JAL_INSNSPMC_EV_MIPS74K_MIPS16_INSNSPMC_EV_MIPS74K_NOP_INSNSPMC_EV_MIPS74K_NT_MUL_DIV_INSNSPMC_EV_MIPS74K_DSP_INSNSPMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_DSP_BRANCH_INSNSPMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_UNCACHED_LOAD_INSNSPMC_EV_MIPS74K_UNCACHED_STORE_INSNSPMC_EV_MIPS74K_EJTAG_INSN_TRIGGERSPMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONSPMC_EV_MIPS74K_SC_INSNSPMC_EV_MIPS74K_FAILED_SC_INSNSPMC_EV_MIPS74K_PREFETCH_INSNSPMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNSPMC_EV_MIPS74K_NO_INSN_CYCLESPMC_EV_MIPS74K_LOAD_MISS_INSNSPMC_EV_MIPS74K_ONE_INSN_CYCLESPMC_EV_MIPS74K_TWO_INSNS_CYCLESPMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLESPMC_EV_MIPS74K_CP1_CP2_STORE_INSNSPMC_EV_MIPS74K_MISPREDICTION_STALLSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLESPMC_EV_MIPS74K_EXCEPTIONS_TAKENPMC_EV_MIPS74K_GRADUATION_REPLAYSPMC_EV_MIPS74K_COREEXTEND_EVENTSPMC_EV_MIPS74K_ISPRAM_EVENTSPMC_EV_MIPS74K_DSPRAM_EVENTSPMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORSPMC_EV_MIPS74K_SYSTEM_EVENT_0PMC_EV_MIPS74K_SYSTEM_EVENT_1PMC_EV_MIPS74K_SYSTEM_EVENT_2PMC_EV_MIPS74K_SYSTEM_EVENT_3PMC_EV_MIPS74K_SYSTEM_EVENT_4PMC_EV_MIPS74K_SYSTEM_EVENT_5PMC_EV_MIPS74K_SYSTEM_EVENT_6PMC_EV_MIPS74K_SYSTEM_EVENT_7PMC_EV_MIPS74K_OCP_ALL_REQUESTSPMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_READ_REQUESTSPMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTSPMC_EV_MIPS74K_FSB_LESS_25_FULLPMC_EV_MIPS74K_FSB_25_50_FULLPMC_EV_MIPS74K_LDQ_LESS_25_FULLPMC_EV_MIPS74K_LDQ_25_50_FULLPMC_EV_MIPS74K_WBB_LESS_25_FULLPMC_EV_MIPS74K_WBB_25_50_FULLPMC_EV_BERI__BLOCK_STARTPMC_EV_BERI_CYCLEPMC_EV_BERI_INSTPMC_EV_BERI_INST_USERPMC_EV_BERI_INST_KERNELPMC_EV_BERI_IMPRECISE_SETBOUNDSPMC_EV_BERI_UNREPRESENTABLE_CAPSPMC_EV_BERI_ITLB_MISSPMC_EV_BERI_DTLB_MISSPMC_EV_BERI_ICACHE_WRITE_HITPMC_EV_BERI_ICACHE_WRITE_MISSPMC_EV_BERI_ICACHE_READ_HITPMC_EV_BERI_ICACHE_READ_MISSPMC_EV_BERI_ICACHE_EVICTPMC_EV_BERI_DCACHE_WRITE_HITPMC_EV_BERI_DCACHE_WRITE_MISSPMC_EV_BERI_DCACHE_READ_HITPMC_EV_BERI_DCACHE_READ_MISSPMC_EV_BERI_DCACHE_EVICTPMC_EV_BERI_DCACHE_SET_TAG_WRITEPMC_EV_BERI_DCACHE_SET_TAG_READPMC_EV_BERI_L2CACHE_WRITE_HITPMC_EV_BERI_L2CACHE_WRITE_MISSPMC_EV_BERI_L2CACHE_READ_HITPMC_EV_BERI_L2CACHE_READ_MISSPMC_EV_BERI_L2CACHE_EVICTPMC_EV_BERI_L2CACHE_SET_TAG_WRITEPMC_EV_BERI_L2CACHE_SET_TAG_READPMC_EV_BERI_MEM_BYTE_READPMC_EV_BERI_MEM_BYTE_WRITEPMC_EV_BERI_MEM_HWORD_READPMC_EV_BERI_MEM_HWORD_WRITEPMC_EV_BERI_MEM_WORD_READPMC_EV_BERI_MEM_WORD_WRITEPMC_EV_BERI_MEM_DWORD_READPMC_EV_BERI_MEM_DWORD_WRITEPMC_EV_BERI_MEM_CAP_READPMC_EV_BERI_MEM_CAP_WRITEPMC_EV_BERI_MEM_CAP_READ_TAG_SETPMC_EV_BERI_MEM_CAP_WRITE_TAG_SETPMC_EV_BERI_TAGCACHE_WRITE_HITPMC_EV_BERI_TAGCACHE_WRITE_MISSPMC_EV_BERI_TAGCACHE_READ_HITPMC_EV_BERI_TAGCACHE_READ_MISSPMC_EV_BERI_TAGCACHE_EVICTPMC_EV_BERI_L2CACHEMASTER_READ_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_L2CACHEMASTER_READ_RSPPMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLITPMC_EV_BERI_L2CACHEMASTER_WRITE_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_TAGCACHEMASTER_READ_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLITPMC_EV_BERI_TAGCACHEMASTER_WRITE_RSPPMC_EV_UCP__BLOCK_STARTPMC_EV_UCP_EVENT_0CH_04H_EPMC_EV_UCP_EVENT_0CH_04H_FPMC_EV_UCP_EVENT_0CH_04H_MPMC_EV_UCP_EVENT_0CH_04H_SPMC_EV_UCP_EVENT_0CH_08H_EPMC_EV_UCP_EVENT_0CH_08H_FPMC_EV_UCP_EVENT_0CH_08H_MPMC_EV_UCP_EVENT_0CH_08H_SPMC_EV_PPC7450__BLOCK_STARTPMC_EV_PPC7450_CYCLEPMC_EV_PPC7450_INSTR_COMPLETEDPMC_EV_PPC7450_TLB_BIT_TRANSITIONSPMC_EV_PPC7450_INSTR_DISPATCHEDPMC_EV_PPC7450_PMON_EXCEPTPMC_EV_PPC7450_PMON_SIGPMC_EV_PPC7450_VPU_INSTR_COMPLETEDPMC_EV_PPC7450_VFPU_INSTR_COMPLETEDPMC_EV_PPC7450_VIU1_INSTR_COMPLETEDPMC_EV_PPC7450_VIU2_INSTR_COMPLETEDPMC_EV_PPC7450_MTVSCR_INSTR_COMPLETEDPMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETEDPMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLESPMC_EV_PPC7450_MFVSCR_SYNC_CYCLESPMC_EV_PPC7450_VSCR_SAT_SETPMC_EV_PPC7450_STORE_INSTR_COMPLETEDPMC_EV_PPC7450_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_SNOOPSPMC_EV_PPC7450_UNRESOLVED_BRANCHESPMC_EV_PPC7450_SPEC_BUFFER_CYCLESPMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLESPMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITSPMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHEDPMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRSPMC_EV_PPC7450_IU2_INSTR_COMPLETEDPMC_EV_PPC7450_BRANCHES_COMPLETEDPMC_EV_PPC7450_EIEIO_INSTR_COMPLETEDPMC_EV_PPC7450_MTSPR_INSTR_COMPLETEDPMC_EV_PPC7450_SC_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_COMPLETEDPMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSESPMC_EV_PPC7450_INSTR_BKPT_MATCHESPMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIEDPMC_EV_PPC7450_LOAD_MISS_ALIASPMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCHPMC_EV_PPC7450_TOUCH_ALIASPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUEPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUTPMC_EV_PPC7450_L1_DATA_SNOOP_HITSPMC_EV_PPC7450_WRITE_THROUGH_STORESPMC_EV_PPC7450_CACHE_INHIBITED_STORESPMC_EV_PPC7450_L1_DATA_LOAD_HITPMC_EV_PPC7450_L1_DATA_TOUCH_HITPMC_EV_PPC7450_L1_DATA_STORE_HITPMC_EV_PPC7450_L1_DATA_TOTAL_HITSPMC_EV_PPC7450_DST_INSTR_DISPATCHEDPMC_EV_PPC7450_REFRESHED_DSTSPMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHESPMC_EV_PPC7450_DSS_INSTR_COMPLETEDPMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_HITPMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FPU_RENORMALIZATIONPMC_EV_PPC7450_FPU_DENORMALIZATIONPMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSUPMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALLPMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALLPMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LMQ_FULL_STALLPMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSUPMC_EV_PPC7450_LSU_RA_LATCH_STALLPMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALLPMC_EV_PPC7450_LSU_LMQ_INDEX_ALIASPMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIASPMC_EV_PPC7450_LSU_CSQ_FORWARDINGPMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISHPMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETEDPMC_EV_PPC7450_LSU_MISALIGN_STALLPMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_DENORMALIZED_RESULTPMC_EV_PPC7450_L1_DATA_TOTAL_MISSESPMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUEPMC_EV_PPC7450_LSU_INSTR_COMPLETEDPMC_EV_PPC7450_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_COMPLETEDPMC_EV_PPC7450_TLBIE_INSTR_COMPLETEDPMC_EV_PPC7450_LWARX_INSTR_COMPLETEDPMC_EV_PPC7450_MFSPR_INSTR_COMPLETEDPMC_EV_PPC7450_REFETCH_SERIALIZATIONPMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHEDPMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETEDPMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSESPMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISSPMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISSPMC_EV_PPC7450_L1_DATA_STORE_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_CYCLES_USEDPMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELYPMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_MISSPMC_EV_PPC7450_VTQ_LINE_FETCHPMC_EV_PPC7450_TLBIE_SNOOPSPMC_EV_PPC7450_L1_INSTR_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2PMC_EV_PPC7450_STORE_MERGE_GATHERPMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTESPMC_EV_PPC7450_DATA_BKPT_MATCHESPMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSEDPMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCYPMC_EV_PPC7450_BTIC_MISSPMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVEDPMC_EV_PPC7450_FPR_ISSUE_STALLEDPMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USERPMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLEPMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_VR_STALLSPMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIESPMC_EV_PPC7450_FPU_INSTR_COMPLETEDPMC_EV_PPC7450_STWCX_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_INSTR_PIECESPMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_DTLB_MISSESPMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_CACHE_OP_HITPMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_PUSHESPMC_EV_PPC7450_L1_DATA_TOTAL_MISSPMC_EV_PPC7450_VT2_FETCHESPMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSEDPMC_EV_PPC7450_BRANCH_FLUSHESPMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCYPMC_EV_PPC7450_FAST_BTIC_HITPMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTEDPMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETEDPMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLEDPMC_EV_PPC7450_IU1_INSTR_COMPLETEDPMC_EV_PPC7450_DSSALL_INSTR_COMPLETEDPMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_PIECESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLESPMC_EV_PPC7450_SNOOP_RETRIESPMC_EV_PPC7450_SUCCESSFUL_STWCXPMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHESPMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_MISPREDICTED_BRANCHESPMC_EV_PPC7450_FOLDED_BRANCHESPMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSUPMC_EV_PPC7450_L2_CACHE_HITSPMC_EV_PPC7450_L3_CACHE_HITSPMC_EV_PPC7450_L2_INSTR_CACHE_MISSESPMC_EV_PPC7450_L3_INSTR_CACHE_MISSESPMC_EV_PPC7450_L2_DATA_CACHE_MISSESPMC_EV_PPC7450_L3_DATA_CACHE_MISSESPMC_EV_PPC7450_L2_LOAD_HITSPMC_EV_PPC7450_L2_STORE_HITSPMC_EV_PPC7450_L3_LOAD_HITSPMC_EV_PPC7450_L3_STORE_HITSPMC_EV_PPC7450_L2_TOUCH_HITSPMC_EV_PPC7450_L3_TOUCH_HITSPMC_EV_PPC7450_SNOOP_MODIFIEDPMC_EV_PPC7450_SNOOP_VALIDPMC_EV_PPC7450_INTERVENTIONPMC_EV_PPC7450_L2_CACHE_MISSESPMC_EV_PPC7450_L3_CACHE_MISSESPMC_EV_PPC7450_L2_CACHE_CASTOUTSPMC_EV_PPC7450_L3_CACHE_CASTOUTSPMC_EV_PPC7450_L2SQ_FULL_CYCLESPMC_EV_PPC7450_L3SQ_FULL_CYCLESPMC_EV_PPC7450_RAQ_FULL_CYCLESPMC_EV_PPC7450_WAQ_FULL_CYCLESPMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_PUSHESPMC_EV_PPC7450_EXTERNAL_SNOOP_RETRYPMC_EV_PPC7450_DTQ_FULL_CYCLESPMC_EV_PPC7450_BUS_RETRYPMC_EV_PPC7450_L2_VALID_REQUESTPMC_EV_PPC7450_BORDQ_FULLPMC_EV_PPC7450_BUS_TAS_FOR_READSPMC_EV_PPC7450_BUS_TAS_FOR_WRITESPMC_EV_PPC7450_BUS_READS_NOT_RETRIEDPMC_EV_PPC7450_BUS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRYPMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENTPMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISIONPMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERINGPMC_EV_PPC7450_SNOOP_REQUESTSPMC_EV_PPC7450_PREFETCH_ENGINE_REQUESTPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOADPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STOREPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_FULLPMC_EV_PPC970__BLOCK_STARTPMC_EV_PPC970_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_GROUP_DISPATCHPMC_EV_PPC970_MARKED_STORE_COMPLETEDPMC_EV_PPC970_GCT_EMPTYPMC_EV_PPC970_RUN_CYCLESPMC_EV_PPC970_OVERFLOWPMC_EV_PPC970_CYCLESPMC_EV_PPC970_THRESHOLD_TIMEOUTPMC_EV_PPC970_GROUP_DISPATCHPMC_EV_PPC970_BR_MARKED_INSTR_FINISHPMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULLPMC_EV_PPC970_STOP_COMPLETIONPMC_EV_PPC970_LSU_EMPTYPMC_EV_PPC970_MARKED_STORE_WITH_INTRPMC_EV_PPC970_CYCLES_IN_SUPERPMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_FXU0_IDLE_FXU1_BUSYPMC_EV_PPC970_SRQ_EMPTYPMC_EV_PPC970_MARKED_GROUP_COMPLETEDPMC_EV_PPC970_CR_MARKED_INSTR_FINISHPMC_EV_PPC970_DISPATCH_SUCCESSPMC_EV_PPC970_FXU0_IDLE_FXU1_IDLEPMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETEDPMC_EV_PPC970_GROUP_MARKED_IDUPMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUTPMC_EV_PPC970_FXU0_BUSY_FXU1_BUSYPMC_EV_PPC970_MARKED_STORE_SENT_TO_STSPMC_EV_PPC970_FXU_MARKED_INSTR_FINISHEDPMC_EV_PPC970_MARKED_GROUP_ISSUEDPMC_EV_PPC970_FXU0_BUSY_FXU1_IDLEPMC_EV_PPC970_GROUP_COMPLETEDPMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNITPMC_EV_PPC970_EXTERNAL_INTERRUPTPMC_EV_PPC970_GROUP_DISPATCH_REJECTPMC_EV_PPC970_LSU_MARKED_INSTR_FINISHPMC_EV_PPC970_TIMEBASE_EVENTPMC_EV_PPC970_LSU_COMPLETION_STALLPMC_EV_PPC970_FXU_COMPLETION_STALLPMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALLPMC_EV_PPC970_FPU_COMPLETION_STALLPMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_REJECT_COMPLETION_STALLPMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISSPMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISSPMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICTPMC_EV_PPC970_BUS_HIGHPMC_EV_PPC970_BUS_LOWPMC_EV_PPC970_ADDERPMC_EV_POWER8__BLOCK_STARTPMC_EV_POWER8_CYCLESPMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETEDPMC_EV_POWER8_FPU_INSTR_COMPLETEDPMC_EV_POWER8_ERAT_INSTR_MISSPMC_EV_POWER8_CYCLES_IDLEPMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNINGPMC_EV_POWER8_STORE_COMPLETEDPMC_EV_POWER8_INSTR_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNINGPMC_EV_POWER8_ERAT_DATA_MISSPMC_EV_POWER8_EXTERNAL_INTERRUPTPMC_EV_POWER8_BRANCH_TAKENPMC_EV_POWER8_L1_INSTR_MISSPMC_EV_POWER8_L2_LOAD_MISSPMC_EV_POWER8_STORE_NO_REAL_ADDRPMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNINGPMC_EV_POWER8_L1_LOAD_MISSPMC_EV_POWER8_TIMEBASE_EVENTPMC_EV_POWER8_L3_INSTR_MISSPMC_EV_POWER8_TLB_DATA_MISSPMC_EV_POWER8_L3_LOAD_MISSPMC_EV_POWER8_LOAD_NO_REAL_ADDRPMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNING_PURR_INCPMC_EV_POWER8_BRANCH_MISPREDICTEDPMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDEDPMC_EV_POWER8_INSTR_COMPLETED_RUNNINGPMC_EV_POWER8_TLB_INSTR_MISSPMC_EV_POWER8_CACHE_LOAD_MISSPMC_EV_POWER8_INSTR_COMPLETEDPMC_EV_E500__BLOCK_STARTPMC_EV_E500_CYCLESPMC_EV_E500_INSTR_COMPLETEDPMC_EV_E500_UOPS_COMPLETEDPMC_EV_E500_INSTR_FETCHEDPMC_EV_E500_UOPS_DECODEDPMC_EV_E500_PM_EVENT_TRANSITIONSPMC_EV_E500_PM_EVENT_CYCLESPMC_EV_E500_BRANCH_INSTRS_COMPLETEDPMC_EV_E500_LOAD_UOPS_COMPLETEDPMC_EV_E500_STORE_UOPS_COMPLETEDPMC_EV_E500_CQ_REDIRECTSPMC_EV_E500_BRANCHES_FINISHEDPMC_EV_E500_TAKEN_BRANCHES_FINISHEDPMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTBPMC_EV_E500_BRANCH_MISPREDPMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTIONPMC_EV_E500_BTB_HITS_PSEUDO_HITSPMC_EV_E500_CYCLES_DECODE_STALLEDPMC_EV_E500_CYCLES_ISSUE_STALLEDPMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLEDPMC_EV_E500_CYCLES_SU1_SCHED_STALLEDPMC_EV_E500_CYCLES_SU2_SCHED_STALLEDPMC_EV_E500_CYCLES_MU_SCHED_STALLEDPMC_EV_E500_CYCLES_LRU_SCHED_STALLEDPMC_EV_E500_CYCLES_BU_SCHED_STALLEDPMC_EV_E500_TOTAL_TRANSLATEDPMC_EV_E500_LOADS_TRANSLATEDPMC_EV_E500_STORES_TRANSLATEDPMC_EV_E500_TOUCHES_TRANSLATEDPMC_EV_E500_CACHEOPS_TRANSLATEDPMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATEDPMC_EV_E500_GUARDED_LOADS_TRANSLATEDPMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATEDPMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATEDPMC_EV_E500_TOTAL_ALLOCATED_TO_DLFBPMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFBPMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETEDPMC_EV_E500_DATA_L1_CACHE_LOCKSPMC_EV_E500_DATA_L1_CACHE_RELOADSPMC_EV_E500_DATA_L1_CACHE_CASTOUTSPMC_EV_E500_LOAD_MISS_DLFB_FULLPMC_EV_E500_LOAD_MISS_LDQ_FULLPMC_EV_E500_LOAD_GUARDED_MISSPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULLPMC_EV_E500_ADDRESS_COLLISIONPMC_EV_E500_DATA_MMU_MISSPMC_EV_E500_DATA_MMU_BUSYPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESSPMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLESPMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLESPMC_EV_E500_LOAD_GUARDED_MISS_CYCLESPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLESPMC_EV_E500_ADDRESS_COLLISION_CYCLESPMC_EV_E500_DATA_MMU_MISS_CYCLESPMC_EV_E500_DATA_MMU_BUSY_CYCLESPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLESPMC_EV_E500_INSTR_L1_CACHE_LOCKSPMC_EV_E500_INSTR_L1_CACHE_RELOADSPMC_EV_E500_INSTR_L1_CACHE_FETCHESPMC_EV_E500_INSTR_MMU_TLB4K_RELOADSPMC_EV_E500_INSTR_MMU_VSP_RELOADSPMC_EV_E500_DATA_MMU_TLB4K_RELOADSPMC_EV_E500_DATA_MMU_VSP_RELOADSPMC_EV_E500_L2MMU_MISSESPMC_EV_E500_BIU_MASTER_REQUESTSPMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTSPMC_EV_E500_BIU_MASTER_RETRIESPMC_EV_E500_SNOOP_REQUESTSPMC_EV_E500_SNOOP_HITSPMC_EV_E500_SNOOP_PUSHESPMC_EV_E500_SNOOP_RETRIESPMC_EV_E500_DLFB_LOAD_MISS_CYCLESPMC_EV_E500_ILFB_FETCH_MISS_CYCLESPMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLESPMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_PMC0_OVERFLOWPMC_EV_E500_PMC1_OVERFLOWPMC_EV_E500_PMC2_OVERFLOWPMC_EV_E500_PMC3_OVERFLOWPMC_EV_E500_INTERRUPTS_TAKENPMC_EV_E500_EXT_INPUT_INTR_TAKENPMC_EV_E500_CRIT_INPUT_INTR_TAKENPMC_EV_E500_SYSCALL_TRAP_INTRPMC_EV_E500_TLB_BIT_TRANSITIONSPMC_EV_E500_L2_LINEFILL_BUFFERPMC_EV_E500_LV2_VSPMC_EV_E500_CASTOUTS_RELEASEDPMC_EV_E500_INTV_ALLOCATIONSPMC_EV_E500_DLFB_RETRIES_TO_MBARPMC_EV_E500_STORE_RETRIESPMC_EV_E500_STASH_L1_HITSPMC_EV_E500_STASH_L2_HITSPMC_EV_E500_STASH_BUSY_1PMC_EV_E500_STASH_BUSY_2PMC_EV_E500_STASH_BUSY_3PMC_EV_E500_STASH_HITSPMC_EV_E500_STASH_HIT_DLFBPMC_EV_E500_STASH_REQUESTSPMC_EV_E500_STASH_REQUESTS_L1PMC_EV_E500_STASH_REQUESTS_L2PMC_EV_E500_STALLS_NO_CAQ_OR_COBPMC_EV_E500_L2_CACHE_ACCESSESPMC_EV_E500_L2_HIT_CACHE_ACCESSESPMC_EV_E500_L2_CACHE_DATA_ACCESSESPMC_EV_E500_L2_CACHE_DATA_HITSPMC_EV_E500_L2_CACHE_INSTR_ACCESSESPMC_EV_E500_L2_CACHE_INSTR_HITSPMC_EV_E500_L2_CACHE_ALLOCATIONSPMC_EV_E500_L2_CACHE_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONSPMC_EV_E500_L2_CACHE_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_LOCKSPMC_EV_E500_L2_CACHE_CASTOUTSPMC_EV_E500_L2_CACHE_DATA_DIRTY_HITSPMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITYPMC_EV_E500_SNOOP_THROTTLING_TURNED_ONPMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONSPMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONSPMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONSPMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHESPMC_EV_E500_IAC1S_DETECTEDPMC_EV_E500_IAC2S_DETECTEDPMC_EV_E500_DAC1S_DTECTEDPMC_EV_E500_DAC2S_DTECTEDPMC_EV_E500_DVT0_DETECTEDPMC_EV_E500_DVT1_DETECTEDPMC_EV_E500_DVT2_DETECTEDPMC_EV_E500_DVT3_DETECTEDPMC_EV_E500_DVT4_DETECTEDPMC_EV_E500_DVT5_DETECTEDPMC_EV_E500_DVT6_DETECTEDPMC_EV_E500_DVT7_DETECTEDPMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULLPMC_EV_E500_FPU_DOUBLE_PUMPPMC_EV_E500_FPU_FINISHPMC_EV_E500_FPU_DIVIDE_CYCLESPMC_EV_E500_FPU_DENORM_INPUT_CYCLESPMC_EV_E500_FPU_RESULT_STALL_CYCLESPMC_EV_E500_FPU_FPSCR_FULL_STALLPMC_EV_E500_FPU_PIPE_SYNC_STALLSPMC_EV_E500_FPU_INPUT_DATA_STALLSPMC_EV_E500_DECORATED_LOADSPMC_EV_E500_DECORATED_STORESPMC_EV_E500_LOAD_RETRIESPMC_EV_E500_STWCX_SUCCESSESPMC_EV_E500_STWCX_FAILURESPMC_EV_ARMV7__BLOCK_STARTPMC_EV_ARMV7_EVENT_00HPMC_EV_ARMV7_EVENT_01HPMC_EV_ARMV7_EVENT_02HPMC_EV_ARMV7_EVENT_03HPMC_EV_ARMV7_EVENT_04HPMC_EV_ARMV7_EVENT_05HPMC_EV_ARMV7_EVENT_06HPMC_EV_ARMV7_EVENT_07HPMC_EV_ARMV7_EVENT_08HPMC_EV_ARMV7_EVENT_09HPMC_EV_ARMV7_EVENT_0AHPMC_EV_ARMV7_EVENT_0BHPMC_EV_ARMV7_EVENT_0CHPMC_EV_ARMV7_EVENT_0DHPMC_EV_ARMV7_EVENT_0EHPMC_EV_ARMV7_EVENT_0FHPMC_EV_ARMV7_EVENT_10HPMC_EV_ARMV7_EVENT_11HPMC_EV_ARMV7_EVENT_12HPMC_EV_ARMV7_EVENT_13HPMC_EV_ARMV7_EVENT_14HPMC_EV_ARMV7_EVENT_15HPMC_EV_ARMV7_EVENT_16HPMC_EV_ARMV7_EVENT_17HPMC_EV_ARMV7_EVENT_18HPMC_EV_ARMV7_EVENT_19HPMC_EV_ARMV7_EVENT_1AHPMC_EV_ARMV7_EVENT_1BHPMC_EV_ARMV7_EVENT_1CHPMC_EV_ARMV7_EVENT_1DHPMC_EV_ARMV7_EVENT_1EHPMC_EV_ARMV7_EVENT_1FHPMC_EV_ARMV7_EVENT_20HPMC_EV_ARMV7_EVENT_21HPMC_EV_ARMV7_EVENT_22HPMC_EV_ARMV7_EVENT_23HPMC_EV_ARMV7_EVENT_24HPMC_EV_ARMV7_EVENT_25HPMC_EV_ARMV7_EVENT_26HPMC_EV_ARMV7_EVENT_27HPMC_EV_ARMV7_EVENT_28HPMC_EV_ARMV7_EVENT_29HPMC_EV_ARMV7_EVENT_2AHPMC_EV_ARMV7_EVENT_2BHPMC_EV_ARMV7_EVENT_2CHPMC_EV_ARMV7_EVENT_2DHPMC_EV_ARMV7_EVENT_2EHPMC_EV_ARMV7_EVENT_2FHPMC_EV_ARMV7_EVENT_30HPMC_EV_ARMV7_EVENT_31HPMC_EV_ARMV7_EVENT_32HPMC_EV_ARMV7_EVENT_33HPMC_EV_ARMV7_EVENT_34HPMC_EV_ARMV7_EVENT_35HPMC_EV_ARMV7_EVENT_36HPMC_EV_ARMV7_EVENT_37HPMC_EV_ARMV7_EVENT_38HPMC_EV_ARMV7_EVENT_39HPMC_EV_ARMV7_EVENT_3AHPMC_EV_ARMV7_EVENT_3BHPMC_EV_ARMV7_EVENT_3CHPMC_EV_ARMV7_EVENT_3DHPMC_EV_ARMV7_EVENT_3EHPMC_EV_ARMV7_EVENT_3FHPMC_EV_ARMV7_EVENT_40HPMC_EV_ARMV7_EVENT_41HPMC_EV_ARMV7_EVENT_42HPMC_EV_ARMV7_EVENT_43HPMC_EV_ARMV7_EVENT_44HPMC_EV_ARMV7_EVENT_45HPMC_EV_ARMV7_EVENT_46HPMC_EV_ARMV7_EVENT_47HPMC_EV_ARMV7_EVENT_48HPMC_EV_ARMV7_EVENT_49HPMC_EV_ARMV7_EVENT_4AHPMC_EV_ARMV7_EVENT_4BHPMC_EV_ARMV7_EVENT_4CHPMC_EV_ARMV7_EVENT_4DHPMC_EV_ARMV7_EVENT_4EHPMC_EV_ARMV7_EVENT_4FHPMC_EV_ARMV7_EVENT_50HPMC_EV_ARMV7_EVENT_51HPMC_EV_ARMV7_EVENT_52HPMC_EV_ARMV7_EVENT_53HPMC_EV_ARMV7_EVENT_54HPMC_EV_ARMV7_EVENT_55HPMC_EV_ARMV7_EVENT_56HPMC_EV_ARMV7_EVENT_57HPMC_EV_ARMV7_EVENT_58HPMC_EV_ARMV7_EVENT_59HPMC_EV_ARMV7_EVENT_5AHPMC_EV_ARMV7_EVENT_5BHPMC_EV_ARMV7_EVENT_5CHPMC_EV_ARMV7_EVENT_5DHPMC_EV_ARMV7_EVENT_5EHPMC_EV_ARMV7_EVENT_5FHPMC_EV_ARMV7_EVENT_60HPMC_EV_ARMV7_EVENT_61HPMC_EV_ARMV7_EVENT_62HPMC_EV_ARMV7_EVENT_63HPMC_EV_ARMV7_EVENT_64HPMC_EV_ARMV7_EVENT_65HPMC_EV_ARMV7_EVENT_66HPMC_EV_ARMV7_EVENT_67HPMC_EV_ARMV7_EVENT_68HPMC_EV_ARMV7_EVENT_69HPMC_EV_ARMV7_EVENT_6AHPMC_EV_ARMV7_EVENT_6BHPMC_EV_ARMV7_EVENT_6CHPMC_EV_ARMV7_EVENT_6DHPMC_EV_ARMV7_EVENT_6EHPMC_EV_ARMV7_EVENT_6FHPMC_EV_ARMV7_EVENT_70HPMC_EV_ARMV7_EVENT_71HPMC_EV_ARMV7_EVENT_72HPMC_EV_ARMV7_EVENT_73HPMC_EV_ARMV7_EVENT_74HPMC_EV_ARMV7_EVENT_75HPMC_EV_ARMV7_EVENT_76HPMC_EV_ARMV7_EVENT_77HPMC_EV_ARMV7_EVENT_78HPMC_EV_ARMV7_EVENT_79HPMC_EV_ARMV7_EVENT_7AHPMC_EV_ARMV7_EVENT_7BHPMC_EV_ARMV7_EVENT_7CHPMC_EV_ARMV7_EVENT_7DHPMC_EV_ARMV7_EVENT_7EHPMC_EV_ARMV7_EVENT_7FHPMC_EV_ARMV7_EVENT_80HPMC_EV_ARMV7_EVENT_81HPMC_EV_ARMV7_EVENT_82HPMC_EV_ARMV7_EVENT_83HPMC_EV_ARMV7_EVENT_84HPMC_EV_ARMV7_EVENT_85HPMC_EV_ARMV7_EVENT_86HPMC_EV_ARMV7_EVENT_87HPMC_EV_ARMV7_EVENT_88HPMC_EV_ARMV7_EVENT_89HPMC_EV_ARMV7_EVENT_8AHPMC_EV_ARMV7_EVENT_8BHPMC_EV_ARMV7_EVENT_8CHPMC_EV_ARMV7_EVENT_8DHPMC_EV_ARMV7_EVENT_8EHPMC_EV_ARMV7_EVENT_8FHPMC_EV_ARMV7_EVENT_90HPMC_EV_ARMV7_EVENT_91HPMC_EV_ARMV7_EVENT_92HPMC_EV_ARMV7_EVENT_93HPMC_EV_ARMV7_EVENT_94HPMC_EV_ARMV7_EVENT_95HPMC_EV_ARMV7_EVENT_96HPMC_EV_ARMV7_EVENT_97HPMC_EV_ARMV7_EVENT_98HPMC_EV_ARMV7_EVENT_99HPMC_EV_ARMV7_EVENT_9AHPMC_EV_ARMV7_EVENT_9BHPMC_EV_ARMV7_EVENT_9CHPMC_EV_ARMV7_EVENT_9DHPMC_EV_ARMV7_EVENT_9EHPMC_EV_ARMV7_EVENT_9FHPMC_EV_ARMV7_EVENT_A0HPMC_EV_ARMV7_EVENT_A1HPMC_EV_ARMV7_EVENT_A2HPMC_EV_ARMV7_EVENT_A3HPMC_EV_ARMV7_EVENT_A4HPMC_EV_ARMV7_EVENT_A5HPMC_EV_ARMV7_EVENT_A6HPMC_EV_ARMV7_EVENT_A7HPMC_EV_ARMV7_EVENT_A8HPMC_EV_ARMV7_EVENT_A9HPMC_EV_ARMV7_EVENT_AAHPMC_EV_ARMV7_EVENT_ABHPMC_EV_ARMV7_EVENT_ACHPMC_EV_ARMV7_EVENT_ADHPMC_EV_ARMV7_EVENT_AEHPMC_EV_ARMV7_EVENT_AFHPMC_EV_ARMV7_EVENT_B0HPMC_EV_ARMV7_EVENT_B1HPMC_EV_ARMV7_EVENT_B2HPMC_EV_ARMV7_EVENT_B3HPMC_EV_ARMV7_EVENT_B4HPMC_EV_ARMV7_EVENT_B5HPMC_EV_ARMV7_EVENT_B6HPMC_EV_ARMV7_EVENT_B7HPMC_EV_ARMV7_EVENT_B8HPMC_EV_ARMV7_EVENT_B9HPMC_EV_ARMV7_EVENT_BAHPMC_EV_ARMV7_EVENT_BBHPMC_EV_ARMV7_EVENT_BCHPMC_EV_ARMV7_EVENT_BDHPMC_EV_ARMV7_EVENT_BEHPMC_EV_ARMV7_EVENT_BFHPMC_EV_ARMV7_EVENT_C0HPMC_EV_ARMV7_EVENT_C1HPMC_EV_ARMV7_EVENT_C2HPMC_EV_ARMV7_EVENT_C3HPMC_EV_ARMV7_EVENT_C4HPMC_EV_ARMV7_EVENT_C5HPMC_EV_ARMV7_EVENT_C6HPMC_EV_ARMV7_EVENT_C7HPMC_EV_ARMV7_EVENT_C8HPMC_EV_ARMV7_EVENT_C9HPMC_EV_ARMV7_EVENT_CAHPMC_EV_ARMV7_EVENT_CBHPMC_EV_ARMV7_EVENT_CCHPMC_EV_ARMV7_EVENT_CDHPMC_EV_ARMV7_EVENT_CEHPMC_EV_ARMV7_EVENT_CFHPMC_EV_ARMV7_EVENT_D0HPMC_EV_ARMV7_EVENT_D1HPMC_EV_ARMV7_EVENT_D2HPMC_EV_ARMV7_EVENT_D3HPMC_EV_ARMV7_EVENT_D4HPMC_EV_ARMV7_EVENT_D5HPMC_EV_ARMV7_EVENT_D6HPMC_EV_ARMV7_EVENT_D7HPMC_EV_ARMV7_EVENT_D8HPMC_EV_ARMV7_EVENT_D9HPMC_EV_ARMV7_EVENT_DAHPMC_EV_ARMV7_EVENT_DBHPMC_EV_ARMV7_EVENT_DCHPMC_EV_ARMV7_EVENT_DDHPMC_EV_ARMV7_EVENT_DEHPMC_EV_ARMV7_EVENT_DFHPMC_EV_ARMV7_EVENT_E0HPMC_EV_ARMV7_EVENT_E1HPMC_EV_ARMV7_EVENT_E2HPMC_EV_ARMV7_EVENT_E3HPMC_EV_ARMV7_EVENT_E4HPMC_EV_ARMV7_EVENT_E5HPMC_EV_ARMV7_EVENT_E6HPMC_EV_ARMV7_EVENT_E7HPMC_EV_ARMV7_EVENT_E8HPMC_EV_ARMV7_EVENT_E9HPMC_EV_ARMV7_EVENT_EAHPMC_EV_ARMV7_EVENT_EBHPMC_EV_ARMV7_EVENT_ECHPMC_EV_ARMV7_EVENT_EDHPMC_EV_ARMV7_EVENT_EEHPMC_EV_ARMV7_EVENT_EFHPMC_EV_ARMV7_EVENT_F0HPMC_EV_ARMV7_EVENT_F1HPMC_EV_ARMV7_EVENT_F2HPMC_EV_ARMV7_EVENT_F3HPMC_EV_ARMV7_EVENT_F4HPMC_EV_ARMV7_EVENT_F5HPMC_EV_ARMV7_EVENT_F6HPMC_EV_ARMV7_EVENT_F7HPMC_EV_ARMV7_EVENT_F8HPMC_EV_ARMV7_EVENT_F9HPMC_EV_ARMV7_EVENT_FAHPMC_EV_ARMV7_EVENT_FBHPMC_EV_ARMV7_EVENT_FCHPMC_EV_ARMV7_EVENT_FDHPMC_EV_ARMV7_EVENT_FEHPMC_EV_ARMV7_EVENT_FFHPMC_EV_ARMV8__BLOCK_STARTPMC_EV_ARMV8_EVENT_00HPMC_EV_ARMV8_EVENT_01HPMC_EV_ARMV8_EVENT_02HPMC_EV_ARMV8_EVENT_03HPMC_EV_ARMV8_EVENT_04HPMC_EV_ARMV8_EVENT_05HPMC_EV_ARMV8_EVENT_06HPMC_EV_ARMV8_EVENT_07HPMC_EV_ARMV8_EVENT_08HPMC_EV_ARMV8_EVENT_09HPMC_EV_ARMV8_EVENT_0AHPMC_EV_ARMV8_EVENT_0BHPMC_EV_ARMV8_EVENT_0CHPMC_EV_ARMV8_EVENT_0DHPMC_EV_ARMV8_EVENT_0EHPMC_EV_ARMV8_EVENT_0FHPMC_EV_ARMV8_EVENT_10HPMC_EV_ARMV8_EVENT_11HPMC_EV_ARMV8_EVENT_12HPMC_EV_ARMV8_EVENT_13HPMC_EV_ARMV8_EVENT_14HPMC_EV_ARMV8_EVENT_15HPMC_EV_ARMV8_EVENT_16HPMC_EV_ARMV8_EVENT_17HPMC_EV_ARMV8_EVENT_18HPMC_EV_ARMV8_EVENT_19HPMC_EV_ARMV8_EVENT_1AHPMC_EV_ARMV8_EVENT_1BHPMC_EV_ARMV8_EVENT_1CHPMC_EV_ARMV8_EVENT_1DHPMC_EV_ARMV8_EVENT_1EHPMC_EV_ARMV8_EVENT_1FHPMC_EV_ARMV8_EVENT_20HPMC_EV_ARMV8_EVENT_21HPMC_EV_ARMV8_EVENT_22HPMC_EV_ARMV8_EVENT_23HPMC_EV_ARMV8_EVENT_24HPMC_EV_ARMV8_EVENT_25HPMC_EV_ARMV8_EVENT_26HPMC_EV_ARMV8_EVENT_27HPMC_EV_ARMV8_EVENT_28HPMC_EV_ARMV8_EVENT_29HPMC_EV_ARMV8_EVENT_2AHPMC_EV_ARMV8_EVENT_2BHPMC_EV_ARMV8_EVENT_2CHPMC_EV_ARMV8_EVENT_2DHPMC_EV_ARMV8_EVENT_2EHPMC_EV_ARMV8_EVENT_2FHPMC_EV_ARMV8_EVENT_30HPMC_EV_ARMV8_EVENT_31HPMC_EV_ARMV8_EVENT_32HPMC_EV_ARMV8_EVENT_33HPMC_EV_ARMV8_EVENT_34HPMC_EV_ARMV8_EVENT_35HPMC_EV_ARMV8_EVENT_36HPMC_EV_ARMV8_EVENT_37HPMC_EV_ARMV8_EVENT_38HPMC_EV_ARMV8_EVENT_39HPMC_EV_ARMV8_EVENT_3AHPMC_EV_ARMV8_EVENT_3BHPMC_EV_ARMV8_EVENT_3CHPMC_EV_ARMV8_EVENT_3DHPMC_EV_ARMV8_EVENT_3EHPMC_EV_ARMV8_EVENT_3FHPMC_EV_ARMV8_EVENT_40HPMC_EV_ARMV8_EVENT_41HPMC_EV_ARMV8_EVENT_42HPMC_EV_ARMV8_EVENT_43HPMC_EV_ARMV8_EVENT_44HPMC_EV_ARMV8_EVENT_45HPMC_EV_ARMV8_EVENT_46HPMC_EV_ARMV8_EVENT_47HPMC_EV_ARMV8_EVENT_48HPMC_EV_ARMV8_EVENT_49HPMC_EV_ARMV8_EVENT_4AHPMC_EV_ARMV8_EVENT_4BHPMC_EV_ARMV8_EVENT_4CHPMC_EV_ARMV8_EVENT_4DHPMC_EV_ARMV8_EVENT_4EHPMC_EV_ARMV8_EVENT_4FHPMC_EV_ARMV8_EVENT_50HPMC_EV_ARMV8_EVENT_51HPMC_EV_ARMV8_EVENT_52HPMC_EV_ARMV8_EVENT_53HPMC_EV_ARMV8_EVENT_54HPMC_EV_ARMV8_EVENT_55HPMC_EV_ARMV8_EVENT_56HPMC_EV_ARMV8_EVENT_57HPMC_EV_ARMV8_EVENT_58HPMC_EV_ARMV8_EVENT_59HPMC_EV_ARMV8_EVENT_5AHPMC_EV_ARMV8_EVENT_5BHPMC_EV_ARMV8_EVENT_5CHPMC_EV_ARMV8_EVENT_5DHPMC_EV_ARMV8_EVENT_5EHPMC_EV_ARMV8_EVENT_5FHPMC_EV_ARMV8_EVENT_60HPMC_EV_ARMV8_EVENT_61HPMC_EV_ARMV8_EVENT_62HPMC_EV_ARMV8_EVENT_63HPMC_EV_ARMV8_EVENT_64HPMC_EV_ARMV8_EVENT_65HPMC_EV_ARMV8_EVENT_66HPMC_EV_ARMV8_EVENT_67HPMC_EV_ARMV8_EVENT_68HPMC_EV_ARMV8_EVENT_69HPMC_EV_ARMV8_EVENT_6AHPMC_EV_ARMV8_EVENT_6BHPMC_EV_ARMV8_EVENT_6CHPMC_EV_ARMV8_EVENT_6DHPMC_EV_ARMV8_EVENT_6EHPMC_EV_ARMV8_EVENT_6FHPMC_EV_ARMV8_EVENT_70HPMC_EV_ARMV8_EVENT_71HPMC_EV_ARMV8_EVENT_72HPMC_EV_ARMV8_EVENT_73HPMC_EV_ARMV8_EVENT_74HPMC_EV_ARMV8_EVENT_75HPMC_EV_ARMV8_EVENT_76HPMC_EV_ARMV8_EVENT_77HPMC_EV_ARMV8_EVENT_78HPMC_EV_ARMV8_EVENT_79HPMC_EV_ARMV8_EVENT_7AHPMC_EV_ARMV8_EVENT_7BHPMC_EV_ARMV8_EVENT_7CHPMC_EV_ARMV8_EVENT_7DHPMC_EV_ARMV8_EVENT_7EHPMC_EV_ARMV8_EVENT_7FHPMC_EV_ARMV8_EVENT_80HPMC_EV_ARMV8_EVENT_81HPMC_EV_ARMV8_EVENT_82HPMC_EV_ARMV8_EVENT_83HPMC_EV_ARMV8_EVENT_84HPMC_EV_ARMV8_EVENT_85HPMC_EV_ARMV8_EVENT_86HPMC_EV_ARMV8_EVENT_87HPMC_EV_ARMV8_EVENT_88HPMC_EV_ARMV8_EVENT_89HPMC_EV_ARMV8_EVENT_8AHPMC_EV_ARMV8_EVENT_8BHPMC_EV_ARMV8_EVENT_8CHPMC_EV_ARMV8_EVENT_8DHPMC_EV_ARMV8_EVENT_8EHPMC_EV_ARMV8_EVENT_8FHPMC_EV_ARMV8_EVENT_90HPMC_EV_ARMV8_EVENT_91HPMC_EV_ARMV8_EVENT_92HPMC_EV_ARMV8_EVENT_93HPMC_EV_ARMV8_EVENT_94HPMC_EV_ARMV8_EVENT_95HPMC_EV_ARMV8_EVENT_96HPMC_EV_ARMV8_EVENT_97HPMC_EV_ARMV8_EVENT_98HPMC_EV_ARMV8_EVENT_99HPMC_EV_ARMV8_EVENT_9AHPMC_EV_ARMV8_EVENT_9BHPMC_EV_ARMV8_EVENT_9CHPMC_EV_ARMV8_EVENT_9DHPMC_EV_ARMV8_EVENT_9EHPMC_EV_ARMV8_EVENT_9FHPMC_EV_ARMV8_EVENT_A0HPMC_EV_ARMV8_EVENT_A1HPMC_EV_ARMV8_EVENT_A2HPMC_EV_ARMV8_EVENT_A3HPMC_EV_ARMV8_EVENT_A4HPMC_EV_ARMV8_EVENT_A5HPMC_EV_ARMV8_EVENT_A6HPMC_EV_ARMV8_EVENT_A7HPMC_EV_ARMV8_EVENT_A8HPMC_EV_ARMV8_EVENT_A9HPMC_EV_ARMV8_EVENT_AAHPMC_EV_ARMV8_EVENT_ABHPMC_EV_ARMV8_EVENT_ACHPMC_EV_ARMV8_EVENT_ADHPMC_EV_ARMV8_EVENT_AEHPMC_EV_ARMV8_EVENT_AFHPMC_EV_ARMV8_EVENT_B0HPMC_EV_ARMV8_EVENT_B1HPMC_EV_ARMV8_EVENT_B2HPMC_EV_ARMV8_EVENT_B3HPMC_EV_ARMV8_EVENT_B4HPMC_EV_ARMV8_EVENT_B5HPMC_EV_ARMV8_EVENT_B6HPMC_EV_ARMV8_EVENT_B7HPMC_EV_ARMV8_EVENT_B8HPMC_EV_ARMV8_EVENT_B9HPMC_EV_ARMV8_EVENT_BAHPMC_EV_ARMV8_EVENT_BBHPMC_EV_ARMV8_EVENT_BCHPMC_EV_ARMV8_EVENT_BDHPMC_EV_ARMV8_EVENT_BEHPMC_EV_ARMV8_EVENT_BFHPMC_EV_ARMV8_EVENT_C0HPMC_EV_ARMV8_EVENT_C1HPMC_EV_ARMV8_EVENT_C2HPMC_EV_ARMV8_EVENT_C3HPMC_EV_ARMV8_EVENT_C4HPMC_EV_ARMV8_EVENT_C5HPMC_EV_ARMV8_EVENT_C6HPMC_EV_ARMV8_EVENT_C7HPMC_EV_ARMV8_EVENT_C8HPMC_EV_ARMV8_EVENT_C9HPMC_EV_ARMV8_EVENT_CAHPMC_EV_ARMV8_EVENT_CBHPMC_EV_ARMV8_EVENT_CCHPMC_EV_ARMV8_EVENT_CDHPMC_EV_ARMV8_EVENT_CEHPMC_EV_ARMV8_EVENT_CFHPMC_EV_ARMV8_EVENT_D0HPMC_EV_ARMV8_EVENT_D1HPMC_EV_ARMV8_EVENT_D2HPMC_EV_ARMV8_EVENT_D3HPMC_EV_ARMV8_EVENT_D4HPMC_EV_ARMV8_EVENT_D5HPMC_EV_ARMV8_EVENT_D6HPMC_EV_ARMV8_EVENT_D7HPMC_EV_ARMV8_EVENT_D8HPMC_EV_ARMV8_EVENT_D9HPMC_EV_ARMV8_EVENT_DAHPMC_EV_ARMV8_EVENT_DBHPMC_EV_ARMV8_EVENT_DCHPMC_EV_ARMV8_EVENT_DDHPMC_EV_ARMV8_EVENT_DEHPMC_EV_ARMV8_EVENT_DFHPMC_EV_ARMV8_EVENT_E0HPMC_EV_ARMV8_EVENT_E1HPMC_EV_ARMV8_EVENT_E2HPMC_EV_ARMV8_EVENT_E3HPMC_EV_ARMV8_EVENT_E4HPMC_EV_ARMV8_EVENT_E5HPMC_EV_ARMV8_EVENT_E6HPMC_EV_ARMV8_EVENT_E7HPMC_EV_ARMV8_EVENT_E8HPMC_EV_ARMV8_EVENT_E9HPMC_EV_ARMV8_EVENT_EAHPMC_EV_ARMV8_EVENT_EBHPMC_EV_ARMV8_EVENT_ECHPMC_EV_ARMV8_EVENT_EDHPMC_EV_ARMV8_EVENT_EEHPMC_EV_ARMV8_EVENT_EFHPMC_EV_ARMV8_EVENT_F0HPMC_EV_ARMV8_EVENT_F1HPMC_EV_ARMV8_EVENT_F2HPMC_EV_ARMV8_EVENT_F3HPMC_EV_ARMV8_EVENT_F4HPMC_EV_ARMV8_EVENT_F5HPMC_EV_ARMV8_EVENT_F6HPMC_EV_ARMV8_EVENT_F7HPMC_EV_ARMV8_EVENT_F8HPMC_EV_ARMV8_EVENT_F9HPMC_EV_ARMV8_EVENT_FAHPMC_EV_ARMV8_EVENT_FBHPMC_EV_ARMV8_EVENT_FCHPMC_EV_ARMV8_EVENT_FDHPMC_EV_ARMV8_EVENT_FEHPMC_EV_ARMV8_EVENT_FFHpmc_eventpmc_event_descr__ARRAY_SIZE_TYPE__pmc_class_tablepm_evc_namepm_evc_name_size__uint32_t__size_tsize_tpm_evc_classPMC_CLASS_TSCPMC_CLASS_K7PMC_CLASS_K8PMC_CLASS_P5PMC_CLASS_P6PMC_CLASS_P4PMC_CLASS_IAFPMC_CLASS_IAPPMC_CLASS_UCFPMC_CLASS_UCPPMC_CLASS_XSCALEPMC_CLASS_MIPS24KPMC_CLASS_OCTEONPMC_CLASS_PPC7450PMC_CLASS_PPC970PMC_CLASS_SOFTPMC_CLASS_ARMV7PMC_CLASS_ARMV8PMC_CLASS_MIPS74KPMC_CLASS_E500PMC_CLASS_BERIPMC_CLASS_POWER8pmc_classpm_evc_event_tablepm_evc_event_table_sizepm_evc_allocate_pmcintpm_capsuint32_tpm_cpupm_classpm_evpm_flagspm_modePMC_MODE_SSPMC_MODE_SCPMC_MODE_TSPMC_MODE_TCpmc_modepm_pmcidpmc_id_tpm_countlong long unsigned int__uint64_tuint64_tpmc_value_tpm_mdpm_amdpm_amd_configpm_amd_sub_classpmc_md_amd_op_pmcallocatepm_iappm_iap_configpm_iap_rsppmc_md_iap_op_pmcallocatepm_ucfpm_ucf_flagsunsigned short__uint16_tuint16_tpmc_md_ucf_op_pmcallocatepm_ucppm_ucp_configpmc_md_ucp_op_pmcallocate__padpmc_md_op_pmcallocatepmc_op_pmcallocatepmc_class_descrpmc_mdep_class_listpmc_mdep_class_list_sizecpu_infopm_cputypePMC_CPU_AMD_K7PMC_CPU_AMD_K8PMC_CPU_INTEL_P5PMC_CPU_INTEL_P6PMC_CPU_INTEL_CLPMC_CPU_INTEL_PIIPMC_CPU_INTEL_PIIIPMC_CPU_INTEL_PMPMC_CPU_INTEL_PIVPMC_CPU_INTEL_COREPMC_CPU_INTEL_CORE2PMC_CPU_INTEL_CORE2EXTREMEPMC_CPU_INTEL_ATOMPMC_CPU_INTEL_COREI7PMC_CPU_INTEL_WESTMEREPMC_CPU_INTEL_SANDYBRIDGEPMC_CPU_INTEL_IVYBRIDGEPMC_CPU_INTEL_SANDYBRIDGE_XEONPMC_CPU_INTEL_IVYBRIDGE_XEONPMC_CPU_INTEL_HASWELLPMC_CPU_INTEL_ATOM_SILVERMONTPMC_CPU_INTEL_NEHALEM_EXPMC_CPU_INTEL_WESTMERE_EXPMC_CPU_INTEL_HASWELL_XEONPMC_CPU_INTEL_BROADWELLPMC_CPU_INTEL_BROADWELL_XEONPMC_CPU_INTEL_SKYLAKEPMC_CPU_INTEL_SKYLAKE_XEONPMC_CPU_INTEL_ATOM_GOLDMONTPMC_CPU_INTEL_XSCALEPMC_CPU_MIPS_24KPMC_CPU_MIPS_OCTEONPMC_CPU_MIPS_74KPMC_CPU_MIPS_BERIPMC_CPU_PPC_7450PMC_CPU_PPC_E500PMC_CPU_PPC_970PMC_CPU_PPC_POWER8PMC_CPU_GENERICPMC_CPU_ARMV7_CORTEX_A5PMC_CPU_ARMV7_CORTEX_A7PMC_CPU_ARMV7_CORTEX_A8PMC_CPU_ARMV7_CORTEX_A9PMC_CPU_ARMV7_CORTEX_A15PMC_CPU_ARMV7_CORTEX_A17PMC_CPU_ARMV8_CORTEX_A53PMC_CPU_ARMV8_CORTEX_A57PMC_CPU_ARMV8_CORTEX_A76pmc_cputypepm_ncpupm_npmcpm_nclasspm_classespm_widthpm_numpmc_classinfopmc_cpuinfosoft_event_infopm_neventpm_eventspmc_dyn_event_descrpmc_op_getdyneventinfopmc_syscalliaf_event_tabletsc_event_tablek8_event_tablecortex_a8_event_tablecortex_a9_event_tablecortex_a53_event_tablecortex_a57_event_tablecortex_a76_event_tableberi_event_tablemips24k_event_tablemips74k_event_tableocteon_event_tableppc7450_event_tableppc970_event_tablepower8_event_tablee500_event_tablesoft_class_table_descrtsc_class_table_descrk8_aliasesk8_pmc_classesk8_class_table_descrk8_mask_fdfopm_namepm_valuepmc_masksk8_mask_lsrlk8_mask_llok8_mask_dck8_mask_dobeek8_mask_ddpik8_mask_dablk8_mask_bilrk8_mask_bfrlmk8_mask_bfilk8_mask_frfik8_mask_frfdoik8_mask_ffek8_mask_nmcpaek8_mask_nmctk8_mask_nmcbsk8_mask_nsck8_mask_nprk8_mask_nhbbgeneric_aliasesgeneric_pmc_classespmc_capability_namespmc_class_namespmc_class_mappmc_cputype_namespmc_cputype_mappmc_disposition_namespmc_mode_namespmc_state_namesPMC_CAP_INTERRUPTPMC_CAP_USERPMC_CAP_SYSTEMPMC_CAP_EDGEPMC_CAP_THRESHOLDPMC_CAP_READPMC_CAP_WRITEPMC_CAP_INVERTPMC_CAP_QUALIFIERPMC_CAP_PRECISEPMC_CAP_TAGGINGPMC_CAP_CASCADEpmc_capsPMC_OP_CONFIGURELOGPMC_OP_FLUSHLOGPMC_OP_GETCPUINFOPMC_OP_GETDRIVERSTATSPMC_OP_GETMODULEVERSIONPMC_OP_GETPMCINFOPMC_OP_PMCADMINPMC_OP_PMCALLOCATEPMC_OP_PMCATTACHPMC_OP_PMCDETACHPMC_OP_PMCGETMSRPMC_OP_PMCRELEASEPMC_OP_PMCRWPMC_OP_PMCSETCOUNTPMC_OP_PMCSTARTPMC_OP_PMCSTOPPMC_OP_WRITELOGPMC_OP_CLOSELOGPMC_OP_GETDYNEVENTINFOpmc_opsPMC_STATE_DISABLEDPMC_STATE_FREEPMC_STATE_ALLOCATEDPMC_STATE_STOPPEDPMC_STATE_RUNNINGPMC_STATE_DELETEDPMC_STATE_MAXpmc_statePMC_DISP_STANDALONEPMC_DISP_FREEPMC_DISP_THREADPMC_DISP_UNKNOWNpmc_disp__int32_tint32_tpm_pmcspm_enabledpm_rowdisppm_ownerpid__pid_tpid_tpm_eventpm_reloadcountpmc_infopmc_pmcinfounsigned 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r.1047.L.str.47.L.str.937.L.str.837.L.str.737.L.str.637.L.str.537.L.str.437.L.str.337.L.str.237.L.str.1137.L.str.137.L.str.1037.L.str.37.L.str.927.L.str.827.L.str.727.L.str.627.L.str.527.L.str.427.L.str.327.L.str.1227.L.str.227.L.str.1127.L.str.127.L.str.1027.L.str.27.L.str.917.L.str.817.L.str.717.L.str.617.L.str.517.L.str.417.L.str.317.L.str.1217.L.str.217.L.str.1117.L.str.117.L.str.1017.L.str.17.L.str.907.L.str.807.L.str.707.L.str.607.L.str.507.L.str.407.L.str.307.L.str.1207.L.str.207.L.str.1107.L.str.107.L.str.1007.L.str.7.L.str.996.L.str.896.L.str.796.L.str.696.L.str.596.L.str.496.L.str.396.L.str.296.L.str.1196.L.str.196.L.str.1096.L.str.96.L.str.986.L.str.886.L.str.786.L.str.686.L.str.586.L.str.486.L.str.386.L.str.286.L.str.1186.L.str.186.L.str.1086.L.str.86.L.str.976.L.str.876.L.str.776.L.str.676.L.str.576.L.str.476.L.str.376.L.str.276.L.str.1176.L.str.176.L.str.1076.L.str.76.L.str.966.L.str.866.L.str.766.L.str.666.L.str.566.L.str.466.L.str.366.L.str.266.L.str.1166.L.str.166.L.str.1066.L.str.66.L.str.956.L.str.856.L.str.756.L.str.656.L.str.556.L.str.456.L.str.356.L.str.256.L.str.1156.L.str.156.L.str.1056.L.str.56.L.str.946.L.str.846.L.str.746.L.str.646.L.str.546.L.str.446.L.str.346.L.str.246.L.str.1146.L.str.146.L.str.1046.L.str.46.L.str.936.L.str.836.L.str.736.L.str.636.L.str.536.L.str.436.L.str.336.L.str.236.L.str.1136.L.str.136.L.str.1036.L.str.36.L.str.926.L.str.826.L.str.726.L.str.626.L.str.526.L.str.426.L.str.326.L.str.1226.L.str.226.L.str.1126.L.str.126.L.str.1026.L.str.26.L.str.916.L.str.816.L.str.716.L.str.616.L.str.516.L.str.416.L.str.316.L.str.1216.L.str.216.L.str.1116.L.str.116.L.str.1016.L.str.16.L.str.906.L.str.806.L.str.706.L.str.606.L.str.506.L.str.406.L.str.306.L.str.1206.L.str.206.L.str.1106.L.str.106.L.str.1006.L.str.6.L.str.995.L.str.895.L.str.795.L.str.695.L.str.595.L.str.495.L.str.395.L.str.295.L.str.1195.L.str.195.L.str.1095.L.str.95.L.str.985.L.str.885.L.str.785.L.str.685.L.str.585.L.str.485.L.str.385.L.str.285.L.str.1185.L.str.185.L.str.1085.L.str.85.L.str.975.L.str.875.L.str.775.L.str.675.L.str.575.L.str.475.L.str.375.L.str.275.L.str.1175.L.str.175.L.str.1075.L.str.75.L.str.965.L.str.865.L.str.765.L.str.665.L.str.565.L.str.465.L.str.365.L.str.265.L.str.1165.L.str.165.L.str.1065.L.str.65.L.str.955.L.str.855.L.str.755.L.str.655.L.str.555.L.str.455.L.str.355.L.str.255.L.str.1155.L.str.155.L.str.1055.L.str.55.L.str.945.L.str.845.L.str.745.L.str.645.L.str.545.L.str.445.L.str.345.L.str.245.L.str.1145.L.str.145.L.str.1045.L.str.45.L.str.935.L.str.835.L.str.735.L.str.635.L.str.535.L.str.435.L.str.335.L.str.1235.L.str.235.L.str.1135.L.str.135.L.str.1035.L.str.35.L.str.925.L.str.825.L.str.725.L.str.625.L.str.525.L.str.425.L.str.325.L.str.1225.L.str.225.L.str.1125.L.str.125.L.str.1025.L.str.25.L.str.915.L.str.815.L.str.715.L.str.615.L.str.515.L.str.415.L.str.315.L.str.1215.L.str.215.L.str.1115.L.str.115.L.str.1015.L.str.15.L.str.905.L.str.805.L.str.705.L.str.605.L.str.505.L.str.405.L.str.305.L.str.1205.L.str.205.L.str.1105.L.str.105.L.str.1005.L.str.5.L.str.994.L.str.894.L.str.794.L.str.694.L.str.594.L.str.494.L.str.394.L.str.294.L.str.1194.L.str.194.L.str.1094.L.str.94.L.str.984.L.str.884.L.str.784.L.str.684.L.str.584.L.str.484.L.str.384.L.str.284.L.str.1184.L.str.184.L.str.1084.L.str.84.L.str.974.L.str.874.L.str.774.L.str.674.L.str.574.L.str.474.L.str.374.L.str.274.L.str.1174.L.str.174.L.str.1074.L.str.74.L.str.964.L.str.864.L.str.764.L.str.664.L.str.564.L.str.464.L.str.364.L.str.264.L.str.1164.L.str.164.L.str.1064.L.str.64.L.str.954.L.str.854.L.str.754.L.str.654.L.str.554.L.str.454.L.str.354.L.str.254.L.str.1154.L.str.154.L.str.1054.L.str.54.L.str.944.L.str.844.L.str.744.L.str.644.L.str.544.L.str.444.L.str.344.L.str.244.L.str.1144.L.str.144.L.str.1044.L.str.44.L.str.934.L.str.834.L.str.734.L.str.634.L.str.534.L.str.434.L.str.334.L.str.1234.L.str.234.L.str.1134.L.str.134.L.str.1034.L.str.34.L.str.924.L.str.824.L.str.724.L.str.624.L.str.524.L.str.424.L.str.324.L.str.1224.L.str.224.L.str.1124.L.str.124.L.str.1024.L.str.24.L.str.914.L.str.814.L.str.714.L.str.614.L.str.514.L.str.414.L.str.314.L.str.1214.L.str.214.L.str.1114.L.str.114.L.str.1014.L.str.14.L.str.904.L.str.804.L.str.704.L.str.604.L.str.504.L.str.404.L.str.304.L.str.1204.L.str.204.L.str.1104.L.str.104.L.str.1004.L.str.4.L.str.993.L.str.893.L.str.793.L.str.693.L.str.593.L.str.493.L.str.393.L.str.293.L.str.1193.L.str.193.L.str.1093.L.str.93.L.str.983.L.str.883.L.str.783.L.str.683.L.str.583.L.str.483.L.str.383.L.str.283.L.str.1183.L.str.183.L.str.1083.L.str.83.L.str.973.L.str.873.L.str.773.L.str.673.L.str.573.L.str.473.L.str.373.L.str.273.L.str.1173.L.str.173.L.str.1073.L.str.73.L.str.963.L.str.863.L.str.763.L.str.663.L.str.563.L.str.463.L.str.363.L.str.263.L.str.1163.L.str.163.L.str.1063.L.str.63.L.str.953.L.str.853.L.str.753.L.str.653.L.str.553.L.str.453.L.str.353.L.str.253.L.str.1153.L.str.153.L.str.1053.L.str.53.L.str.943.L.str.843.L.str.743.L.str.643.L.str.543.L.str.443.L.str.343.L.str.243.L.str.1143.L.str.143.L.str.1043.L.str.43.L.str.933.L.str.833.L.str.733.L.str.633.L.str.533.L.str.433.L.str.333.L.str.1233.L.str.233.L.str.1133.L.str.133.L.str.1033.L.str.33.L.str.923.L.str.823.L.str.723.L.str.623.L.str.523.L.str.423.L.str.323.L.str.1223.L.str.223.L.str.1123.L.str.123.L.str.1023.L.str.23.L.str.913.L.str.813.L.str.713.L.str.613.L.str.513.L.str.413.L.str.313.L.str.1213.L.str.213.L.str.1113.L.str.113.L.str.1013.L.str.13.L.str.903.L.str.803.L.str.703.L.str.603.L.str.503.L.str.403.L.str.303.L.str.1203.L.str.203.L.str.1103.L.str.103.L.str.1003.L.str.3.L.str.992.L.str.892.L.str.792.L.str.692.L.str.592.L.str.492.L.str.392.L.str.292.L.str.1192.L.str.192.L.str.1092.L.str.92.L.str.982.L.str.882.L.str.782.L.str.682.L.str.582.L.str.482.L.str.382.L.str.282.L.str.1182.L.str.182.L.str.1082.L.str.82.L.str.972.L.str.872.L.str.772.L.str.672.L.str.572.L.str.472.L.str.372.L.str.272.L.str.1172.L.str.172.L.str.1072.L.str.72.L.str.962.L.str.862.L.str.762.L.str.662.L.str.562.L.str.462.L.str.362.L.str.262.L.str.1162.L.str.162.L.str.1062.L.str.62.L.str.952.L.str.852.L.str.752.L.str.652.L.str.552.L.str.452.L.str.352.L.str.252.L.str.1152.L.str.152.L.str.1052.L.str.52.L.str.942.L.str.842.L.str.742.L.str.642.L.str.542.L.str.442.L.str.342.L.str.242.L.str.1142.L.str.142.L.str.1042.L.str.42.L.str.932.L.str.832.L.str.732.L.str.632.L.str.532.L.str.432.L.str.332.L.str.1232.L.str.232.L.str.1132.L.str.132.L.str.1032.L.str.32.L.str.922.L.str.822.L.str.722.L.str.622.L.str.522.L.str.422.L.str.322.L.str.1222.L.str.222.L.str.1122.L.str.122.L.str.1022.L.str.22.L.str.912.L.str.812.L.str.712.L.str.612.L.str.512.L.str.412.L.str.312.L.str.1212.L.str.212.L.str.1112.L.str.112.L.str.1012.L.str.12.L.str.902.L.str.802.L.str.702.L.str.602.L.str.502.L.str.402.L.str.302.L.str.1202.L.str.202.L.str.1102.L.str.102.L.str.1002.L.str.2.L.str.991.L.str.891.L.str.791.L.str.691.L.str.591.L.str.491.L.str.391.L.str.291.L.str.1191.L.str.191.L.str.1091.L.str.91.L.str.981.L.str.881.L.str.781.L.str.681.L.str.581.L.str.481.L.str.381.L.str.281.L.str.1181.L.str.181.L.str.1081.L.str.81.L.str.971.L.str.871.L.str.771.L.str.671.L.str.571.L.str.471.L.str.371.L.str.271.L.str.1171.L.str.171.L.str.1071.L.str.71.L.str.961.L.str.861.L.str.761.L.str.661.L.str.561.L.str.461.L.str.361.L.str.261.L.str.1161.L.str.161.L.str.1061.L.str.61.L.str.951.L.str.851.L.str.751.L.str.651.L.str.551.L.str.451.L.str.351.L.str.251.L.str.1151.L.str.151.L.str.1051.L.str.51.L.str.941.L.str.841.L.str.741.L.str.641.L.str.541.L.str.441.L.str.341.L.str.241.L.str.1141.L.str.141.L.str.1041.L.str.41.L.str.931.L.str.831.L.str.731.L.str.631.L.str.531.L.str.431.L.str.331.L.str.1231.L.str.231.L.str.1131.L.str.131.L.str.1031.L.str.31.L.str.921.L.str.821.L.str.721.L.str.621.L.str.521.L.str.421.L.str.321.L.str.1221.L.str.221.L.str.1121.L.str.121.L.str.1021.L.str.21.L.str.911.L.str.811.L.str.711.L.str.611.L.str.511.L.str.411.L.str.311.L.str.1211.L.str.211.L.str.1111.L.str.111.L.str.1011.L.str.11.L.str.901.L.str.801.L.str.701.L.str.601.L.str.501.L.str.401.L.str.301.L.str.1201.L.str.201.L.str.1101.L.str.101.L.str.1001.L.str.1.rodata.str1.1.L.str.990.L.str.890.L.str.790.L.str.690.L.str.590.L.str.490.L.str.390.L.str.290.L.str.1190.L.str.190.L.str.1090.L.str.90.L.str.980.L.str.880.L.str.780.L.str.680.L.str.580.L.str.480.L.str.380.L.str.280.L.str.1180.L.str.180.L.str.1080.L.str.80.L.str.970.L.str.870.L.str.770.L.str.670.L.str.570.L.str.470.L.str.370.L.str.270.L.str.1170.L.str.170.L.str.1070.L.str.70.L.str.960.L.str.860.L.str.760.L.str.660.L.str.560.L.str.460.L.str.360.L.str.260.L.str.1160.L.str.160.L.str.1060.L.str.60.L.str.950.L.str.850.L.str.750.L.str.650.L.str.550.L.str.450.L.str.350.L.str.250.L.str.1150.L.str.150.L.str.1050.L.str.50.L.str.940.L.str.840.L.str.740.L.str.640.L.str.540.L.str.440.L.str.340.L.str.240.L.str.1140.L.str.140.L.str.1040.L.str.40.L.str.930.L.str.830.L.str.730.L.str.630.L.str.530.L.str.430.L.str.330.L.str.1230.L.str.230.L.str.1130.L.str.130.L.str.1030.L.str.30.L.str.920.L.str.820.L.str.720.L.str.620.L.str.520.L.str.420.L.str.320.L.str.1220.L.str.220.L.str.1120.L.str.120.L.str.1020.L.str.20.L.str.910.L.str.810.L.str.710.L.str.610.L.str.510.L.str.410.L.str.310.L.str.1210.L.str.210.L.str.1110.L.str.110.L.str.1010.L.str.10.L.str.900.L.str.800.L.str.700.L.str.600.L.str.500.L.str.400.L.str.300.L.str.1200.L.str.200.L.str.1100.L.str.100.L.str.1000N�=
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FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe)/usr/src/lib/libpmc/pmclog.c/usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmcunsigned intPMCLOG_OKPMCLOG_EOFPMCLOG_REQUIRE_DATAPMCLOG_ERRORpmclog_statePMCLOG_TYPE_CLOSELOGPMCLOG_TYPE_DROPNOTIFYPMCLOG_TYPE_INITIALIZEPMCLOG_TYPE_PMCALLOCATEPMCLOG_TYPE_PMCATTACHPMCLOG_TYPE_PMCDETACHPMCLOG_TYPE_PROCCSWPMCLOG_TYPE_PROCEXECPMCLOG_TYPE_PROCEXITPMCLOG_TYPE_PROCFORKPMCLOG_TYPE_SYSEXITPMCLOG_TYPE_USERDATAPMCLOG_TYPE_MAP_INPMCLOG_TYPE_MAP_OUTPMCLOG_TYPE_CALLCHAINPMCLOG_TYPE_PMCALLOCATEDYNPMCLOG_TYPE_THR_CREATEPMCLOG_TYPE_THR_EXITPMCLOG_TYPE_PROC_CREATEpmclog_typePL_STATE_NEW_RECORDPL_STATE_EXPECTING_HEADERPL_STATE_PARTIAL_RECORDPL_STATE_ERRORpmclog_parser_statePMC_CPU_AMD_K7PMC_CPU_AMD_K8PMC_CPU_INTEL_P5PMC_CPU_INTEL_P6PMC_CPU_INTEL_CLPMC_CPU_INTEL_PIIPMC_CPU_INTEL_PIIIPMC_CPU_INTEL_PMPMC_CPU_INTEL_PIVPMC_CPU_INTEL_COREPMC_CPU_INTEL_CORE2PMC_CPU_INTEL_CORE2EXTREMEPMC_CPU_INTEL_ATOMPMC_CPU_INTEL_COREI7PMC_CPU_INTEL_WESTMEREPMC_CPU_INTEL_SANDYBRIDGEPMC_CPU_INTEL_IVYBRIDGEPMC_CPU_INTEL_SANDYBRIDGE_XEONPMC_CPU_INTEL_IVYBRIDGE_XEONPMC_CPU_INTEL_HASWELLPMC_CPU_INTEL_ATOM_SILVERMONTPMC_CPU_INTEL_NEHALEM_EXPMC_CPU_INTEL_WESTMERE_EXPMC_CPU_INTEL_HASWELL_XEONPMC_CPU_INTEL_BROADWELLPMC_CPU_INTEL_BROADWELL_XEONPMC_CPU_INTEL_SKYLAKEPMC_CPU_INTEL_SKYLAKE_XEONPMC_CPU_INTEL_ATOM_GOLDMONTPMC_CPU_INTEL_XSCALEPMC_CPU_MIPS_24KPMC_CPU_MIPS_OCTEONPMC_CPU_MIPS_74KPMC_CPU_MIPS_BERIPMC_CPU_PPC_7450PMC_CPU_PPC_E500PMC_CPU_PPC_970PMC_CPU_PPC_POWER8PMC_CPU_GENERICPMC_CPU_ARMV7_CORTEX_A5PMC_CPU_ARMV7_CORTEX_A7PMC_CPU_ARMV7_CORTEX_A8PMC_CPU_ARMV7_CORTEX_A9PMC_CPU_ARMV7_CORTEX_A15PMC_CPU_ARMV7_CORTEX_A17PMC_CPU_ARMV8_CORTEX_A53PMC_CPU_ARMV8_CORTEX_A57PMC_CPU_ARMV8_CORTEX_A76pmc_cputypePMC_EV_TSC__BLOCK_STARTPMC_EV_TSC_TSCPMC_EV_IAF__BLOCK_STARTPMC_EV_IAF_INSTR_RETIRED_ANYPMC_EV_IAF_CPU_CLK_UNHALTED_COREPMC_EV_IAF_CPU_CLK_UNHALTED_REFPMC_EV_K7__BLOCK_STARTPMC_EV_K7_DC_ACCESSESPMC_EV_K7_DC_MISSESPMC_EV_K7_DC_REFILLS_FROM_L2PMC_EV_K7_DC_REFILLS_FROM_SYSTEMPMC_EV_K7_DC_WRITEBACKSPMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITSPMC_EV_K7_L1_AND_L2_DTLB_MISSESPMC_EV_K7_MISALIGNED_REFERENCESPMC_EV_K7_IC_FETCHESPMC_EV_K7_IC_MISSESPMC_EV_K7_L1_ITLB_MISSESPMC_EV_K7_L1_L2_ITLB_MISSESPMC_EV_K7_RETIRED_INSTRUCTIONSPMC_EV_K7_RETIRED_OPSPMC_EV_K7_RETIRED_BRANCHESPMC_EV_K7_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_TAKEN_BRANCHESPMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K7_RETIRED_RESYNC_BRANCHESPMC_EV_K7_INTERRUPTS_MASKED_CYCLESPMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K7_HARDWARE_INTERRUPTSPMC_EV_K8__BLOCK_STARTPMC_EV_K8_FP_DISPATCHED_FPU_OPSPMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIREDPMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPSPMC_EV_K8_LS_SEGMENT_REGISTER_LOADPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODEPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_LS_BUFFER2_FULLPMC_EV_K8_LS_LOCKED_OPERATIONPMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONSPMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONSPMC_EV_K8_DC_ACCESSPMC_EV_K8_DC_MISSPMC_EV_K8_DC_REFILL_FROM_L2PMC_EV_K8_DC_REFILL_FROM_SYSTEMPMC_EV_K8_DC_COPYBACKPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HITPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISSPMC_EV_K8_DC_MISALIGNED_DATA_REFERENCEPMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCELPMC_EV_K8_DC_ONE_BIT_ECC_ERRORPMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONSPMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKSPMC_EV_K8_BU_CPU_CLK_UNHALTEDPMC_EV_K8_BU_INTERNAL_L2_REQUESTPMC_EV_K8_BU_FILL_REQUEST_L2_MISSPMC_EV_K8_BU_FILL_INTO_L2PMC_EV_K8_IC_FETCHPMC_EV_K8_IC_MISSPMC_EV_K8_IC_REFILL_FROM_L2PMC_EV_K8_IC_REFILL_FROM_SYSTEMPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HITPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISSPMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_IC_INSTRUCTION_FETCH_STALLPMC_EV_K8_IC_RETURN_STACK_HITPMC_EV_K8_IC_RETURN_STACK_OVERFLOWPMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_UOPSPMC_EV_K8_FR_RETIRED_BRANCHESPMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHESPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K8_FR_RETIRED_RESYNCSPMC_EV_K8_FR_RETIRED_NEAR_RETURNSPMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPAREPMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSPMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLESPMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTSPMC_EV_K8_FR_DECODER_EMPTYPMC_EV_K8_FR_DISPATCH_STALLSPMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIREPMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATIONPMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOADPMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIETPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDINGPMC_EV_K8_FR_FPU_EXCEPTIONSPMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENTPMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWPMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDPMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUNDPMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATIONPMC_EV_K8_NB_SIZED_COMMANDSPMC_EV_K8_NB_PROBE_RESULTPMC_EV_K8_NB_HT_BUS0_BANDWIDTHPMC_EV_K8_NB_HT_BUS1_BANDWIDTHPMC_EV_K8_NB_HT_BUS2_BANDWIDTHPMC_EV_MIPS24K__BLOCK_STARTPMC_EV_MIPS24K_CYCLEPMC_EV_MIPS24K_INSTR_EXECUTEDPMC_EV_MIPS24K_BRANCH_COMPLETEDPMC_EV_MIPS24K_BRANCH_MISPREDPMC_EV_MIPS24K_RETURNPMC_EV_MIPS24K_RETURN_MISPREDPMC_EV_MIPS24K_RETURN_NOT_31PMC_EV_MIPS24K_RETURN_NOTPREDPMC_EV_MIPS24K_ITLB_ACCESSPMC_EV_MIPS24K_ITLB_MISSPMC_EV_MIPS24K_DTLB_ACCESSPMC_EV_MIPS24K_DTLB_MISSPMC_EV_MIPS24K_JTLB_IACCESSPMC_EV_MIPS24K_JTLB_IMISSPMC_EV_MIPS24K_JTLB_DACCESSPMC_EV_MIPS24K_JTLB_DMISSPMC_EV_MIPS24K_IC_FETCHPMC_EV_MIPS24K_IC_MISSPMC_EV_MIPS24K_DC_LOADSTOREPMC_EV_MIPS24K_DC_WRITEBACKPMC_EV_MIPS24K_DC_MISSPMC_EV_MIPS24K_STORE_MISSPMC_EV_MIPS24K_LOAD_MISSPMC_EV_MIPS24K_INTEGER_COMPLETEDPMC_EV_MIPS24K_FP_COMPLETEDPMC_EV_MIPS24K_LOAD_COMPLETEDPMC_EV_MIPS24K_STORE_COMPLETEDPMC_EV_MIPS24K_BARRIER_COMPLETEDPMC_EV_MIPS24K_MIPS16_COMPLETEDPMC_EV_MIPS24K_NOP_COMPLETEDPMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETEDPMC_EV_MIPS24K_RF_STALLPMC_EV_MIPS24K_INSTR_REFETCHPMC_EV_MIPS24K_STORE_COND_COMPLETEDPMC_EV_MIPS24K_STORE_COND_FAILEDPMC_EV_MIPS24K_ICACHE_REQUESTSPMC_EV_MIPS24K_ICACHE_HITPMC_EV_MIPS24K_L2_WRITEBACKPMC_EV_MIPS24K_L2_ACCESSPMC_EV_MIPS24K_L2_MISSPMC_EV_MIPS24K_L2_ERR_CORRECTEDPMC_EV_MIPS24K_EXCEPTIONSPMC_EV_MIPS24K_RF_CYCLES_STALLEDPMC_EV_MIPS24K_IFU_CYCLES_STALLEDPMC_EV_MIPS24K_ALU_CYCLES_STALLEDPMC_EV_MIPS24K_UNCACHED_LOADPMC_EV_MIPS24K_UNCACHED_STOREPMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETEDPMC_EV_MIPS24K_MFTC_COMPLETEDPMC_EV_MIPS24K_IC_BLOCKED_CYCLESPMC_EV_MIPS24K_DC_BLOCKED_CYCLESPMC_EV_MIPS24K_L2_IMISS_STALL_CYCLESPMC_EV_MIPS24K_L2_DMISS_STALL_CYCLESPMC_EV_MIPS24K_DMISS_CYCLESPMC_EV_MIPS24K_L2_MISS_CYCLESPMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLESPMC_EV_MIPS24K_MDU_STALL_CYCLESPMC_EV_MIPS24K_FPU_STALL_CYCLESPMC_EV_MIPS24K_CP2_STALL_CYCLESPMC_EV_MIPS24K_COREXTEND_STALL_CYCLESPMC_EV_MIPS24K_ISPRAM_STALL_CYCLESPMC_EV_MIPS24K_DSPRAM_STALL_CYCLESPMC_EV_MIPS24K_CACHE_STALL_CYCLESPMC_EV_MIPS24K_LOAD_TO_USE_STALLSPMC_EV_MIPS24K_BASE_MISPRED_STALLSPMC_EV_MIPS24K_CPO_READ_STALLSPMC_EV_MIPS24K_BRANCH_MISPRED_CYCLESPMC_EV_MIPS24K_IFETCH_BUFFER_FULLPMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATEDPMC_EV_MIPS24K_EJTAG_ITRIGGERPMC_EV_MIPS24K_EJTAG_DTRIGGERPMC_EV_MIPS24K_FSB_LT_QUARTERPMC_EV_MIPS24K_FSB_QUARTER_TO_HALFPMC_EV_MIPS24K_FSB_GT_HALFPMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_LDQ_LT_QUARTERPMC_EV_MIPS24K_LDQ_QUARTER_TO_HALFPMC_EV_MIPS24K_LDQ_GT_HALFPMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_WBB_LT_QUARTERPMC_EV_MIPS24K_WBB_QUARTER_TO_HALFPMC_EV_MIPS24K_WBB_GT_HALFPMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_REQUEST_LATENCYPMC_EV_MIPS24K_REQUEST_COUNTPMC_EV_OCTEON__BLOCK_STARTPMC_EV_OCTEON_CLKPMC_EV_OCTEON_ISSUEPMC_EV_OCTEON_RETPMC_EV_OCTEON_NISSUEPMC_EV_OCTEON_SISSUEPMC_EV_OCTEON_DISSUEPMC_EV_OCTEON_IFIPMC_EV_OCTEON_BRPMC_EV_OCTEON_BRMISPMC_EV_OCTEON_JPMC_EV_OCTEON_JMISPMC_EV_OCTEON_REPLAYPMC_EV_OCTEON_IUNAPMC_EV_OCTEON_TRAPPMC_EV_OCTEON_UULOADPMC_EV_OCTEON_UUSTOREPMC_EV_OCTEON_ULOADPMC_EV_OCTEON_USTOREPMC_EV_OCTEON_ECPMC_EV_OCTEON_MCPMC_EV_OCTEON_CCPMC_EV_OCTEON_CSRCPMC_EV_OCTEON_CFETCHPMC_EV_OCTEON_CPREFPMC_EV_OCTEON_ICAPMC_EV_OCTEON_IIPMC_EV_OCTEON_IPPMC_EV_OCTEON_CIMISSPMC_EV_OCTEON_WBUFPMC_EV_OCTEON_WDATPMC_EV_OCTEON_WBUFLDPMC_EV_OCTEON_WBUFFLPMC_EV_OCTEON_WBUFTRPMC_EV_OCTEON_BADDPMC_EV_OCTEON_BADDL2PMC_EV_OCTEON_BFILLPMC_EV_OCTEON_DDIDSPMC_EV_OCTEON_IDIDSPMC_EV_OCTEON_DIDNAPMC_EV_OCTEON_LDSPMC_EV_OCTEON_LMLDSPMC_EV_OCTEON_IOLDSPMC_EV_OCTEON_DMLDSPMC_EV_OCTEON_STSPMC_EV_OCTEON_LMSTSPMC_EV_OCTEON_IOSTSPMC_EV_OCTEON_IOBDMAPMC_EV_OCTEON_DTLBPMC_EV_OCTEON_DTLBADPMC_EV_OCTEON_ITLBPMC_EV_OCTEON_SYNCPMC_EV_OCTEON_SYNCIOBPMC_EV_OCTEON_SYNCWPMC_EV_MIPS74K__BLOCK_STARTPMC_EV_MIPS74K_CYCLESPMC_EV_MIPS74K_INSTR_EXECUTEDPMC_EV_MIPS74K_PREDICTED_JR_31PMC_EV_MIPS74K_JR_31_MISPREDICTIONSPMC_EV_MIPS74K_REDIRECT_STALLSPMC_EV_MIPS74K_JR_31_NO_PREDICTIONSPMC_EV_MIPS74K_ITLB_ACCESSESPMC_EV_MIPS74K_ITLB_MISSESPMC_EV_MIPS74K_JTLB_INSN_MISSESPMC_EV_MIPS74K_ICACHE_ACCESSESPMC_EV_MIPS74K_ICACHE_MISSESPMC_EV_MIPS74K_ICACHE_MISS_STALLSPMC_EV_MIPS74K_UNCACHED_IFETCH_STALLSPMC_EV_MIPS74K_PDTRACE_BACK_STALLSPMC_EV_MIPS74K_IFU_REPLAYSPMC_EV_MIPS74K_KILLED_FETCH_SLOTSPMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLESPMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLESPMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLESPMC_EV_MIPS74K_DDQ0_FULL_DR_STALLSPMC_EV_MIPS74K_DDQ1_FULL_DR_STALLSPMC_EV_MIPS74K_ALCB_FULL_DR_STALLSPMC_EV_MIPS74K_AGCB_FULL_DR_STALLSPMC_EV_MIPS74K_CLDQ_FULL_DR_STALLSPMC_EV_MIPS74K_IODQ_FULL_DR_STALLSPMC_EV_MIPS74K_ALU_EMPTY_CYCLESPMC_EV_MIPS74K_AGEN_EMPTY_CYCLESPMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLESPMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLESPMC_EV_MIPS74K_ALU_BUBBLE_CYCLESPMC_EV_MIPS74K_AGEN_BUBBLE_CYCLESPMC_EV_MIPS74K_SINGLE_ISSUE_CYCLESPMC_EV_MIPS74K_DUAL_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLESPMC_EV_MIPS74K_JALR_JALR_HB_INSNSPMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTSPMC_EV_MIPS74K_DCACHE_LOAD_ACCESSESPMC_EV_MIPS74K_DCACHE_ACCESSESPMC_EV_MIPS74K_DCACHE_WRITEBACKSPMC_EV_MIPS74K_DCACHE_MISSESPMC_EV_MIPS74K_JTLB_DATA_ACCESSESPMC_EV_MIPS74K_JTLB_DATA_MISSESPMC_EV_MIPS74K_LOAD_STORE_REPLAYSPMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASESPMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLESPMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTSPMC_EV_MIPS74K_L2_CACHE_WRITEBACKSPMC_EV_MIPS74K_L2_CACHE_ACCESSESPMC_EV_MIPS74K_L2_CACHE_MISSESPMC_EV_MIPS74K_L2_CACHE_MISS_CYCLESPMC_EV_MIPS74K_FSB_FULL_STALLSPMC_EV_MIPS74K_FSB_OVER_50_FULLPMC_EV_MIPS74K_LDQ_FULL_STALLSPMC_EV_MIPS74K_LDQ_OVER_50_FULLPMC_EV_MIPS74K_WBB_FULL_STALLSPMC_EV_MIPS74K_WBB_OVER_50_FULLPMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYSPMC_EV_MIPS74K_CP1_CP2_LOAD_INSNSPMC_EV_MIPS74K_JR_NON_31_INSNSPMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNSPMC_EV_MIPS74K_BRANCH_INSNSPMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNSPMC_EV_MIPS74K_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_COND_BRANCH_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNSPMC_EV_MIPS74K_INTEGER_INSNSPMC_EV_MIPS74K_FPU_INSNSPMC_EV_MIPS74K_LOAD_INSNSPMC_EV_MIPS74K_STORE_INSNSPMC_EV_MIPS74K_J_JAL_INSNSPMC_EV_MIPS74K_MIPS16_INSNSPMC_EV_MIPS74K_NOP_INSNSPMC_EV_MIPS74K_NT_MUL_DIV_INSNSPMC_EV_MIPS74K_DSP_INSNSPMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_DSP_BRANCH_INSNSPMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_UNCACHED_LOAD_INSNSPMC_EV_MIPS74K_UNCACHED_STORE_INSNSPMC_EV_MIPS74K_EJTAG_INSN_TRIGGERSPMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONSPMC_EV_MIPS74K_SC_INSNSPMC_EV_MIPS74K_FAILED_SC_INSNSPMC_EV_MIPS74K_PREFETCH_INSNSPMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNSPMC_EV_MIPS74K_NO_INSN_CYCLESPMC_EV_MIPS74K_LOAD_MISS_INSNSPMC_EV_MIPS74K_ONE_INSN_CYCLESPMC_EV_MIPS74K_TWO_INSNS_CYCLESPMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLESPMC_EV_MIPS74K_CP1_CP2_STORE_INSNSPMC_EV_MIPS74K_MISPREDICTION_STALLSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLESPMC_EV_MIPS74K_EXCEPTIONS_TAKENPMC_EV_MIPS74K_GRADUATION_REPLAYSPMC_EV_MIPS74K_COREEXTEND_EVENTSPMC_EV_MIPS74K_ISPRAM_EVENTSPMC_EV_MIPS74K_DSPRAM_EVENTSPMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORSPMC_EV_MIPS74K_SYSTEM_EVENT_0PMC_EV_MIPS74K_SYSTEM_EVENT_1PMC_EV_MIPS74K_SYSTEM_EVENT_2PMC_EV_MIPS74K_SYSTEM_EVENT_3PMC_EV_MIPS74K_SYSTEM_EVENT_4PMC_EV_MIPS74K_SYSTEM_EVENT_5PMC_EV_MIPS74K_SYSTEM_EVENT_6PMC_EV_MIPS74K_SYSTEM_EVENT_7PMC_EV_MIPS74K_OCP_ALL_REQUESTSPMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_READ_REQUESTSPMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTSPMC_EV_MIPS74K_FSB_LESS_25_FULLPMC_EV_MIPS74K_FSB_25_50_FULLPMC_EV_MIPS74K_LDQ_LESS_25_FULLPMC_EV_MIPS74K_LDQ_25_50_FULLPMC_EV_MIPS74K_WBB_LESS_25_FULLPMC_EV_MIPS74K_WBB_25_50_FULLPMC_EV_BERI__BLOCK_STARTPMC_EV_BERI_CYCLEPMC_EV_BERI_INSTPMC_EV_BERI_INST_USERPMC_EV_BERI_INST_KERNELPMC_EV_BERI_IMPRECISE_SETBOUNDSPMC_EV_BERI_UNREPRESENTABLE_CAPSPMC_EV_BERI_ITLB_MISSPMC_EV_BERI_DTLB_MISSPMC_EV_BERI_ICACHE_WRITE_HITPMC_EV_BERI_ICACHE_WRITE_MISSPMC_EV_BERI_ICACHE_READ_HITPMC_EV_BERI_ICACHE_READ_MISSPMC_EV_BERI_ICACHE_EVICTPMC_EV_BERI_DCACHE_WRITE_HITPMC_EV_BERI_DCACHE_WRITE_MISSPMC_EV_BERI_DCACHE_READ_HITPMC_EV_BERI_DCACHE_READ_MISSPMC_EV_BERI_DCACHE_EVICTPMC_EV_BERI_DCACHE_SET_TAG_WRITEPMC_EV_BERI_DCACHE_SET_TAG_READPMC_EV_BERI_L2CACHE_WRITE_HITPMC_EV_BERI_L2CACHE_WRITE_MISSPMC_EV_BERI_L2CACHE_READ_HITPMC_EV_BERI_L2CACHE_READ_MISSPMC_EV_BERI_L2CACHE_EVICTPMC_EV_BERI_L2CACHE_SET_TAG_WRITEPMC_EV_BERI_L2CACHE_SET_TAG_READPMC_EV_BERI_MEM_BYTE_READPMC_EV_BERI_MEM_BYTE_WRITEPMC_EV_BERI_MEM_HWORD_READPMC_EV_BERI_MEM_HWORD_WRITEPMC_EV_BERI_MEM_WORD_READPMC_EV_BERI_MEM_WORD_WRITEPMC_EV_BERI_MEM_DWORD_READPMC_EV_BERI_MEM_DWORD_WRITEPMC_EV_BERI_MEM_CAP_READPMC_EV_BERI_MEM_CAP_WRITEPMC_EV_BERI_MEM_CAP_READ_TAG_SETPMC_EV_BERI_MEM_CAP_WRITE_TAG_SETPMC_EV_BERI_TAGCACHE_WRITE_HITPMC_EV_BERI_TAGCACHE_WRITE_MISSPMC_EV_BERI_TAGCACHE_READ_HITPMC_EV_BERI_TAGCACHE_READ_MISSPMC_EV_BERI_TAGCACHE_EVICTPMC_EV_BERI_L2CACHEMASTER_READ_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_L2CACHEMASTER_READ_RSPPMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLITPMC_EV_BERI_L2CACHEMASTER_WRITE_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_TAGCACHEMASTER_READ_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLITPMC_EV_BERI_TAGCACHEMASTER_WRITE_RSPPMC_EV_UCP__BLOCK_STARTPMC_EV_UCP_EVENT_0CH_04H_EPMC_EV_UCP_EVENT_0CH_04H_FPMC_EV_UCP_EVENT_0CH_04H_MPMC_EV_UCP_EVENT_0CH_04H_SPMC_EV_UCP_EVENT_0CH_08H_EPMC_EV_UCP_EVENT_0CH_08H_FPMC_EV_UCP_EVENT_0CH_08H_MPMC_EV_UCP_EVENT_0CH_08H_SPMC_EV_PPC7450__BLOCK_STARTPMC_EV_PPC7450_CYCLEPMC_EV_PPC7450_INSTR_COMPLETEDPMC_EV_PPC7450_TLB_BIT_TRANSITIONSPMC_EV_PPC7450_INSTR_DISPATCHEDPMC_EV_PPC7450_PMON_EXCEPTPMC_EV_PPC7450_PMON_SIGPMC_EV_PPC7450_VPU_INSTR_COMPLETEDPMC_EV_PPC7450_VFPU_INSTR_COMPLETEDPMC_EV_PPC7450_VIU1_INSTR_COMPLETEDPMC_EV_PPC7450_VIU2_INSTR_COMPLETEDPMC_EV_PPC7450_MTVSCR_INSTR_COMPLETEDPMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETEDPMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLESPMC_EV_PPC7450_MFVSCR_SYNC_CYCLESPMC_EV_PPC7450_VSCR_SAT_SETPMC_EV_PPC7450_STORE_INSTR_COMPLETEDPMC_EV_PPC7450_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_SNOOPSPMC_EV_PPC7450_UNRESOLVED_BRANCHESPMC_EV_PPC7450_SPEC_BUFFER_CYCLESPMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLESPMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITSPMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHEDPMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRSPMC_EV_PPC7450_IU2_INSTR_COMPLETEDPMC_EV_PPC7450_BRANCHES_COMPLETEDPMC_EV_PPC7450_EIEIO_INSTR_COMPLETEDPMC_EV_PPC7450_MTSPR_INSTR_COMPLETEDPMC_EV_PPC7450_SC_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_COMPLETEDPMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSESPMC_EV_PPC7450_INSTR_BKPT_MATCHESPMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIEDPMC_EV_PPC7450_LOAD_MISS_ALIASPMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCHPMC_EV_PPC7450_TOUCH_ALIASPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUEPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUTPMC_EV_PPC7450_L1_DATA_SNOOP_HITSPMC_EV_PPC7450_WRITE_THROUGH_STORESPMC_EV_PPC7450_CACHE_INHIBITED_STORESPMC_EV_PPC7450_L1_DATA_LOAD_HITPMC_EV_PPC7450_L1_DATA_TOUCH_HITPMC_EV_PPC7450_L1_DATA_STORE_HITPMC_EV_PPC7450_L1_DATA_TOTAL_HITSPMC_EV_PPC7450_DST_INSTR_DISPATCHEDPMC_EV_PPC7450_REFRESHED_DSTSPMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHESPMC_EV_PPC7450_DSS_INSTR_COMPLETEDPMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_HITPMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FPU_RENORMALIZATIONPMC_EV_PPC7450_FPU_DENORMALIZATIONPMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSUPMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALLPMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALLPMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LMQ_FULL_STALLPMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSUPMC_EV_PPC7450_LSU_RA_LATCH_STALLPMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALLPMC_EV_PPC7450_LSU_LMQ_INDEX_ALIASPMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIASPMC_EV_PPC7450_LSU_CSQ_FORWARDINGPMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISHPMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETEDPMC_EV_PPC7450_LSU_MISALIGN_STALLPMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_DENORMALIZED_RESULTPMC_EV_PPC7450_L1_DATA_TOTAL_MISSESPMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUEPMC_EV_PPC7450_LSU_INSTR_COMPLETEDPMC_EV_PPC7450_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_COMPLETEDPMC_EV_PPC7450_TLBIE_INSTR_COMPLETEDPMC_EV_PPC7450_LWARX_INSTR_COMPLETEDPMC_EV_PPC7450_MFSPR_INSTR_COMPLETEDPMC_EV_PPC7450_REFETCH_SERIALIZATIONPMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHEDPMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETEDPMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSESPMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISSPMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISSPMC_EV_PPC7450_L1_DATA_STORE_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_CYCLES_USEDPMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELYPMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_MISSPMC_EV_PPC7450_VTQ_LINE_FETCHPMC_EV_PPC7450_TLBIE_SNOOPSPMC_EV_PPC7450_L1_INSTR_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2PMC_EV_PPC7450_STORE_MERGE_GATHERPMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTESPMC_EV_PPC7450_DATA_BKPT_MATCHESPMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSEDPMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCYPMC_EV_PPC7450_BTIC_MISSPMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVEDPMC_EV_PPC7450_FPR_ISSUE_STALLEDPMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USERPMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLEPMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_VR_STALLSPMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIESPMC_EV_PPC7450_FPU_INSTR_COMPLETEDPMC_EV_PPC7450_STWCX_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_INSTR_PIECESPMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_DTLB_MISSESPMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_CACHE_OP_HITPMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_PUSHESPMC_EV_PPC7450_L1_DATA_TOTAL_MISSPMC_EV_PPC7450_VT2_FETCHESPMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSEDPMC_EV_PPC7450_BRANCH_FLUSHESPMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCYPMC_EV_PPC7450_FAST_BTIC_HITPMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTEDPMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETEDPMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLEDPMC_EV_PPC7450_IU1_INSTR_COMPLETEDPMC_EV_PPC7450_DSSALL_INSTR_COMPLETEDPMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_PIECESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLESPMC_EV_PPC7450_SNOOP_RETRIESPMC_EV_PPC7450_SUCCESSFUL_STWCXPMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHESPMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_MISPREDICTED_BRANCHESPMC_EV_PPC7450_FOLDED_BRANCHESPMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSUPMC_EV_PPC7450_L2_CACHE_HITSPMC_EV_PPC7450_L3_CACHE_HITSPMC_EV_PPC7450_L2_INSTR_CACHE_MISSESPMC_EV_PPC7450_L3_INSTR_CACHE_MISSESPMC_EV_PPC7450_L2_DATA_CACHE_MISSESPMC_EV_PPC7450_L3_DATA_CACHE_MISSESPMC_EV_PPC7450_L2_LOAD_HITSPMC_EV_PPC7450_L2_STORE_HITSPMC_EV_PPC7450_L3_LOAD_HITSPMC_EV_PPC7450_L3_STORE_HITSPMC_EV_PPC7450_L2_TOUCH_HITSPMC_EV_PPC7450_L3_TOUCH_HITSPMC_EV_PPC7450_SNOOP_MODIFIEDPMC_EV_PPC7450_SNOOP_VALIDPMC_EV_PPC7450_INTERVENTIONPMC_EV_PPC7450_L2_CACHE_MISSESPMC_EV_PPC7450_L3_CACHE_MISSESPMC_EV_PPC7450_L2_CACHE_CASTOUTSPMC_EV_PPC7450_L3_CACHE_CASTOUTSPMC_EV_PPC7450_L2SQ_FULL_CYCLESPMC_EV_PPC7450_L3SQ_FULL_CYCLESPMC_EV_PPC7450_RAQ_FULL_CYCLESPMC_EV_PPC7450_WAQ_FULL_CYCLESPMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_PUSHESPMC_EV_PPC7450_EXTERNAL_SNOOP_RETRYPMC_EV_PPC7450_DTQ_FULL_CYCLESPMC_EV_PPC7450_BUS_RETRYPMC_EV_PPC7450_L2_VALID_REQUESTPMC_EV_PPC7450_BORDQ_FULLPMC_EV_PPC7450_BUS_TAS_FOR_READSPMC_EV_PPC7450_BUS_TAS_FOR_WRITESPMC_EV_PPC7450_BUS_READS_NOT_RETRIEDPMC_EV_PPC7450_BUS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRYPMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENTPMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISIONPMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERINGPMC_EV_PPC7450_SNOOP_REQUESTSPMC_EV_PPC7450_PREFETCH_ENGINE_REQUESTPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOADPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STOREPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_FULLPMC_EV_PPC970__BLOCK_STARTPMC_EV_PPC970_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_GROUP_DISPATCHPMC_EV_PPC970_MARKED_STORE_COMPLETEDPMC_EV_PPC970_GCT_EMPTYPMC_EV_PPC970_RUN_CYCLESPMC_EV_PPC970_OVERFLOWPMC_EV_PPC970_CYCLESPMC_EV_PPC970_THRESHOLD_TIMEOUTPMC_EV_PPC970_GROUP_DISPATCHPMC_EV_PPC970_BR_MARKED_INSTR_FINISHPMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULLPMC_EV_PPC970_STOP_COMPLETIONPMC_EV_PPC970_LSU_EMPTYPMC_EV_PPC970_MARKED_STORE_WITH_INTRPMC_EV_PPC970_CYCLES_IN_SUPERPMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_FXU0_IDLE_FXU1_BUSYPMC_EV_PPC970_SRQ_EMPTYPMC_EV_PPC970_MARKED_GROUP_COMPLETEDPMC_EV_PPC970_CR_MARKED_INSTR_FINISHPMC_EV_PPC970_DISPATCH_SUCCESSPMC_EV_PPC970_FXU0_IDLE_FXU1_IDLEPMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETEDPMC_EV_PPC970_GROUP_MARKED_IDUPMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUTPMC_EV_PPC970_FXU0_BUSY_FXU1_BUSYPMC_EV_PPC970_MARKED_STORE_SENT_TO_STSPMC_EV_PPC970_FXU_MARKED_INSTR_FINISHEDPMC_EV_PPC970_MARKED_GROUP_ISSUEDPMC_EV_PPC970_FXU0_BUSY_FXU1_IDLEPMC_EV_PPC970_GROUP_COMPLETEDPMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNITPMC_EV_PPC970_EXTERNAL_INTERRUPTPMC_EV_PPC970_GROUP_DISPATCH_REJECTPMC_EV_PPC970_LSU_MARKED_INSTR_FINISHPMC_EV_PPC970_TIMEBASE_EVENTPMC_EV_PPC970_LSU_COMPLETION_STALLPMC_EV_PPC970_FXU_COMPLETION_STALLPMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALLPMC_EV_PPC970_FPU_COMPLETION_STALLPMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_REJECT_COMPLETION_STALLPMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISSPMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISSPMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICTPMC_EV_PPC970_BUS_HIGHPMC_EV_PPC970_BUS_LOWPMC_EV_PPC970_ADDERPMC_EV_POWER8__BLOCK_STARTPMC_EV_POWER8_CYCLESPMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETEDPMC_EV_POWER8_FPU_INSTR_COMPLETEDPMC_EV_POWER8_ERAT_INSTR_MISSPMC_EV_POWER8_CYCLES_IDLEPMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNINGPMC_EV_POWER8_STORE_COMPLETEDPMC_EV_POWER8_INSTR_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNINGPMC_EV_POWER8_ERAT_DATA_MISSPMC_EV_POWER8_EXTERNAL_INTERRUPTPMC_EV_POWER8_BRANCH_TAKENPMC_EV_POWER8_L1_INSTR_MISSPMC_EV_POWER8_L2_LOAD_MISSPMC_EV_POWER8_STORE_NO_REAL_ADDRPMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNINGPMC_EV_POWER8_L1_LOAD_MISSPMC_EV_POWER8_TIMEBASE_EVENTPMC_EV_POWER8_L3_INSTR_MISSPMC_EV_POWER8_TLB_DATA_MISSPMC_EV_POWER8_L3_LOAD_MISSPMC_EV_POWER8_LOAD_NO_REAL_ADDRPMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNING_PURR_INCPMC_EV_POWER8_BRANCH_MISPREDICTEDPMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDEDPMC_EV_POWER8_INSTR_COMPLETED_RUNNINGPMC_EV_POWER8_TLB_INSTR_MISSPMC_EV_POWER8_CACHE_LOAD_MISSPMC_EV_POWER8_INSTR_COMPLETEDPMC_EV_E500__BLOCK_STARTPMC_EV_E500_CYCLESPMC_EV_E500_INSTR_COMPLETEDPMC_EV_E500_UOPS_COMPLETEDPMC_EV_E500_INSTR_FETCHEDPMC_EV_E500_UOPS_DECODEDPMC_EV_E500_PM_EVENT_TRANSITIONSPMC_EV_E500_PM_EVENT_CYCLESPMC_EV_E500_BRANCH_INSTRS_COMPLETEDPMC_EV_E500_LOAD_UOPS_COMPLETEDPMC_EV_E500_STORE_UOPS_COMPLETEDPMC_EV_E500_CQ_REDIRECTSPMC_EV_E500_BRANCHES_FINISHEDPMC_EV_E500_TAKEN_BRANCHES_FINISHEDPMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTBPMC_EV_E500_BRANCH_MISPREDPMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTIONPMC_EV_E500_BTB_HITS_PSEUDO_HITSPMC_EV_E500_CYCLES_DECODE_STALLEDPMC_EV_E500_CYCLES_ISSUE_STALLEDPMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLEDPMC_EV_E500_CYCLES_SU1_SCHED_STALLEDPMC_EV_E500_CYCLES_SU2_SCHED_STALLEDPMC_EV_E500_CYCLES_MU_SCHED_STALLEDPMC_EV_E500_CYCLES_LRU_SCHED_STALLEDPMC_EV_E500_CYCLES_BU_SCHED_STALLEDPMC_EV_E500_TOTAL_TRANSLATEDPMC_EV_E500_LOADS_TRANSLATEDPMC_EV_E500_STORES_TRANSLATEDPMC_EV_E500_TOUCHES_TRANSLATEDPMC_EV_E500_CACHEOPS_TRANSLATEDPMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATEDPMC_EV_E500_GUARDED_LOADS_TRANSLATEDPMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATEDPMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATEDPMC_EV_E500_TOTAL_ALLOCATED_TO_DLFBPMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFBPMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETEDPMC_EV_E500_DATA_L1_CACHE_LOCKSPMC_EV_E500_DATA_L1_CACHE_RELOADSPMC_EV_E500_DATA_L1_CACHE_CASTOUTSPMC_EV_E500_LOAD_MISS_DLFB_FULLPMC_EV_E500_LOAD_MISS_LDQ_FULLPMC_EV_E500_LOAD_GUARDED_MISSPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULLPMC_EV_E500_ADDRESS_COLLISIONPMC_EV_E500_DATA_MMU_MISSPMC_EV_E500_DATA_MMU_BUSYPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESSPMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLESPMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLESPMC_EV_E500_LOAD_GUARDED_MISS_CYCLESPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLESPMC_EV_E500_ADDRESS_COLLISION_CYCLESPMC_EV_E500_DATA_MMU_MISS_CYCLESPMC_EV_E500_DATA_MMU_BUSY_CYCLESPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLESPMC_EV_E500_INSTR_L1_CACHE_LOCKSPMC_EV_E500_INSTR_L1_CACHE_RELOADSPMC_EV_E500_INSTR_L1_CACHE_FETCHESPMC_EV_E500_INSTR_MMU_TLB4K_RELOADSPMC_EV_E500_INSTR_MMU_VSP_RELOADSPMC_EV_E500_DATA_MMU_TLB4K_RELOADSPMC_EV_E500_DATA_MMU_VSP_RELOADSPMC_EV_E500_L2MMU_MISSESPMC_EV_E500_BIU_MASTER_REQUESTSPMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTSPMC_EV_E500_BIU_MASTER_RETRIESPMC_EV_E500_SNOOP_REQUESTSPMC_EV_E500_SNOOP_HITSPMC_EV_E500_SNOOP_PUSHESPMC_EV_E500_SNOOP_RETRIESPMC_EV_E500_DLFB_LOAD_MISS_CYCLESPMC_EV_E500_ILFB_FETCH_MISS_CYCLESPMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLESPMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_PMC0_OVERFLOWPMC_EV_E500_PMC1_OVERFLOWPMC_EV_E500_PMC2_OVERFLOWPMC_EV_E500_PMC3_OVERFLOWPMC_EV_E500_INTERRUPTS_TAKENPMC_EV_E500_EXT_INPUT_INTR_TAKENPMC_EV_E500_CRIT_INPUT_INTR_TAKENPMC_EV_E500_SYSCALL_TRAP_INTRPMC_EV_E500_TLB_BIT_TRANSITIONSPMC_EV_E500_L2_LINEFILL_BUFFERPMC_EV_E500_LV2_VSPMC_EV_E500_CASTOUTS_RELEASEDPMC_EV_E500_INTV_ALLOCATIONSPMC_EV_E500_DLFB_RETRIES_TO_MBARPMC_EV_E500_STORE_RETRIESPMC_EV_E500_STASH_L1_HITSPMC_EV_E500_STASH_L2_HITSPMC_EV_E500_STASH_BUSY_1PMC_EV_E500_STASH_BUSY_2PMC_EV_E500_STASH_BUSY_3PMC_EV_E500_STASH_HITSPMC_EV_E500_STASH_HIT_DLFBPMC_EV_E500_STASH_REQUESTSPMC_EV_E500_STASH_REQUESTS_L1PMC_EV_E500_STASH_REQUESTS_L2PMC_EV_E500_STALLS_NO_CAQ_OR_COBPMC_EV_E500_L2_CACHE_ACCESSESPMC_EV_E500_L2_HIT_CACHE_ACCESSESPMC_EV_E500_L2_CACHE_DATA_ACCESSESPMC_EV_E500_L2_CACHE_DATA_HITSPMC_EV_E500_L2_CACHE_INSTR_ACCESSESPMC_EV_E500_L2_CACHE_INSTR_HITSPMC_EV_E500_L2_CACHE_ALLOCATIONSPMC_EV_E500_L2_CACHE_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONSPMC_EV_E500_L2_CACHE_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_LOCKSPMC_EV_E500_L2_CACHE_CASTOUTSPMC_EV_E500_L2_CACHE_DATA_DIRTY_HITSPMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITYPMC_EV_E500_SNOOP_THROTTLING_TURNED_ONPMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONSPMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONSPMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONSPMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHESPMC_EV_E500_IAC1S_DETECTEDPMC_EV_E500_IAC2S_DETECTEDPMC_EV_E500_DAC1S_DTECTEDPMC_EV_E500_DAC2S_DTECTEDPMC_EV_E500_DVT0_DETECTEDPMC_EV_E500_DVT1_DETECTEDPMC_EV_E500_DVT2_DETECTEDPMC_EV_E500_DVT3_DETECTEDPMC_EV_E500_DVT4_DETECTEDPMC_EV_E500_DVT5_DETECTEDPMC_EV_E500_DVT6_DETECTEDPMC_EV_E500_DVT7_DETECTEDPMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULLPMC_EV_E500_FPU_DOUBLE_PUMPPMC_EV_E500_FPU_FINISHPMC_EV_E500_FPU_DIVIDE_CYCLESPMC_EV_E500_FPU_DENORM_INPUT_CYCLESPMC_EV_E500_FPU_RESULT_STALL_CYCLESPMC_EV_E500_FPU_FPSCR_FULL_STALLPMC_EV_E500_FPU_PIPE_SYNC_STALLSPMC_EV_E500_FPU_INPUT_DATA_STALLSPMC_EV_E500_DECORATED_LOADSPMC_EV_E500_DECORATED_STORESPMC_EV_E500_LOAD_RETRIESPMC_EV_E500_STWCX_SUCCESSESPMC_EV_E500_STWCX_FAILURESPMC_EV_ARMV7__BLOCK_STARTPMC_EV_ARMV7_EVENT_00HPMC_EV_ARMV7_EVENT_01HPMC_EV_ARMV7_EVENT_02HPMC_EV_ARMV7_EVENT_03HPMC_EV_ARMV7_EVENT_04HPMC_EV_ARMV7_EVENT_05HPMC_EV_ARMV7_EVENT_06HPMC_EV_ARMV7_EVENT_07HPMC_EV_ARMV7_EVENT_08HPMC_EV_ARMV7_EVENT_09HPMC_EV_ARMV7_EVENT_0AHPMC_EV_ARMV7_EVENT_0BHPMC_EV_ARMV7_EVENT_0CHPMC_EV_ARMV7_EVENT_0DHPMC_EV_ARMV7_EVENT_0EHPMC_EV_ARMV7_EVENT_0FHPMC_EV_ARMV7_EVENT_10HPMC_EV_ARMV7_EVENT_11HPMC_EV_ARMV7_EVENT_12HPMC_EV_ARMV7_EVENT_13HPMC_EV_ARMV7_EVENT_14HPMC_EV_ARMV7_EVENT_15HPMC_EV_ARMV7_EVENT_16HPMC_EV_ARMV7_EVENT_17HPMC_EV_ARMV7_EVENT_18HPMC_EV_ARMV7_EVENT_19HPMC_EV_ARMV7_EVENT_1AHPMC_EV_ARMV7_EVENT_1BHPMC_EV_ARMV7_EVENT_1CHPMC_EV_ARMV7_EVENT_1DHPMC_EV_ARMV7_EVENT_1EHPMC_EV_ARMV7_EVENT_1FHPMC_EV_ARMV7_EVENT_20HPMC_EV_ARMV7_EVENT_21HPMC_EV_ARMV7_EVENT_22HPMC_EV_ARMV7_EVENT_23HPMC_EV_ARMV7_EVENT_24HPMC_EV_ARMV7_EVENT_25HPMC_EV_ARMV7_EVENT_26HPMC_EV_ARMV7_EVENT_27HPMC_EV_ARMV7_EVENT_28HPMC_EV_ARMV7_EVENT_29HPMC_EV_ARMV7_EVENT_2AHPMC_EV_ARMV7_EVENT_2BHPMC_EV_ARMV7_EVENT_2CHPMC_EV_ARMV7_EVENT_2DHPMC_EV_ARMV7_EVENT_2EHPMC_EV_ARMV7_EVENT_2FHPMC_EV_ARMV7_EVENT_30HPMC_EV_ARMV7_EVENT_31HPMC_EV_ARMV7_EVENT_32HPMC_EV_ARMV7_EVENT_33HPMC_EV_ARMV7_EVENT_34HPMC_EV_ARMV7_EVENT_35HPMC_EV_ARMV7_EVENT_36HPMC_EV_ARMV7_EVENT_37HPMC_EV_ARMV7_EVENT_38HPMC_EV_ARMV7_EVENT_39HPMC_EV_ARMV7_EVENT_3AHPMC_EV_ARMV7_EVENT_3BHPMC_EV_ARMV7_EVENT_3CHPMC_EV_ARMV7_EVENT_3DHPMC_EV_ARMV7_EVENT_3EHPMC_EV_ARMV7_EVENT_3FHPMC_EV_ARMV7_EVENT_40HPMC_EV_ARMV7_EVENT_41HPMC_EV_ARMV7_EVENT_42HPMC_EV_ARMV7_EVENT_43HPMC_EV_ARMV7_EVENT_44HPMC_EV_ARMV7_EVENT_45HPMC_EV_ARMV7_EVENT_46HPMC_EV_ARMV7_EVENT_47HPMC_EV_ARMV7_EVENT_48HPMC_EV_ARMV7_EVENT_49HPMC_EV_ARMV7_EVENT_4AHPMC_EV_ARMV7_EVENT_4BHPMC_EV_ARMV7_EVENT_4CHPMC_EV_ARMV7_EVENT_4DHPMC_EV_ARMV7_EVENT_4EHPMC_EV_ARMV7_EVENT_4FHPMC_EV_ARMV7_EVENT_50HPMC_EV_ARMV7_EVENT_51HPMC_EV_ARMV7_EVENT_52HPMC_EV_ARMV7_EVENT_53HPMC_EV_ARMV7_EVENT_54HPMC_EV_ARMV7_EVENT_55HPMC_EV_ARMV7_EVENT_56HPMC_EV_ARMV7_EVENT_57HPMC_EV_ARMV7_EVENT_58HPMC_EV_ARMV7_EVENT_59HPMC_EV_ARMV7_EVENT_5AHPMC_EV_ARMV7_EVENT_5BHPMC_EV_ARMV7_EVENT_5CHPMC_EV_ARMV7_EVENT_5DHPMC_EV_ARMV7_EVENT_5EHPMC_EV_ARMV7_EVENT_5FHPMC_EV_ARMV7_EVENT_60HPMC_EV_ARMV7_EVENT_61HPMC_EV_ARMV7_EVENT_62HPMC_EV_ARMV7_EVENT_63HPMC_EV_ARMV7_EVENT_64HPMC_EV_ARMV7_EVENT_65HPMC_EV_ARMV7_EVENT_66HPMC_EV_ARMV7_EVENT_67HPMC_EV_ARMV7_EVENT_68HPMC_EV_ARMV7_EVENT_69HPMC_EV_ARMV7_EVENT_6AHPMC_EV_ARMV7_EVENT_6BHPMC_EV_ARMV7_EVENT_6CHPMC_EV_ARMV7_EVENT_6DHPMC_EV_ARMV7_EVENT_6EHPMC_EV_ARMV7_EVENT_6FHPMC_EV_ARMV7_EVENT_70HPMC_EV_ARMV7_EVENT_71HPMC_EV_ARMV7_EVENT_72HPMC_EV_ARMV7_EVENT_73HPMC_EV_ARMV7_EVENT_74HPMC_EV_ARMV7_EVENT_75HPMC_EV_ARMV7_EVENT_76HPMC_EV_ARMV7_EVENT_77HPMC_EV_ARMV7_EVENT_78HPMC_EV_ARMV7_EVENT_79HPMC_EV_ARMV7_EVENT_7AHPMC_EV_ARMV7_EVENT_7BHPMC_EV_ARMV7_EVENT_7CHPMC_EV_ARMV7_EVENT_7DHPMC_EV_ARMV7_EVENT_7EHPMC_EV_ARMV7_EVENT_7FHPMC_EV_ARMV7_EVENT_80HPMC_EV_ARMV7_EVENT_81HPMC_EV_ARMV7_EVENT_82HPMC_EV_ARMV7_EVENT_83HPMC_EV_ARMV7_EVENT_84HPMC_EV_ARMV7_EVENT_85HPMC_EV_ARMV7_EVENT_86HPMC_EV_ARMV7_EVENT_87HPMC_EV_ARMV7_EVENT_88HPMC_EV_ARMV7_EVENT_89HPMC_EV_ARMV7_EVENT_8AHPMC_EV_ARMV7_EVENT_8BHPMC_EV_ARMV7_EVENT_8CHPMC_EV_ARMV7_EVENT_8DHPMC_EV_ARMV7_EVENT_8EHPMC_EV_ARMV7_EVENT_8FHPMC_EV_ARMV7_EVENT_90HPMC_EV_ARMV7_EVENT_91HPMC_EV_ARMV7_EVENT_92HPMC_EV_ARMV7_EVENT_93HPMC_EV_ARMV7_EVENT_94HPMC_EV_ARMV7_EVENT_95HPMC_EV_ARMV7_EVENT_96HPMC_EV_ARMV7_EVENT_97HPMC_EV_ARMV7_EVENT_98HPMC_EV_ARMV7_EVENT_99HPMC_EV_ARMV7_EVENT_9AHPMC_EV_ARMV7_EVENT_9BHPMC_EV_ARMV7_EVENT_9CHPMC_EV_ARMV7_EVENT_9DHPMC_EV_ARMV7_EVENT_9EHPMC_EV_ARMV7_EVENT_9FHPMC_EV_ARMV7_EVENT_A0HPMC_EV_ARMV7_EVENT_A1HPMC_EV_ARMV7_EVENT_A2HPMC_EV_ARMV7_EVENT_A3HPMC_EV_ARMV7_EVENT_A4HPMC_EV_ARMV7_EVENT_A5HPMC_EV_ARMV7_EVENT_A6HPMC_EV_ARMV7_EVENT_A7HPMC_EV_ARMV7_EVENT_A8HPMC_EV_ARMV7_EVENT_A9HPMC_EV_ARMV7_EVENT_AAHPMC_EV_ARMV7_EVENT_ABHPMC_EV_ARMV7_EVENT_ACHPMC_EV_ARMV7_EVENT_ADHPMC_EV_ARMV7_EVENT_AEHPMC_EV_ARMV7_EVENT_AFHPMC_EV_ARMV7_EVENT_B0HPMC_EV_ARMV7_EVENT_B1HPMC_EV_ARMV7_EVENT_B2HPMC_EV_ARMV7_EVENT_B3HPMC_EV_ARMV7_EVENT_B4HPMC_EV_ARMV7_EVENT_B5HPMC_EV_ARMV7_EVENT_B6HPMC_EV_ARMV7_EVENT_B7HPMC_EV_ARMV7_EVENT_B8HPMC_EV_ARMV7_EVENT_B9HPMC_EV_ARMV7_EVENT_BAHPMC_EV_ARMV7_EVENT_BBHPMC_EV_ARMV7_EVENT_BCHPMC_EV_ARMV7_EVENT_BDHPMC_EV_ARMV7_EVENT_BEHPMC_EV_ARMV7_EVENT_BFHPMC_EV_ARMV7_EVENT_C0HPMC_EV_ARMV7_EVENT_C1HPMC_EV_ARMV7_EVENT_C2HPMC_EV_ARMV7_EVENT_C3HPMC_EV_ARMV7_EVENT_C4HPMC_EV_ARMV7_EVENT_C5HPMC_EV_ARMV7_EVENT_C6HPMC_EV_ARMV7_EVENT_C7HPMC_EV_ARMV7_EVENT_C8HPMC_EV_ARMV7_EVENT_C9HPMC_EV_ARMV7_EVENT_CAHPMC_EV_ARMV7_EVENT_CBHPMC_EV_ARMV7_EVENT_CCHPMC_EV_ARMV7_EVENT_CDHPMC_EV_ARMV7_EVENT_CEHPMC_EV_ARMV7_EVENT_CFHPMC_EV_ARMV7_EVENT_D0HPMC_EV_ARMV7_EVENT_D1HPMC_EV_ARMV7_EVENT_D2HPMC_EV_ARMV7_EVENT_D3HPMC_EV_ARMV7_EVENT_D4HPMC_EV_ARMV7_EVENT_D5HPMC_EV_ARMV7_EVENT_D6HPMC_EV_ARMV7_EVENT_D7HPMC_EV_ARMV7_EVENT_D8HPMC_EV_ARMV7_EVENT_D9HPMC_EV_ARMV7_EVENT_DAHPMC_EV_ARMV7_EVENT_DBHPMC_EV_ARMV7_EVENT_DCHPMC_EV_ARMV7_EVENT_DDHPMC_EV_ARMV7_EVENT_DEHPMC_EV_ARMV7_EVENT_DFHPMC_EV_ARMV7_EVENT_E0HPMC_EV_ARMV7_EVENT_E1HPMC_EV_ARMV7_EVENT_E2HPMC_EV_ARMV7_EVENT_E3HPMC_EV_ARMV7_EVENT_E4HPMC_EV_ARMV7_EVENT_E5HPMC_EV_ARMV7_EVENT_E6HPMC_EV_ARMV7_EVENT_E7HPMC_EV_ARMV7_EVENT_E8HPMC_EV_ARMV7_EVENT_E9HPMC_EV_ARMV7_EVENT_EAHPMC_EV_ARMV7_EVENT_EBHPMC_EV_ARMV7_EVENT_ECHPMC_EV_ARMV7_EVENT_EDHPMC_EV_ARMV7_EVENT_EEHPMC_EV_ARMV7_EVENT_EFHPMC_EV_ARMV7_EVENT_F0HPMC_EV_ARMV7_EVENT_F1HPMC_EV_ARMV7_EVENT_F2HPMC_EV_ARMV7_EVENT_F3HPMC_EV_ARMV7_EVENT_F4HPMC_EV_ARMV7_EVENT_F5HPMC_EV_ARMV7_EVENT_F6HPMC_EV_ARMV7_EVENT_F7HPMC_EV_ARMV7_EVENT_F8HPMC_EV_ARMV7_EVENT_F9HPMC_EV_ARMV7_EVENT_FAHPMC_EV_ARMV7_EVENT_FBHPMC_EV_ARMV7_EVENT_FCHPMC_EV_ARMV7_EVENT_FDHPMC_EV_ARMV7_EVENT_FEHPMC_EV_ARMV7_EVENT_FFHPMC_EV_ARMV8__BLOCK_STARTPMC_EV_ARMV8_EVENT_00HPMC_EV_ARMV8_EVENT_01HPMC_EV_ARMV8_EVENT_02HPMC_EV_ARMV8_EVENT_03HPMC_EV_ARMV8_EVENT_04HPMC_EV_ARMV8_EVENT_05HPMC_EV_ARMV8_EVENT_06HPMC_EV_ARMV8_EVENT_07HPMC_EV_ARMV8_EVENT_08HPMC_EV_ARMV8_EVENT_09HPMC_EV_ARMV8_EVENT_0AHPMC_EV_ARMV8_EVENT_0BHPMC_EV_ARMV8_EVENT_0CHPMC_EV_ARMV8_EVENT_0DHPMC_EV_ARMV8_EVENT_0EHPMC_EV_ARMV8_EVENT_0FHPMC_EV_ARMV8_EVENT_10HPMC_EV_ARMV8_EVENT_11HPMC_EV_ARMV8_EVENT_12HPMC_EV_ARMV8_EVENT_13HPMC_EV_ARMV8_EVENT_14HPMC_EV_ARMV8_EVENT_15HPMC_EV_ARMV8_EVENT_16HPMC_EV_ARMV8_EVENT_17HPMC_EV_ARMV8_EVENT_18HPMC_EV_ARMV8_EVENT_19HPMC_EV_ARMV8_EVENT_1AHPMC_EV_ARMV8_EVENT_1BHPMC_EV_ARMV8_EVENT_1CHPMC_EV_ARMV8_EVENT_1DHPMC_EV_ARMV8_EVENT_1EHPMC_EV_ARMV8_EVENT_1FHPMC_EV_ARMV8_EVENT_20HPMC_EV_ARMV8_EVENT_21HPMC_EV_ARMV8_EVENT_22HPMC_EV_ARMV8_EVENT_23HPMC_EV_ARMV8_EVENT_24HPMC_EV_ARMV8_EVENT_25HPMC_EV_ARMV8_EVENT_26HPMC_EV_ARMV8_EVENT_27HPMC_EV_ARMV8_EVENT_28HPMC_EV_ARMV8_EVENT_29HPMC_EV_ARMV8_EVENT_2AHPMC_EV_ARMV8_EVENT_2BHPMC_EV_ARMV8_EVENT_2CHPMC_EV_ARMV8_EVENT_2DHPMC_EV_ARMV8_EVENT_2EHPMC_EV_ARMV8_EVENT_2FHPMC_EV_ARMV8_EVENT_30HPMC_EV_ARMV8_EVENT_31HPMC_EV_ARMV8_EVENT_32HPMC_EV_ARMV8_EVENT_33HPMC_EV_ARMV8_EVENT_34HPMC_EV_ARMV8_EVENT_35HPMC_EV_ARMV8_EVENT_36HPMC_EV_ARMV8_EVENT_37HPMC_EV_ARMV8_EVENT_38HPMC_EV_ARMV8_EVENT_39HPMC_EV_ARMV8_EVENT_3AHPMC_EV_ARMV8_EVENT_3BHPMC_EV_ARMV8_EVENT_3CHPMC_EV_ARMV8_EVENT_3DHPMC_EV_ARMV8_EVENT_3EHPMC_EV_ARMV8_EVENT_3FHPMC_EV_ARMV8_EVENT_40HPMC_EV_ARMV8_EVENT_41HPMC_EV_ARMV8_EVENT_42HPMC_EV_ARMV8_EVENT_43HPMC_EV_ARMV8_EVENT_44HPMC_EV_ARMV8_EVENT_45HPMC_EV_ARMV8_EVENT_46HPMC_EV_ARMV8_EVENT_47HPMC_EV_ARMV8_EVENT_48HPMC_EV_ARMV8_EVENT_49HPMC_EV_ARMV8_EVENT_4AHPMC_EV_ARMV8_EVENT_4BHPMC_EV_ARMV8_EVENT_4CHPMC_EV_ARMV8_EVENT_4DHPMC_EV_ARMV8_EVENT_4EHPMC_EV_ARMV8_EVENT_4FHPMC_EV_ARMV8_EVENT_50HPMC_EV_ARMV8_EVENT_51HPMC_EV_ARMV8_EVENT_52HPMC_EV_ARMV8_EVENT_53HPMC_EV_ARMV8_EVENT_54HPMC_EV_ARMV8_EVENT_55HPMC_EV_ARMV8_EVENT_56HPMC_EV_ARMV8_EVENT_57HPMC_EV_ARMV8_EVENT_58HPMC_EV_ARMV8_EVENT_59HPMC_EV_ARMV8_EVENT_5AHPMC_EV_ARMV8_EVENT_5BHPMC_EV_ARMV8_EVENT_5CHPMC_EV_ARMV8_EVENT_5DHPMC_EV_ARMV8_EVENT_5EHPMC_EV_ARMV8_EVENT_5FHPMC_EV_ARMV8_EVENT_60HPMC_EV_ARMV8_EVENT_61HPMC_EV_ARMV8_EVENT_62HPMC_EV_ARMV8_EVENT_63HPMC_EV_ARMV8_EVENT_64HPMC_EV_ARMV8_EVENT_65HPMC_EV_ARMV8_EVENT_66HPMC_EV_ARMV8_EVENT_67HPMC_EV_ARMV8_EVENT_68HPMC_EV_ARMV8_EVENT_69HPMC_EV_ARMV8_EVENT_6AHPMC_EV_ARMV8_EVENT_6BHPMC_EV_ARMV8_EVENT_6CHPMC_EV_ARMV8_EVENT_6DHPMC_EV_ARMV8_EVENT_6EHPMC_EV_ARMV8_EVENT_6FHPMC_EV_ARMV8_EVENT_70HPMC_EV_ARMV8_EVENT_71HPMC_EV_ARMV8_EVENT_72HPMC_EV_ARMV8_EVENT_73HPMC_EV_ARMV8_EVENT_74HPMC_EV_ARMV8_EVENT_75HPMC_EV_ARMV8_EVENT_76HPMC_EV_ARMV8_EVENT_77HPMC_EV_ARMV8_EVENT_78HPMC_EV_ARMV8_EVENT_79HPMC_EV_ARMV8_EVENT_7AHPMC_EV_ARMV8_EVENT_7BHPMC_EV_ARMV8_EVENT_7CHPMC_EV_ARMV8_EVENT_7DHPMC_EV_ARMV8_EVENT_7EHPMC_EV_ARMV8_EVENT_7FHPMC_EV_ARMV8_EVENT_80HPMC_EV_ARMV8_EVENT_81HPMC_EV_ARMV8_EVENT_82HPMC_EV_ARMV8_EVENT_83HPMC_EV_ARMV8_EVENT_84HPMC_EV_ARMV8_EVENT_85HPMC_EV_ARMV8_EVENT_86HPMC_EV_ARMV8_EVENT_87HPMC_EV_ARMV8_EVENT_88HPMC_EV_ARMV8_EVENT_89HPMC_EV_ARMV8_EVENT_8AHPMC_EV_ARMV8_EVENT_8BHPMC_EV_ARMV8_EVENT_8CHPMC_EV_ARMV8_EVENT_8DHPMC_EV_ARMV8_EVENT_8EHPMC_EV_ARMV8_EVENT_8FHPMC_EV_ARMV8_EVENT_90HPMC_EV_ARMV8_EVENT_91HPMC_EV_ARMV8_EVENT_92HPMC_EV_ARMV8_EVENT_93HPMC_EV_ARMV8_EVENT_94HPMC_EV_ARMV8_EVENT_95HPMC_EV_ARMV8_EVENT_96HPMC_EV_ARMV8_EVENT_97HPMC_EV_ARMV8_EVENT_98HPMC_EV_ARMV8_EVENT_99HPMC_EV_ARMV8_EVENT_9AHPMC_EV_ARMV8_EVENT_9BHPMC_EV_ARMV8_EVENT_9CHPMC_EV_ARMV8_EVENT_9DHPMC_EV_ARMV8_EVENT_9EHPMC_EV_ARMV8_EVENT_9FHPMC_EV_ARMV8_EVENT_A0HPMC_EV_ARMV8_EVENT_A1HPMC_EV_ARMV8_EVENT_A2HPMC_EV_ARMV8_EVENT_A3HPMC_EV_ARMV8_EVENT_A4HPMC_EV_ARMV8_EVENT_A5HPMC_EV_ARMV8_EVENT_A6HPMC_EV_ARMV8_EVENT_A7HPMC_EV_ARMV8_EVENT_A8HPMC_EV_ARMV8_EVENT_A9HPMC_EV_ARMV8_EVENT_AAHPMC_EV_ARMV8_EVENT_ABHPMC_EV_ARMV8_EVENT_ACHPMC_EV_ARMV8_EVENT_ADHPMC_EV_ARMV8_EVENT_AEHPMC_EV_ARMV8_EVENT_AFHPMC_EV_ARMV8_EVENT_B0HPMC_EV_ARMV8_EVENT_B1HPMC_EV_ARMV8_EVENT_B2HPMC_EV_ARMV8_EVENT_B3HPMC_EV_ARMV8_EVENT_B4HPMC_EV_ARMV8_EVENT_B5HPMC_EV_ARMV8_EVENT_B6HPMC_EV_ARMV8_EVENT_B7HPMC_EV_ARMV8_EVENT_B8HPMC_EV_ARMV8_EVENT_B9HPMC_EV_ARMV8_EVENT_BAHPMC_EV_ARMV8_EVENT_BBHPMC_EV_ARMV8_EVENT_BCHPMC_EV_ARMV8_EVENT_BDHPMC_EV_ARMV8_EVENT_BEHPMC_EV_ARMV8_EVENT_BFHPMC_EV_ARMV8_EVENT_C0HPMC_EV_ARMV8_EVENT_C1HPMC_EV_ARMV8_EVENT_C2HPMC_EV_ARMV8_EVENT_C3HPMC_EV_ARMV8_EVENT_C4HPMC_EV_ARMV8_EVENT_C5HPMC_EV_ARMV8_EVENT_C6HPMC_EV_ARMV8_EVENT_C7HPMC_EV_ARMV8_EVENT_C8HPMC_EV_ARMV8_EVENT_C9HPMC_EV_ARMV8_EVENT_CAHPMC_EV_ARMV8_EVENT_CBHPMC_EV_ARMV8_EVENT_CCHPMC_EV_ARMV8_EVENT_CDHPMC_EV_ARMV8_EVENT_CEHPMC_EV_ARMV8_EVENT_CFHPMC_EV_ARMV8_EVENT_D0HPMC_EV_ARMV8_EVENT_D1HPMC_EV_ARMV8_EVENT_D2HPMC_EV_ARMV8_EVENT_D3HPMC_EV_ARMV8_EVENT_D4HPMC_EV_ARMV8_EVENT_D5HPMC_EV_ARMV8_EVENT_D6HPMC_EV_ARMV8_EVENT_D7HPMC_EV_ARMV8_EVENT_D8HPMC_EV_ARMV8_EVENT_D9HPMC_EV_ARMV8_EVENT_DAHPMC_EV_ARMV8_EVENT_DBHPMC_EV_ARMV8_EVENT_DCHPMC_EV_ARMV8_EVENT_DDHPMC_EV_ARMV8_EVENT_DEHPMC_EV_ARMV8_EVENT_DFHPMC_EV_ARMV8_EVENT_E0HPMC_EV_ARMV8_EVENT_E1HPMC_EV_ARMV8_EVENT_E2HPMC_EV_ARMV8_EVENT_E3HPMC_EV_ARMV8_EVENT_E4HPMC_EV_ARMV8_EVENT_E5HPMC_EV_ARMV8_EVENT_E6HPMC_EV_ARMV8_EVENT_E7HPMC_EV_ARMV8_EVENT_E8HPMC_EV_ARMV8_EVENT_E9HPMC_EV_ARMV8_EVENT_EAHPMC_EV_ARMV8_EVENT_EBHPMC_EV_ARMV8_EVENT_ECHPMC_EV_ARMV8_EVENT_EDHPMC_EV_ARMV8_EVENT_EEHPMC_EV_ARMV8_EVENT_EFHPMC_EV_ARMV8_EVENT_F0HPMC_EV_ARMV8_EVENT_F1HPMC_EV_ARMV8_EVENT_F2HPMC_EV_ARMV8_EVENT_F3HPMC_EV_ARMV8_EVENT_F4HPMC_EV_ARMV8_EVENT_F5HPMC_EV_ARMV8_EVENT_F6HPMC_EV_ARMV8_EVENT_F7HPMC_EV_ARMV8_EVENT_F8HPMC_EV_ARMV8_EVENT_F9HPMC_EV_ARMV8_EVENT_FAHPMC_EV_ARMV8_EVENT_FBHPMC_EV_ARMV8_EVENT_FCHPMC_EV_ARMV8_EVENT_FDHPMC_EV_ARMV8_EVENT_FEHPMC_EV_ARMV8_EVENT_FFHpmc_eventps_stateps_archps_version__uint32_tuint32_tps_initializedintps_countps_offsetlong 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tmp/usr/include/unistd.hsrc/lib/libpmc/pmc.h
src/lib/libpmc/libpmcinternal.h
tmp/usr/include/stdlib.h
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?W����FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe)/usr/src/lib/libpmc/libpmc_pmu_util.c/usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmcpmu_amd_alias_tablepa_aliascharpa_namepmu_alias__ARRAY_SIZE_TYPE__pmu_intel_alias_tablestat_mode_cntrsunsigned intPMC_CLASS_TSCPMC_CLASS_K7PMC_CLASS_K8PMC_CLASS_P5PMC_CLASS_P6PMC_CLASS_P4PMC_CLASS_IAFPMC_CLASS_IAPPMC_CLASS_UCFPMC_CLASS_UCPPMC_CLASS_XSCALEPMC_CLASS_MIPS24KPMC_CLASS_OCTEONPMC_CLASS_PPC7450PMC_CLASS_PPC970PMC_CLASS_SOFTPMC_CLASS_ARMV7PMC_CLASS_ARMV8PMC_CLASS_MIPS74KPMC_CLASS_E500PMC_CLASS_BERIPMC_CLASS_POWER8pmc_classPMC_EV_TSC__BLOCK_STARTPMC_EV_TSC_TSCPMC_EV_IAF__BLOCK_STARTPMC_EV_IAF_INSTR_RETIRED_ANYPMC_EV_IAF_CPU_CLK_UNHALTED_COREPMC_EV_IAF_CPU_CLK_UNHALTED_REFPMC_EV_K7__BLOCK_STARTPMC_EV_K7_DC_ACCESSESPMC_EV_K7_DC_MISSESPMC_EV_K7_DC_REFILLS_FROM_L2PMC_EV_K7_DC_REFILLS_FROM_SYSTEMPMC_EV_K7_DC_WRITEBACKSPMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITSPMC_EV_K7_L1_AND_L2_DTLB_MISSESPMC_EV_K7_MISALIGNED_REFERENCESPMC_EV_K7_IC_FETCHESPMC_EV_K7_IC_MISSESPMC_EV_K7_L1_ITLB_MISSESPMC_EV_K7_L1_L2_ITLB_MISSESPMC_EV_K7_RETIRED_INSTRUCTIONSPMC_EV_K7_RETIRED_OPSPMC_EV_K7_RETIRED_BRANCHESPMC_EV_K7_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_TAKEN_BRANCHESPMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K7_RETIRED_RESYNC_BRANCHESPMC_EV_K7_INTERRUPTS_MASKED_CYCLESPMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K7_HARDWARE_INTERRUPTSPMC_EV_K8__BLOCK_STARTPMC_EV_K8_FP_DISPATCHED_FPU_OPSPMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIREDPMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPSPMC_EV_K8_LS_SEGMENT_REGISTER_LOADPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODEPMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_LS_BUFFER2_FULLPMC_EV_K8_LS_LOCKED_OPERATIONPMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONSPMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONSPMC_EV_K8_DC_ACCESSPMC_EV_K8_DC_MISSPMC_EV_K8_DC_REFILL_FROM_L2PMC_EV_K8_DC_REFILL_FROM_SYSTEMPMC_EV_K8_DC_COPYBACKPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HITPMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISSPMC_EV_K8_DC_MISALIGNED_DATA_REFERENCEPMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCELPMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCELPMC_EV_K8_DC_ONE_BIT_ECC_ERRORPMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONSPMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKSPMC_EV_K8_BU_CPU_CLK_UNHALTEDPMC_EV_K8_BU_INTERNAL_L2_REQUESTPMC_EV_K8_BU_FILL_REQUEST_L2_MISSPMC_EV_K8_BU_FILL_INTO_L2PMC_EV_K8_IC_FETCHPMC_EV_K8_IC_MISSPMC_EV_K8_IC_REFILL_FROM_L2PMC_EV_K8_IC_REFILL_FROM_SYSTEMPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HITPMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISSPMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOPPMC_EV_K8_IC_INSTRUCTION_FETCH_STALLPMC_EV_K8_IC_RETURN_STACK_HITPMC_EV_K8_IC_RETURN_STACK_OVERFLOWPMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_UOPSPMC_EV_K8_FR_RETIRED_BRANCHESPMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHESPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTEDPMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERSPMC_EV_K8_FR_RETIRED_RESYNCSPMC_EV_K8_FR_RETIRED_NEAR_RETURNSPMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTEDPMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPAREPMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONSPMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSPMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLESPMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESPMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTSPMC_EV_K8_FR_DECODER_EMPTYPMC_EV_K8_FR_DISPATCH_STALLSPMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIREPMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATIONPMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOADPMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULLPMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIETPMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDINGPMC_EV_K8_FR_FPU_EXCEPTIONSPMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENTPMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWPMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDPMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUNDPMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATIONPMC_EV_K8_NB_SIZED_COMMANDSPMC_EV_K8_NB_PROBE_RESULTPMC_EV_K8_NB_HT_BUS0_BANDWIDTHPMC_EV_K8_NB_HT_BUS1_BANDWIDTHPMC_EV_K8_NB_HT_BUS2_BANDWIDTHPMC_EV_MIPS24K__BLOCK_STARTPMC_EV_MIPS24K_CYCLEPMC_EV_MIPS24K_INSTR_EXECUTEDPMC_EV_MIPS24K_BRANCH_COMPLETEDPMC_EV_MIPS24K_BRANCH_MISPREDPMC_EV_MIPS24K_RETURNPMC_EV_MIPS24K_RETURN_MISPREDPMC_EV_MIPS24K_RETURN_NOT_31PMC_EV_MIPS24K_RETURN_NOTPREDPMC_EV_MIPS24K_ITLB_ACCESSPMC_EV_MIPS24K_ITLB_MISSPMC_EV_MIPS24K_DTLB_ACCESSPMC_EV_MIPS24K_DTLB_MISSPMC_EV_MIPS24K_JTLB_IACCESSPMC_EV_MIPS24K_JTLB_IMISSPMC_EV_MIPS24K_JTLB_DACCESSPMC_EV_MIPS24K_JTLB_DMISSPMC_EV_MIPS24K_IC_FETCHPMC_EV_MIPS24K_IC_MISSPMC_EV_MIPS24K_DC_LOADSTOREPMC_EV_MIPS24K_DC_WRITEBACKPMC_EV_MIPS24K_DC_MISSPMC_EV_MIPS24K_STORE_MISSPMC_EV_MIPS24K_LOAD_MISSPMC_EV_MIPS24K_INTEGER_COMPLETEDPMC_EV_MIPS24K_FP_COMPLETEDPMC_EV_MIPS24K_LOAD_COMPLETEDPMC_EV_MIPS24K_STORE_COMPLETEDPMC_EV_MIPS24K_BARRIER_COMPLETEDPMC_EV_MIPS24K_MIPS16_COMPLETEDPMC_EV_MIPS24K_NOP_COMPLETEDPMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETEDPMC_EV_MIPS24K_RF_STALLPMC_EV_MIPS24K_INSTR_REFETCHPMC_EV_MIPS24K_STORE_COND_COMPLETEDPMC_EV_MIPS24K_STORE_COND_FAILEDPMC_EV_MIPS24K_ICACHE_REQUESTSPMC_EV_MIPS24K_ICACHE_HITPMC_EV_MIPS24K_L2_WRITEBACKPMC_EV_MIPS24K_L2_ACCESSPMC_EV_MIPS24K_L2_MISSPMC_EV_MIPS24K_L2_ERR_CORRECTEDPMC_EV_MIPS24K_EXCEPTIONSPMC_EV_MIPS24K_RF_CYCLES_STALLEDPMC_EV_MIPS24K_IFU_CYCLES_STALLEDPMC_EV_MIPS24K_ALU_CYCLES_STALLEDPMC_EV_MIPS24K_UNCACHED_LOADPMC_EV_MIPS24K_UNCACHED_STOREPMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETEDPMC_EV_MIPS24K_MFTC_COMPLETEDPMC_EV_MIPS24K_IC_BLOCKED_CYCLESPMC_EV_MIPS24K_DC_BLOCKED_CYCLESPMC_EV_MIPS24K_L2_IMISS_STALL_CYCLESPMC_EV_MIPS24K_L2_DMISS_STALL_CYCLESPMC_EV_MIPS24K_DMISS_CYCLESPMC_EV_MIPS24K_L2_MISS_CYCLESPMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLESPMC_EV_MIPS24K_MDU_STALL_CYCLESPMC_EV_MIPS24K_FPU_STALL_CYCLESPMC_EV_MIPS24K_CP2_STALL_CYCLESPMC_EV_MIPS24K_COREXTEND_STALL_CYCLESPMC_EV_MIPS24K_ISPRAM_STALL_CYCLESPMC_EV_MIPS24K_DSPRAM_STALL_CYCLESPMC_EV_MIPS24K_CACHE_STALL_CYCLESPMC_EV_MIPS24K_LOAD_TO_USE_STALLSPMC_EV_MIPS24K_BASE_MISPRED_STALLSPMC_EV_MIPS24K_CPO_READ_STALLSPMC_EV_MIPS24K_BRANCH_MISPRED_CYCLESPMC_EV_MIPS24K_IFETCH_BUFFER_FULLPMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATEDPMC_EV_MIPS24K_EJTAG_ITRIGGERPMC_EV_MIPS24K_EJTAG_DTRIGGERPMC_EV_MIPS24K_FSB_LT_QUARTERPMC_EV_MIPS24K_FSB_QUARTER_TO_HALFPMC_EV_MIPS24K_FSB_GT_HALFPMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_LDQ_LT_QUARTERPMC_EV_MIPS24K_LDQ_QUARTER_TO_HALFPMC_EV_MIPS24K_LDQ_GT_HALFPMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_WBB_LT_QUARTERPMC_EV_MIPS24K_WBB_QUARTER_TO_HALFPMC_EV_MIPS24K_WBB_GT_HALFPMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLSPMC_EV_MIPS24K_REQUEST_LATENCYPMC_EV_MIPS24K_REQUEST_COUNTPMC_EV_OCTEON__BLOCK_STARTPMC_EV_OCTEON_CLKPMC_EV_OCTEON_ISSUEPMC_EV_OCTEON_RETPMC_EV_OCTEON_NISSUEPMC_EV_OCTEON_SISSUEPMC_EV_OCTEON_DISSUEPMC_EV_OCTEON_IFIPMC_EV_OCTEON_BRPMC_EV_OCTEON_BRMISPMC_EV_OCTEON_JPMC_EV_OCTEON_JMISPMC_EV_OCTEON_REPLAYPMC_EV_OCTEON_IUNAPMC_EV_OCTEON_TRAPPMC_EV_OCTEON_UULOADPMC_EV_OCTEON_UUSTOREPMC_EV_OCTEON_ULOADPMC_EV_OCTEON_USTOREPMC_EV_OCTEON_ECPMC_EV_OCTEON_MCPMC_EV_OCTEON_CCPMC_EV_OCTEON_CSRCPMC_EV_OCTEON_CFETCHPMC_EV_OCTEON_CPREFPMC_EV_OCTEON_ICAPMC_EV_OCTEON_IIPMC_EV_OCTEON_IPPMC_EV_OCTEON_CIMISSPMC_EV_OCTEON_WBUFPMC_EV_OCTEON_WDATPMC_EV_OCTEON_WBUFLDPMC_EV_OCTEON_WBUFFLPMC_EV_OCTEON_WBUFTRPMC_EV_OCTEON_BADDPMC_EV_OCTEON_BADDL2PMC_EV_OCTEON_BFILLPMC_EV_OCTEON_DDIDSPMC_EV_OCTEON_IDIDSPMC_EV_OCTEON_DIDNAPMC_EV_OCTEON_LDSPMC_EV_OCTEON_LMLDSPMC_EV_OCTEON_IOLDSPMC_EV_OCTEON_DMLDSPMC_EV_OCTEON_STSPMC_EV_OCTEON_LMSTSPMC_EV_OCTEON_IOSTSPMC_EV_OCTEON_IOBDMAPMC_EV_OCTEON_DTLBPMC_EV_OCTEON_DTLBADPMC_EV_OCTEON_ITLBPMC_EV_OCTEON_SYNCPMC_EV_OCTEON_SYNCIOBPMC_EV_OCTEON_SYNCWPMC_EV_MIPS74K__BLOCK_STARTPMC_EV_MIPS74K_CYCLESPMC_EV_MIPS74K_INSTR_EXECUTEDPMC_EV_MIPS74K_PREDICTED_JR_31PMC_EV_MIPS74K_JR_31_MISPREDICTIONSPMC_EV_MIPS74K_REDIRECT_STALLSPMC_EV_MIPS74K_JR_31_NO_PREDICTIONSPMC_EV_MIPS74K_ITLB_ACCESSESPMC_EV_MIPS74K_ITLB_MISSESPMC_EV_MIPS74K_JTLB_INSN_MISSESPMC_EV_MIPS74K_ICACHE_ACCESSESPMC_EV_MIPS74K_ICACHE_MISSESPMC_EV_MIPS74K_ICACHE_MISS_STALLSPMC_EV_MIPS74K_UNCACHED_IFETCH_STALLSPMC_EV_MIPS74K_PDTRACE_BACK_STALLSPMC_EV_MIPS74K_IFU_REPLAYSPMC_EV_MIPS74K_KILLED_FETCH_SLOTSPMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLESPMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLESPMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLESPMC_EV_MIPS74K_DDQ0_FULL_DR_STALLSPMC_EV_MIPS74K_DDQ1_FULL_DR_STALLSPMC_EV_MIPS74K_ALCB_FULL_DR_STALLSPMC_EV_MIPS74K_AGCB_FULL_DR_STALLSPMC_EV_MIPS74K_CLDQ_FULL_DR_STALLSPMC_EV_MIPS74K_IODQ_FULL_DR_STALLSPMC_EV_MIPS74K_ALU_EMPTY_CYCLESPMC_EV_MIPS74K_AGEN_EMPTY_CYCLESPMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLESPMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLESPMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLESPMC_EV_MIPS74K_ALU_BUBBLE_CYCLESPMC_EV_MIPS74K_AGEN_BUBBLE_CYCLESPMC_EV_MIPS74K_SINGLE_ISSUE_CYCLESPMC_EV_MIPS74K_DUAL_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLESPMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLESPMC_EV_MIPS74K_JALR_JALR_HB_INSNSPMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTSPMC_EV_MIPS74K_DCACHE_LOAD_ACCESSESPMC_EV_MIPS74K_DCACHE_ACCESSESPMC_EV_MIPS74K_DCACHE_WRITEBACKSPMC_EV_MIPS74K_DCACHE_MISSESPMC_EV_MIPS74K_JTLB_DATA_ACCESSESPMC_EV_MIPS74K_JTLB_DATA_MISSESPMC_EV_MIPS74K_LOAD_STORE_REPLAYSPMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASESPMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLESPMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTSPMC_EV_MIPS74K_L2_CACHE_WRITEBACKSPMC_EV_MIPS74K_L2_CACHE_ACCESSESPMC_EV_MIPS74K_L2_CACHE_MISSESPMC_EV_MIPS74K_L2_CACHE_MISS_CYCLESPMC_EV_MIPS74K_FSB_FULL_STALLSPMC_EV_MIPS74K_FSB_OVER_50_FULLPMC_EV_MIPS74K_LDQ_FULL_STALLSPMC_EV_MIPS74K_LDQ_OVER_50_FULLPMC_EV_MIPS74K_WBB_FULL_STALLSPMC_EV_MIPS74K_WBB_OVER_50_FULLPMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYSPMC_EV_MIPS74K_CP1_CP2_LOAD_INSNSPMC_EV_MIPS74K_JR_NON_31_INSNSPMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNSPMC_EV_MIPS74K_BRANCH_INSNSPMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNSPMC_EV_MIPS74K_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNSPMC_EV_MIPS74K_COND_BRANCH_INSNSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNSPMC_EV_MIPS74K_INTEGER_INSNSPMC_EV_MIPS74K_FPU_INSNSPMC_EV_MIPS74K_LOAD_INSNSPMC_EV_MIPS74K_STORE_INSNSPMC_EV_MIPS74K_J_JAL_INSNSPMC_EV_MIPS74K_MIPS16_INSNSPMC_EV_MIPS74K_NOP_INSNSPMC_EV_MIPS74K_NT_MUL_DIV_INSNSPMC_EV_MIPS74K_DSP_INSNSPMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_DSP_BRANCH_INSNSPMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNSPMC_EV_MIPS74K_UNCACHED_LOAD_INSNSPMC_EV_MIPS74K_UNCACHED_STORE_INSNSPMC_EV_MIPS74K_EJTAG_INSN_TRIGGERSPMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONSPMC_EV_MIPS74K_SC_INSNSPMC_EV_MIPS74K_FAILED_SC_INSNSPMC_EV_MIPS74K_PREFETCH_INSNSPMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNSPMC_EV_MIPS74K_NO_INSN_CYCLESPMC_EV_MIPS74K_LOAD_MISS_INSNSPMC_EV_MIPS74K_ONE_INSN_CYCLESPMC_EV_MIPS74K_TWO_INSNS_CYCLESPMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLESPMC_EV_MIPS74K_CP1_CP2_STORE_INSNSPMC_EV_MIPS74K_MISPREDICTION_STALLSPMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLESPMC_EV_MIPS74K_EXCEPTIONS_TAKENPMC_EV_MIPS74K_GRADUATION_REPLAYSPMC_EV_MIPS74K_COREEXTEND_EVENTSPMC_EV_MIPS74K_ISPRAM_EVENTSPMC_EV_MIPS74K_DSPRAM_EVENTSPMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORSPMC_EV_MIPS74K_SYSTEM_EVENT_0PMC_EV_MIPS74K_SYSTEM_EVENT_1PMC_EV_MIPS74K_SYSTEM_EVENT_2PMC_EV_MIPS74K_SYSTEM_EVENT_3PMC_EV_MIPS74K_SYSTEM_EVENT_4PMC_EV_MIPS74K_SYSTEM_EVENT_5PMC_EV_MIPS74K_SYSTEM_EVENT_6PMC_EV_MIPS74K_SYSTEM_EVENT_7PMC_EV_MIPS74K_OCP_ALL_REQUESTSPMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_READ_REQUESTSPMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_REQUESTSPMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTSPMC_EV_MIPS74K_FSB_LESS_25_FULLPMC_EV_MIPS74K_FSB_25_50_FULLPMC_EV_MIPS74K_LDQ_LESS_25_FULLPMC_EV_MIPS74K_LDQ_25_50_FULLPMC_EV_MIPS74K_WBB_LESS_25_FULLPMC_EV_MIPS74K_WBB_25_50_FULLPMC_EV_BERI__BLOCK_STARTPMC_EV_BERI_CYCLEPMC_EV_BERI_INSTPMC_EV_BERI_INST_USERPMC_EV_BERI_INST_KERNELPMC_EV_BERI_IMPRECISE_SETBOUNDSPMC_EV_BERI_UNREPRESENTABLE_CAPSPMC_EV_BERI_ITLB_MISSPMC_EV_BERI_DTLB_MISSPMC_EV_BERI_ICACHE_WRITE_HITPMC_EV_BERI_ICACHE_WRITE_MISSPMC_EV_BERI_ICACHE_READ_HITPMC_EV_BERI_ICACHE_READ_MISSPMC_EV_BERI_ICACHE_EVICTPMC_EV_BERI_DCACHE_WRITE_HITPMC_EV_BERI_DCACHE_WRITE_MISSPMC_EV_BERI_DCACHE_READ_HITPMC_EV_BERI_DCACHE_READ_MISSPMC_EV_BERI_DCACHE_EVICTPMC_EV_BERI_DCACHE_SET_TAG_WRITEPMC_EV_BERI_DCACHE_SET_TAG_READPMC_EV_BERI_L2CACHE_WRITE_HITPMC_EV_BERI_L2CACHE_WRITE_MISSPMC_EV_BERI_L2CACHE_READ_HITPMC_EV_BERI_L2CACHE_READ_MISSPMC_EV_BERI_L2CACHE_EVICTPMC_EV_BERI_L2CACHE_SET_TAG_WRITEPMC_EV_BERI_L2CACHE_SET_TAG_READPMC_EV_BERI_MEM_BYTE_READPMC_EV_BERI_MEM_BYTE_WRITEPMC_EV_BERI_MEM_HWORD_READPMC_EV_BERI_MEM_HWORD_WRITEPMC_EV_BERI_MEM_WORD_READPMC_EV_BERI_MEM_WORD_WRITEPMC_EV_BERI_MEM_DWORD_READPMC_EV_BERI_MEM_DWORD_WRITEPMC_EV_BERI_MEM_CAP_READPMC_EV_BERI_MEM_CAP_WRITEPMC_EV_BERI_MEM_CAP_READ_TAG_SETPMC_EV_BERI_MEM_CAP_WRITE_TAG_SETPMC_EV_BERI_TAGCACHE_WRITE_HITPMC_EV_BERI_TAGCACHE_WRITE_MISSPMC_EV_BERI_TAGCACHE_READ_HITPMC_EV_BERI_TAGCACHE_READ_MISSPMC_EV_BERI_TAGCACHE_EVICTPMC_EV_BERI_L2CACHEMASTER_READ_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQPMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_L2CACHEMASTER_READ_RSPPMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLITPMC_EV_BERI_L2CACHEMASTER_WRITE_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQPMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLITPMC_EV_BERI_TAGCACHEMASTER_READ_RSPPMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLITPMC_EV_BERI_TAGCACHEMASTER_WRITE_RSPPMC_EV_UCP__BLOCK_STARTPMC_EV_UCP_EVENT_0CH_04H_EPMC_EV_UCP_EVENT_0CH_04H_FPMC_EV_UCP_EVENT_0CH_04H_MPMC_EV_UCP_EVENT_0CH_04H_SPMC_EV_UCP_EVENT_0CH_08H_EPMC_EV_UCP_EVENT_0CH_08H_FPMC_EV_UCP_EVENT_0CH_08H_MPMC_EV_UCP_EVENT_0CH_08H_SPMC_EV_PPC7450__BLOCK_STARTPMC_EV_PPC7450_CYCLEPMC_EV_PPC7450_INSTR_COMPLETEDPMC_EV_PPC7450_TLB_BIT_TRANSITIONSPMC_EV_PPC7450_INSTR_DISPATCHEDPMC_EV_PPC7450_PMON_EXCEPTPMC_EV_PPC7450_PMON_SIGPMC_EV_PPC7450_VPU_INSTR_COMPLETEDPMC_EV_PPC7450_VFPU_INSTR_COMPLETEDPMC_EV_PPC7450_VIU1_INSTR_COMPLETEDPMC_EV_PPC7450_VIU2_INSTR_COMPLETEDPMC_EV_PPC7450_MTVSCR_INSTR_COMPLETEDPMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETEDPMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLESPMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLESPMC_EV_PPC7450_MFVSCR_SYNC_CYCLESPMC_EV_PPC7450_VSCR_SAT_SETPMC_EV_PPC7450_STORE_INSTR_COMPLETEDPMC_EV_PPC7450_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_SNOOPSPMC_EV_PPC7450_UNRESOLVED_BRANCHESPMC_EV_PPC7450_SPEC_BUFFER_CYCLESPMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLESPMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITSPMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHEDPMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLESPMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRSPMC_EV_PPC7450_IU2_INSTR_COMPLETEDPMC_EV_PPC7450_BRANCHES_COMPLETEDPMC_EV_PPC7450_EIEIO_INSTR_COMPLETEDPMC_EV_PPC7450_MTSPR_INSTR_COMPLETEDPMC_EV_PPC7450_SC_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_COMPLETEDPMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSESPMC_EV_PPC7450_INSTR_BKPT_MATCHESPMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIEDPMC_EV_PPC7450_LOAD_MISS_ALIASPMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCHPMC_EV_PPC7450_TOUCH_ALIASPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUEPMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUTPMC_EV_PPC7450_L1_DATA_SNOOP_HITSPMC_EV_PPC7450_WRITE_THROUGH_STORESPMC_EV_PPC7450_CACHE_INHIBITED_STORESPMC_EV_PPC7450_L1_DATA_LOAD_HITPMC_EV_PPC7450_L1_DATA_TOUCH_HITPMC_EV_PPC7450_L1_DATA_STORE_HITPMC_EV_PPC7450_L1_DATA_TOTAL_HITSPMC_EV_PPC7450_DST_INSTR_DISPATCHEDPMC_EV_PPC7450_REFRESHED_DSTSPMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHESPMC_EV_PPC7450_DSS_INSTR_COMPLETEDPMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_HITPMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FPU_RENORMALIZATIONPMC_EV_PPC7450_FPU_DENORMALIZATIONPMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSUPMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALLPMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALLPMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQPMC_EV_PPC7450_LSU_LMQ_FULL_STALLPMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSUPMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSUPMC_EV_PPC7450_LSU_RA_LATCH_STALLPMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALLPMC_EV_PPC7450_LSU_LMQ_INDEX_ALIASPMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIASPMC_EV_PPC7450_LSU_CSQ_FORWARDINGPMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISHPMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETEDPMC_EV_PPC7450_LSU_MISALIGN_STALLPMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSYPMC_EV_PPC7450_FP_DENORMALIZED_RESULTPMC_EV_PPC7450_L1_DATA_TOTAL_MISSESPMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUEPMC_EV_PPC7450_LSU_INSTR_COMPLETEDPMC_EV_PPC7450_LOAD_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_COMPLETEDPMC_EV_PPC7450_TLBIE_INSTR_COMPLETEDPMC_EV_PPC7450_LWARX_INSTR_COMPLETEDPMC_EV_PPC7450_MFSPR_INSTR_COMPLETEDPMC_EV_PPC7450_REFETCH_SERIALIZATIONPMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHEDPMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETEDPMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSESPMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISSPMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISSPMC_EV_PPC7450_L1_DATA_STORE_MISSPMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_CYCLES_USEDPMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHESPMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELYPMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGEPMC_EV_PPC7450_VTQ_LINE_FETCH_MISSPMC_EV_PPC7450_VTQ_LINE_FETCHPMC_EV_PPC7450_TLBIE_SNOOPSPMC_EV_PPC7450_L1_INSTR_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_RELOADSPMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2PMC_EV_PPC7450_STORE_MERGE_GATHERPMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTESPMC_EV_PPC7450_DATA_BKPT_MATCHESPMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSEDPMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCYPMC_EV_PPC7450_BTIC_MISSPMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVEDPMC_EV_PPC7450_FPR_ISSUE_STALLEDPMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USERPMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLEPMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHESPMC_EV_PPC7450_VR_STALLSPMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIESPMC_EV_PPC7450_FPU_INSTR_COMPLETEDPMC_EV_PPC7450_STWCX_INSTR_COMPLETEDPMC_EV_PPC7450_LS_LM_INSTR_PIECESPMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLDPMC_EV_PPC7450_DTLB_MISSESPMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSESPMC_EV_PPC7450_L1_DATA_CACHE_OP_HITPMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLESPMC_EV_PPC7450_L1_DATA_PUSHESPMC_EV_PPC7450_L1_DATA_TOTAL_MISSPMC_EV_PPC7450_VT2_FETCHESPMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSEDPMC_EV_PPC7450_BRANCH_FLUSHESPMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVEPMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCYPMC_EV_PPC7450_FAST_BTIC_HITPMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTEDPMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETEDPMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHEDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLDPMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLEDPMC_EV_PPC7450_IU1_INSTR_COMPLETEDPMC_EV_PPC7450_DSSALL_INSTR_COMPLETEDPMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SYNC_INSTR_COMPLETEDPMC_EV_PPC7450_SS_SM_INSTR_PIECESPMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLESPMC_EV_PPC7450_SNOOP_RETRIESPMC_EV_PPC7450_SUCCESSFUL_STWCXPMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHESPMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYPMC_EV_PPC7450_MISPREDICTED_BRANCHESPMC_EV_PPC7450_FOLDED_BRANCHESPMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSUPMC_EV_PPC7450_L2_CACHE_HITSPMC_EV_PPC7450_L3_CACHE_HITSPMC_EV_PPC7450_L2_INSTR_CACHE_MISSESPMC_EV_PPC7450_L3_INSTR_CACHE_MISSESPMC_EV_PPC7450_L2_DATA_CACHE_MISSESPMC_EV_PPC7450_L3_DATA_CACHE_MISSESPMC_EV_PPC7450_L2_LOAD_HITSPMC_EV_PPC7450_L2_STORE_HITSPMC_EV_PPC7450_L3_LOAD_HITSPMC_EV_PPC7450_L3_STORE_HITSPMC_EV_PPC7450_L2_TOUCH_HITSPMC_EV_PPC7450_L3_TOUCH_HITSPMC_EV_PPC7450_SNOOP_MODIFIEDPMC_EV_PPC7450_SNOOP_VALIDPMC_EV_PPC7450_INTERVENTIONPMC_EV_PPC7450_L2_CACHE_MISSESPMC_EV_PPC7450_L3_CACHE_MISSESPMC_EV_PPC7450_L2_CACHE_CASTOUTSPMC_EV_PPC7450_L3_CACHE_CASTOUTSPMC_EV_PPC7450_L2SQ_FULL_CYCLESPMC_EV_PPC7450_L3SQ_FULL_CYCLESPMC_EV_PPC7450_RAQ_FULL_CYCLESPMC_EV_PPC7450_WAQ_FULL_CYCLESPMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_INTERVENTIONSPMC_EV_PPC7450_EXTERNAL_PUSHESPMC_EV_PPC7450_EXTERNAL_SNOOP_RETRYPMC_EV_PPC7450_DTQ_FULL_CYCLESPMC_EV_PPC7450_BUS_RETRYPMC_EV_PPC7450_L2_VALID_REQUESTPMC_EV_PPC7450_BORDQ_FULLPMC_EV_PPC7450_BUS_TAS_FOR_READSPMC_EV_PPC7450_BUS_TAS_FOR_WRITESPMC_EV_PPC7450_BUS_READS_NOT_RETRIEDPMC_EV_PPC7450_BUS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIEDPMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRYPMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENTPMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISIONPMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERINGPMC_EV_PPC7450_SNOOP_REQUESTSPMC_EV_PPC7450_PREFETCH_ENGINE_REQUESTPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOADPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STOREPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCHPMC_EV_PPC7450_PREFETCH_ENGINE_FULLPMC_EV_PPC970__BLOCK_STARTPMC_EV_PPC970_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_GROUP_DISPATCHPMC_EV_PPC970_MARKED_STORE_COMPLETEDPMC_EV_PPC970_GCT_EMPTYPMC_EV_PPC970_RUN_CYCLESPMC_EV_PPC970_OVERFLOWPMC_EV_PPC970_CYCLESPMC_EV_PPC970_THRESHOLD_TIMEOUTPMC_EV_PPC970_GROUP_DISPATCHPMC_EV_PPC970_BR_MARKED_INSTR_FINISHPMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULLPMC_EV_PPC970_STOP_COMPLETIONPMC_EV_PPC970_LSU_EMPTYPMC_EV_PPC970_MARKED_STORE_WITH_INTRPMC_EV_PPC970_CYCLES_IN_SUPERPMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_FXU0_IDLE_FXU1_BUSYPMC_EV_PPC970_SRQ_EMPTYPMC_EV_PPC970_MARKED_GROUP_COMPLETEDPMC_EV_PPC970_CR_MARKED_INSTR_FINISHPMC_EV_PPC970_DISPATCH_SUCCESSPMC_EV_PPC970_FXU0_IDLE_FXU1_IDLEPMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETEDPMC_EV_PPC970_GROUP_MARKED_IDUPMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUTPMC_EV_PPC970_FXU0_BUSY_FXU1_BUSYPMC_EV_PPC970_MARKED_STORE_SENT_TO_STSPMC_EV_PPC970_FXU_MARKED_INSTR_FINISHEDPMC_EV_PPC970_MARKED_GROUP_ISSUEDPMC_EV_PPC970_FXU0_BUSY_FXU1_IDLEPMC_EV_PPC970_GROUP_COMPLETEDPMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETEDPMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNITPMC_EV_PPC970_EXTERNAL_INTERRUPTPMC_EV_PPC970_GROUP_DISPATCH_REJECTPMC_EV_PPC970_LSU_MARKED_INSTR_FINISHPMC_EV_PPC970_TIMEBASE_EVENTPMC_EV_PPC970_LSU_COMPLETION_STALLPMC_EV_PPC970_FXU_COMPLETION_STALLPMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALLPMC_EV_PPC970_FPU_COMPLETION_STALLPMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_REJECT_COMPLETION_STALLPMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALLPMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISSPMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISSPMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICTPMC_EV_PPC970_BUS_HIGHPMC_EV_PPC970_BUS_LOWPMC_EV_PPC970_ADDERPMC_EV_POWER8__BLOCK_STARTPMC_EV_POWER8_CYCLESPMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETEDPMC_EV_POWER8_FPU_INSTR_COMPLETEDPMC_EV_POWER8_ERAT_INSTR_MISSPMC_EV_POWER8_CYCLES_IDLEPMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNINGPMC_EV_POWER8_STORE_COMPLETEDPMC_EV_POWER8_INSTR_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNINGPMC_EV_POWER8_ERAT_DATA_MISSPMC_EV_POWER8_EXTERNAL_INTERRUPTPMC_EV_POWER8_BRANCH_TAKENPMC_EV_POWER8_L1_INSTR_MISSPMC_EV_POWER8_L2_LOAD_MISSPMC_EV_POWER8_STORE_NO_REAL_ADDRPMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNINGPMC_EV_POWER8_L1_LOAD_MISSPMC_EV_POWER8_TIMEBASE_EVENTPMC_EV_POWER8_L3_INSTR_MISSPMC_EV_POWER8_TLB_DATA_MISSPMC_EV_POWER8_L3_LOAD_MISSPMC_EV_POWER8_LOAD_NO_REAL_ADDRPMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHEDPMC_EV_POWER8_CYCLES_RUNNING_PURR_INCPMC_EV_POWER8_BRANCH_MISPREDICTEDPMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDEDPMC_EV_POWER8_INSTR_COMPLETED_RUNNINGPMC_EV_POWER8_TLB_INSTR_MISSPMC_EV_POWER8_CACHE_LOAD_MISSPMC_EV_POWER8_INSTR_COMPLETEDPMC_EV_E500__BLOCK_STARTPMC_EV_E500_CYCLESPMC_EV_E500_INSTR_COMPLETEDPMC_EV_E500_UOPS_COMPLETEDPMC_EV_E500_INSTR_FETCHEDPMC_EV_E500_UOPS_DECODEDPMC_EV_E500_PM_EVENT_TRANSITIONSPMC_EV_E500_PM_EVENT_CYCLESPMC_EV_E500_BRANCH_INSTRS_COMPLETEDPMC_EV_E500_LOAD_UOPS_COMPLETEDPMC_EV_E500_STORE_UOPS_COMPLETEDPMC_EV_E500_CQ_REDIRECTSPMC_EV_E500_BRANCHES_FINISHEDPMC_EV_E500_TAKEN_BRANCHES_FINISHEDPMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTBPMC_EV_E500_BRANCH_MISPREDPMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTIONPMC_EV_E500_BTB_HITS_PSEUDO_HITSPMC_EV_E500_CYCLES_DECODE_STALLEDPMC_EV_E500_CYCLES_ISSUE_STALLEDPMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLEDPMC_EV_E500_CYCLES_SU1_SCHED_STALLEDPMC_EV_E500_CYCLES_SU2_SCHED_STALLEDPMC_EV_E500_CYCLES_MU_SCHED_STALLEDPMC_EV_E500_CYCLES_LRU_SCHED_STALLEDPMC_EV_E500_CYCLES_BU_SCHED_STALLEDPMC_EV_E500_TOTAL_TRANSLATEDPMC_EV_E500_LOADS_TRANSLATEDPMC_EV_E500_STORES_TRANSLATEDPMC_EV_E500_TOUCHES_TRANSLATEDPMC_EV_E500_CACHEOPS_TRANSLATEDPMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATEDPMC_EV_E500_GUARDED_LOADS_TRANSLATEDPMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATEDPMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATEDPMC_EV_E500_TOTAL_ALLOCATED_TO_DLFBPMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFBPMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFBPMC_EV_E500_STORES_COMPLETEDPMC_EV_E500_DATA_L1_CACHE_LOCKSPMC_EV_E500_DATA_L1_CACHE_RELOADSPMC_EV_E500_DATA_L1_CACHE_CASTOUTSPMC_EV_E500_LOAD_MISS_DLFB_FULLPMC_EV_E500_LOAD_MISS_LDQ_FULLPMC_EV_E500_LOAD_GUARDED_MISSPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULLPMC_EV_E500_ADDRESS_COLLISIONPMC_EV_E500_DATA_MMU_MISSPMC_EV_E500_DATA_MMU_BUSYPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESSPMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLESPMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLESPMC_EV_E500_LOAD_GUARDED_MISS_CYCLESPMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLESPMC_EV_E500_ADDRESS_COLLISION_CYCLESPMC_EV_E500_DATA_MMU_MISS_CYCLESPMC_EV_E500_DATA_MMU_BUSY_CYCLESPMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLESPMC_EV_E500_INSTR_L1_CACHE_LOCKSPMC_EV_E500_INSTR_L1_CACHE_RELOADSPMC_EV_E500_INSTR_L1_CACHE_FETCHESPMC_EV_E500_INSTR_MMU_TLB4K_RELOADSPMC_EV_E500_INSTR_MMU_VSP_RELOADSPMC_EV_E500_DATA_MMU_TLB4K_RELOADSPMC_EV_E500_DATA_MMU_VSP_RELOADSPMC_EV_E500_L2MMU_MISSESPMC_EV_E500_BIU_MASTER_REQUESTSPMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTSPMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTSPMC_EV_E500_BIU_MASTER_RETRIESPMC_EV_E500_SNOOP_REQUESTSPMC_EV_E500_SNOOP_HITSPMC_EV_E500_SNOOP_PUSHESPMC_EV_E500_SNOOP_RETRIESPMC_EV_E500_DLFB_LOAD_MISS_CYCLESPMC_EV_E500_ILFB_FETCH_MISS_CYCLESPMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLESPMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLESPMC_EV_E500_PMC0_OVERFLOWPMC_EV_E500_PMC1_OVERFLOWPMC_EV_E500_PMC2_OVERFLOWPMC_EV_E500_PMC3_OVERFLOWPMC_EV_E500_INTERRUPTS_TAKENPMC_EV_E500_EXT_INPUT_INTR_TAKENPMC_EV_E500_CRIT_INPUT_INTR_TAKENPMC_EV_E500_SYSCALL_TRAP_INTRPMC_EV_E500_TLB_BIT_TRANSITIONSPMC_EV_E500_L2_LINEFILL_BUFFERPMC_EV_E500_LV2_VSPMC_EV_E500_CASTOUTS_RELEASEDPMC_EV_E500_INTV_ALLOCATIONSPMC_EV_E500_DLFB_RETRIES_TO_MBARPMC_EV_E500_STORE_RETRIESPMC_EV_E500_STASH_L1_HITSPMC_EV_E500_STASH_L2_HITSPMC_EV_E500_STASH_BUSY_1PMC_EV_E500_STASH_BUSY_2PMC_EV_E500_STASH_BUSY_3PMC_EV_E500_STASH_HITSPMC_EV_E500_STASH_HIT_DLFBPMC_EV_E500_STASH_REQUESTSPMC_EV_E500_STASH_REQUESTS_L1PMC_EV_E500_STASH_REQUESTS_L2PMC_EV_E500_STALLS_NO_CAQ_OR_COBPMC_EV_E500_L2_CACHE_ACCESSESPMC_EV_E500_L2_HIT_CACHE_ACCESSESPMC_EV_E500_L2_CACHE_DATA_ACCESSESPMC_EV_E500_L2_CACHE_DATA_HITSPMC_EV_E500_L2_CACHE_INSTR_ACCESSESPMC_EV_E500_L2_CACHE_INSTR_HITSPMC_EV_E500_L2_CACHE_ALLOCATIONSPMC_EV_E500_L2_CACHE_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONSPMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONSPMC_EV_E500_L2_CACHE_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_UPDATESPMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATESPMC_EV_E500_L2_CACHE_LOCKSPMC_EV_E500_L2_CACHE_CASTOUTSPMC_EV_E500_L2_CACHE_DATA_DIRTY_HITSPMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITYPMC_EV_E500_SNOOP_THROTTLING_TURNED_ONPMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONSPMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONSPMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONSPMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHESPMC_EV_E500_IAC1S_DETECTEDPMC_EV_E500_IAC2S_DETECTEDPMC_EV_E500_DAC1S_DTECTEDPMC_EV_E500_DAC2S_DTECTEDPMC_EV_E500_DVT0_DETECTEDPMC_EV_E500_DVT1_DETECTEDPMC_EV_E500_DVT2_DETECTEDPMC_EV_E500_DVT3_DETECTEDPMC_EV_E500_DVT4_DETECTEDPMC_EV_E500_DVT5_DETECTEDPMC_EV_E500_DVT6_DETECTEDPMC_EV_E500_DVT7_DETECTEDPMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULLPMC_EV_E500_FPU_DOUBLE_PUMPPMC_EV_E500_FPU_FINISHPMC_EV_E500_FPU_DIVIDE_CYCLESPMC_EV_E500_FPU_DENORM_INPUT_CYCLESPMC_EV_E500_FPU_RESULT_STALL_CYCLESPMC_EV_E500_FPU_FPSCR_FULL_STALLPMC_EV_E500_FPU_PIPE_SYNC_STALLSPMC_EV_E500_FPU_INPUT_DATA_STALLSPMC_EV_E500_DECORATED_LOADSPMC_EV_E500_DECORATED_STORESPMC_EV_E500_LOAD_RETRIESPMC_EV_E500_STWCX_SUCCESSESPMC_EV_E500_STWCX_FAILURESPMC_EV_ARMV7__BLOCK_STARTPMC_EV_ARMV7_EVENT_00HPMC_EV_ARMV7_EVENT_01HPMC_EV_ARMV7_EVENT_02HPMC_EV_ARMV7_EVENT_03HPMC_EV_ARMV7_EVENT_04HPMC_EV_ARMV7_EVENT_05HPMC_EV_ARMV7_EVENT_06HPMC_EV_ARMV7_EVENT_07HPMC_EV_ARMV7_EVENT_08HPMC_EV_ARMV7_EVENT_09HPMC_EV_ARMV7_EVENT_0AHPMC_EV_ARMV7_EVENT_0BHPMC_EV_ARMV7_EVENT_0CHPMC_EV_ARMV7_EVENT_0DHPMC_EV_ARMV7_EVENT_0EHPMC_EV_ARMV7_EVENT_0FHPMC_EV_ARMV7_EVENT_10HPMC_EV_ARMV7_EVENT_11HPMC_EV_ARMV7_EVENT_12HPMC_EV_ARMV7_EVENT_13HPMC_EV_ARMV7_EVENT_14HPMC_EV_ARMV7_EVENT_15HPMC_EV_ARMV7_EVENT_16HPMC_EV_ARMV7_EVENT_17HPMC_EV_ARMV7_EVENT_18HPMC_EV_ARMV7_EVENT_19HPMC_EV_ARMV7_EVENT_1AHPMC_EV_ARMV7_EVENT_1BHPMC_EV_ARMV7_EVENT_1CHPMC_EV_ARMV7_EVENT_1DHPMC_EV_ARMV7_EVENT_1EHPMC_EV_ARMV7_EVENT_1FHPMC_EV_ARMV7_EVENT_20HPMC_EV_ARMV7_EVENT_21HPMC_EV_ARMV7_EVENT_22HPMC_EV_ARMV7_EVENT_23HPMC_EV_ARMV7_EVENT_24HPMC_EV_ARMV7_EVENT_25HPMC_EV_ARMV7_EVENT_26HPMC_EV_ARMV7_EVENT_27HPMC_EV_ARMV7_EVENT_28HPMC_EV_ARMV7_EVENT_29HPMC_EV_ARMV7_EVENT_2AHPMC_EV_ARMV7_EVENT_2BHPMC_EV_ARMV7_EVENT_2CHPMC_EV_ARMV7_EVENT_2DHPMC_EV_ARMV7_EVENT_2EHPMC_EV_ARMV7_EVENT_2FHPMC_EV_ARMV7_EVENT_30HPMC_EV_ARMV7_EVENT_31HPMC_EV_ARMV7_EVENT_32HPMC_EV_ARMV7_EVENT_33HPMC_EV_ARMV7_EVENT_34HPMC_EV_ARMV7_EVENT_35HPMC_EV_ARMV7_EVENT_36HPMC_EV_ARMV7_EVENT_37HPMC_EV_ARMV7_EVENT_38HPMC_EV_ARMV7_EVENT_39HPMC_EV_ARMV7_EVENT_3AHPMC_EV_ARMV7_EVENT_3BHPMC_EV_ARMV7_EVENT_3CHPMC_EV_ARMV7_EVENT_3DHPMC_EV_ARMV7_EVENT_3EHPMC_EV_ARMV7_EVENT_3FHPMC_EV_ARMV7_EVENT_40HPMC_EV_ARMV7_EVENT_41HPMC_EV_ARMV7_EVENT_42HPMC_EV_ARMV7_EVENT_43HPMC_EV_ARMV7_EVENT_44HPMC_EV_ARMV7_EVENT_45HPMC_EV_ARMV7_EVENT_46HPMC_EV_ARMV7_EVENT_47HPMC_EV_ARMV7_EVENT_48HPMC_EV_ARMV7_EVENT_49HPMC_EV_ARMV7_EVENT_4AHPMC_EV_ARMV7_EVENT_4BHPMC_EV_ARMV7_EVENT_4CHPMC_EV_ARMV7_EVENT_4DHPMC_EV_ARMV7_EVENT_4EHPMC_EV_ARMV7_EVENT_4FHPMC_EV_ARMV7_EVENT_50HPMC_EV_ARMV7_EVENT_51HPMC_EV_ARMV7_EVENT_52HPMC_EV_ARMV7_EVENT_53HPMC_EV_ARMV7_EVENT_54HPMC_EV_ARMV7_EVENT_55HPMC_EV_ARMV7_EVENT_56HPMC_EV_ARMV7_EVENT_57HPMC_EV_ARMV7_EVENT_58HPMC_EV_ARMV7_EVENT_59HPMC_EV_ARMV7_EVENT_5AHPMC_EV_ARMV7_EVENT_5BHPMC_EV_ARMV7_EVENT_5CHPMC_EV_ARMV7_EVENT_5DHPMC_EV_ARMV7_EVENT_5EHPMC_EV_ARMV7_EVENT_5FHPMC_EV_ARMV7_EVENT_60HPMC_EV_ARMV7_EVENT_61HPMC_EV_ARMV7_EVENT_62HPMC_EV_ARMV7_EVENT_63HPMC_EV_ARMV7_EVENT_64HPMC_EV_ARMV7_EVENT_65HPMC_EV_ARMV7_EVENT_66HPMC_EV_ARMV7_EVENT_67HPMC_EV_ARMV7_EVENT_68HPMC_EV_ARMV7_EVENT_69HPMC_EV_ARMV7_EVENT_6AHPMC_EV_ARMV7_EVENT_6BHPMC_EV_ARMV7_EVENT_6CHPMC_EV_ARMV7_EVENT_6DHPMC_EV_ARMV7_EVENT_6EHPMC_EV_ARMV7_EVENT_6FHPMC_EV_ARMV7_EVENT_70HPMC_EV_ARMV7_EVENT_71HPMC_EV_ARMV7_EVENT_72HPMC_EV_ARMV7_EVENT_73HPMC_EV_ARMV7_EVENT_74HPMC_EV_ARMV7_EVENT_75HPMC_EV_ARMV7_EVENT_76HPMC_EV_ARMV7_EVENT_77HPMC_EV_ARMV7_EVENT_78HPMC_EV_ARMV7_EVENT_79HPMC_EV_ARMV7_EVENT_7AHPMC_EV_ARMV7_EVENT_7BHPMC_EV_ARMV7_EVENT_7CHPMC_EV_ARMV7_EVENT_7DHPMC_EV_ARMV7_EVENT_7EHPMC_EV_ARMV7_EVENT_7FHPMC_EV_ARMV7_EVENT_80HPMC_EV_ARMV7_EVENT_81HPMC_EV_ARMV7_EVENT_82HPMC_EV_ARMV7_EVENT_83HPMC_EV_ARMV7_EVENT_84HPMC_EV_ARMV7_EVENT_85HPMC_EV_ARMV7_EVENT_86HPMC_EV_ARMV7_EVENT_87HPMC_EV_ARMV7_EVENT_88HPMC_EV_ARMV7_EVENT_89HPMC_EV_ARMV7_EVENT_8AHPMC_EV_ARMV7_EVENT_8BHPMC_EV_ARMV7_EVENT_8CHPMC_EV_ARMV7_EVENT_8DHPMC_EV_ARMV7_EVENT_8EHPMC_EV_ARMV7_EVENT_8FHPMC_EV_ARMV7_EVENT_90HPMC_EV_ARMV7_EVENT_91HPMC_EV_ARMV7_EVENT_92HPMC_EV_ARMV7_EVENT_93HPMC_EV_ARMV7_EVENT_94HPMC_EV_ARMV7_EVENT_95HPMC_EV_ARMV7_EVENT_96HPMC_EV_ARMV7_EVENT_97HPMC_EV_ARMV7_EVENT_98HPMC_EV_ARMV7_EVENT_99HPMC_EV_ARMV7_EVENT_9AHPMC_EV_ARMV7_EVENT_9BHPMC_EV_ARMV7_EVENT_9CHPMC_EV_ARMV7_EVENT_9DHPMC_EV_ARMV7_EVENT_9EHPMC_EV_ARMV7_EVENT_9FHPMC_EV_ARMV7_EVENT_A0HPMC_EV_ARMV7_EVENT_A1HPMC_EV_ARMV7_EVENT_A2HPMC_EV_ARMV7_EVENT_A3HPMC_EV_ARMV7_EVENT_A4HPMC_EV_ARMV7_EVENT_A5HPMC_EV_ARMV7_EVENT_A6HPMC_EV_ARMV7_EVENT_A7HPMC_EV_ARMV7_EVENT_A8HPMC_EV_ARMV7_EVENT_A9HPMC_EV_ARMV7_EVENT_AAHPMC_EV_ARMV7_EVENT_ABHPMC_EV_ARMV7_EVENT_ACHPMC_EV_ARMV7_EVENT_ADHPMC_EV_ARMV7_EVENT_AEHPMC_EV_ARMV7_EVENT_AFHPMC_EV_ARMV7_EVENT_B0HPMC_EV_ARMV7_EVENT_B1HPMC_EV_ARMV7_EVENT_B2HPMC_EV_ARMV7_EVENT_B3HPMC_EV_ARMV7_EVENT_B4HPMC_EV_ARMV7_EVENT_B5HPMC_EV_ARMV7_EVENT_B6HPMC_EV_ARMV7_EVENT_B7HPMC_EV_ARMV7_EVENT_B8HPMC_EV_ARMV7_EVENT_B9HPMC_EV_ARMV7_EVENT_BAHPMC_EV_ARMV7_EVENT_BBHPMC_EV_ARMV7_EVENT_BCHPMC_EV_ARMV7_EVENT_BDHPMC_EV_ARMV7_EVENT_BEHPMC_EV_ARMV7_EVENT_BFHPMC_EV_ARMV7_EVENT_C0HPMC_EV_ARMV7_EVENT_C1HPMC_EV_ARMV7_EVENT_C2HPMC_EV_ARMV7_EVENT_C3HPMC_EV_ARMV7_EVENT_C4HPMC_EV_ARMV7_EVENT_C5HPMC_EV_ARMV7_EVENT_C6HPMC_EV_ARMV7_EVENT_C7HPMC_EV_ARMV7_EVENT_C8HPMC_EV_ARMV7_EVENT_C9HPMC_EV_ARMV7_EVENT_CAHPMC_EV_ARMV7_EVENT_CBHPMC_EV_ARMV7_EVENT_CCHPMC_EV_ARMV7_EVENT_CDHPMC_EV_ARMV7_EVENT_CEHPMC_EV_ARMV7_EVENT_CFHPMC_EV_ARMV7_EVENT_D0HPMC_EV_ARMV7_EVENT_D1HPMC_EV_ARMV7_EVENT_D2HPMC_EV_ARMV7_EVENT_D3HPMC_EV_ARMV7_EVENT_D4HPMC_EV_ARMV7_EVENT_D5HPMC_EV_ARMV7_EVENT_D6HPMC_EV_ARMV7_EVENT_D7HPMC_EV_ARMV7_EVENT_D8HPMC_EV_ARMV7_EVENT_D9HPMC_EV_ARMV7_EVENT_DAHPMC_EV_ARMV7_EVENT_DBHPMC_EV_ARMV7_EVENT_DCHPMC_EV_ARMV7_EVENT_DDHPMC_EV_ARMV7_EVENT_DEHPMC_EV_ARMV7_EVENT_DFHPMC_EV_ARMV7_EVENT_E0HPMC_EV_ARMV7_EVENT_E1HPMC_EV_ARMV7_EVENT_E2HPMC_EV_ARMV7_EVENT_E3HPMC_EV_ARMV7_EVENT_E4HPMC_EV_ARMV7_EVENT_E5HPMC_EV_ARMV7_EVENT_E6HPMC_EV_ARMV7_EVENT_E7HPMC_EV_ARMV7_EVENT_E8HPMC_EV_ARMV7_EVENT_E9HPMC_EV_ARMV7_EVENT_EAHPMC_EV_ARMV7_EVENT_EBHPMC_EV_ARMV7_EVENT_ECHPMC_EV_ARMV7_EVENT_EDHPMC_EV_ARMV7_EVENT_EEHPMC_EV_ARMV7_EVENT_EFHPMC_EV_ARMV7_EVENT_F0HPMC_EV_ARMV7_EVENT_F1HPMC_EV_ARMV7_EVENT_F2HPMC_EV_ARMV7_EVENT_F3HPMC_EV_ARMV7_EVENT_F4HPMC_EV_ARMV7_EVENT_F5HPMC_EV_ARMV7_EVENT_F6HPMC_EV_ARMV7_EVENT_F7HPMC_EV_ARMV7_EVENT_F8HPMC_EV_ARMV7_EVENT_F9HPMC_EV_ARMV7_EVENT_FAHPMC_EV_ARMV7_EVENT_FBHPMC_EV_ARMV7_EVENT_FCHPMC_EV_ARMV7_EVENT_FDHPMC_EV_ARMV7_EVENT_FEHPMC_EV_ARMV7_EVENT_FFHPMC_EV_ARMV8__BLOCK_STARTPMC_EV_ARMV8_EVENT_00HPMC_EV_ARMV8_EVENT_01HPMC_EV_ARMV8_EVENT_02HPMC_EV_ARMV8_EVENT_03HPMC_EV_ARMV8_EVENT_04HPMC_EV_ARMV8_EVENT_05HPMC_EV_ARMV8_EVENT_06HPMC_EV_ARMV8_EVENT_07HPMC_EV_ARMV8_EVENT_08HPMC_EV_ARMV8_EVENT_09HPMC_EV_ARMV8_EVENT_0AHPMC_EV_ARMV8_EVENT_0BHPMC_EV_ARMV8_EVENT_0CHPMC_EV_ARMV8_EVENT_0DHPMC_EV_ARMV8_EVENT_0EHPMC_EV_ARMV8_EVENT_0FHPMC_EV_ARMV8_EVENT_10HPMC_EV_ARMV8_EVENT_11HPMC_EV_ARMV8_EVENT_12HPMC_EV_ARMV8_EVENT_13HPMC_EV_ARMV8_EVENT_14HPMC_EV_ARMV8_EVENT_15HPMC_EV_ARMV8_EVENT_16HPMC_EV_ARMV8_EVENT_17HPMC_EV_ARMV8_EVENT_18HPMC_EV_ARMV8_EVENT_19HPMC_EV_ARMV8_EVENT_1AHPMC_EV_ARMV8_EVENT_1BHPMC_EV_ARMV8_EVENT_1CHPMC_EV_ARMV8_EVENT_1DHPMC_EV_ARMV8_EVENT_1EHPMC_EV_ARMV8_EVENT_1FHPMC_EV_ARMV8_EVENT_20HPMC_EV_ARMV8_EVENT_21HPMC_EV_ARMV8_EVENT_22HPMC_EV_ARMV8_EVENT_23HPMC_EV_ARMV8_EVENT_24HPMC_EV_ARMV8_EVENT_25HPMC_EV_ARMV8_EVENT_26HPMC_EV_ARMV8_EVENT_27HPMC_EV_ARMV8_EVENT_28HPMC_EV_ARMV8_EVENT_29HPMC_EV_ARMV8_EVENT_2AHPMC_EV_ARMV8_EVENT_2BHPMC_EV_ARMV8_EVENT_2CHPMC_EV_ARMV8_EVENT_2DHPMC_EV_ARMV8_EVENT_2EHPMC_EV_ARMV8_EVENT_2FHPMC_EV_ARMV8_EVENT_30HPMC_EV_ARMV8_EVENT_31HPMC_EV_ARMV8_EVENT_32HPMC_EV_ARMV8_EVENT_33HPMC_EV_ARMV8_EVENT_34HPMC_EV_ARMV8_EVENT_35HPMC_EV_ARMV8_EVENT_36HPMC_EV_ARMV8_EVENT_37HPMC_EV_ARMV8_EVENT_38HPMC_EV_ARMV8_EVENT_39HPMC_EV_ARMV8_EVENT_3AHPMC_EV_ARMV8_EVENT_3BHPMC_EV_ARMV8_EVENT_3CHPMC_EV_ARMV8_EVENT_3DHPMC_EV_ARMV8_EVENT_3EHPMC_EV_ARMV8_EVENT_3FHPMC_EV_ARMV8_EVENT_40HPMC_EV_ARMV8_EVENT_41HPMC_EV_ARMV8_EVENT_42HPMC_EV_ARMV8_EVENT_43HPMC_EV_ARMV8_EVENT_44HPMC_EV_ARMV8_EVENT_45HPMC_EV_ARMV8_EVENT_46HPMC_EV_ARMV8_EVENT_47HPMC_EV_ARMV8_EVENT_48HPMC_EV_ARMV8_EVENT_49HPMC_EV_ARMV8_EVENT_4AHPMC_EV_ARMV8_EVENT_4BHPMC_EV_ARMV8_EVENT_4CHPMC_EV_ARMV8_EVENT_4DHPMC_EV_ARMV8_EVENT_4EHPMC_EV_ARMV8_EVENT_4FHPMC_EV_ARMV8_EVENT_50HPMC_EV_ARMV8_EVENT_51HPMC_EV_ARMV8_EVENT_52HPMC_EV_ARMV8_EVENT_53HPMC_EV_ARMV8_EVENT_54HPMC_EV_ARMV8_EVENT_55HPMC_EV_ARMV8_EVENT_56HPMC_EV_ARMV8_EVENT_57HPMC_EV_ARMV8_EVENT_58HPMC_EV_ARMV8_EVENT_59HPMC_EV_ARMV8_EVENT_5AHPMC_EV_ARMV8_EVENT_5BHPMC_EV_ARMV8_EVENT_5CHPMC_EV_ARMV8_EVENT_5DHPMC_EV_ARMV8_EVENT_5EHPMC_EV_ARMV8_EVENT_5FHPMC_EV_ARMV8_EVENT_60HPMC_EV_ARMV8_EVENT_61HPMC_EV_ARMV8_EVENT_62HPMC_EV_ARMV8_EVENT_63HPMC_EV_ARMV8_EVENT_64HPMC_EV_ARMV8_EVENT_65HPMC_EV_ARMV8_EVENT_66HPMC_EV_ARMV8_EVENT_67HPMC_EV_ARMV8_EVENT_68HPMC_EV_ARMV8_EVENT_69HPMC_EV_ARMV8_EVENT_6AHPMC_EV_ARMV8_EVENT_6BHPMC_EV_ARMV8_EVENT_6CHPMC_EV_ARMV8_EVENT_6DHPMC_EV_ARMV8_EVENT_6EHPMC_EV_ARMV8_EVENT_6FHPMC_EV_ARMV8_EVENT_70HPMC_EV_ARMV8_EVENT_71HPMC_EV_ARMV8_EVENT_72HPMC_EV_ARMV8_EVENT_73HPMC_EV_ARMV8_EVENT_74HPMC_EV_ARMV8_EVENT_75HPMC_EV_ARMV8_EVENT_76HPMC_EV_ARMV8_EVENT_77HPMC_EV_ARMV8_EVENT_78HPMC_EV_ARMV8_EVENT_79HPMC_EV_ARMV8_EVENT_7AHPMC_EV_ARMV8_EVENT_7BHPMC_EV_ARMV8_EVENT_7CHPMC_EV_ARMV8_EVENT_7DHPMC_EV_ARMV8_EVENT_7EHPMC_EV_ARMV8_EVENT_7FHPMC_EV_ARMV8_EVENT_80HPMC_EV_ARMV8_EVENT_81HPMC_EV_ARMV8_EVENT_82HPMC_EV_ARMV8_EVENT_83HPMC_EV_ARMV8_EVENT_84HPMC_EV_ARMV8_EVENT_85HPMC_EV_ARMV8_EVENT_86HPMC_EV_ARMV8_EVENT_87HPMC_EV_ARMV8_EVENT_88HPMC_EV_ARMV8_EVENT_89HPMC_EV_ARMV8_EVENT_8AHPMC_EV_ARMV8_EVENT_8BHPMC_EV_ARMV8_EVENT_8CHPMC_EV_ARMV8_EVENT_8DHPMC_EV_ARMV8_EVENT_8EHPMC_EV_ARMV8_EVENT_8FHPMC_EV_ARMV8_EVENT_90HPMC_EV_ARMV8_EVENT_91HPMC_EV_ARMV8_EVENT_92HPMC_EV_ARMV8_EVENT_93HPMC_EV_ARMV8_EVENT_94HPMC_EV_ARMV8_EVENT_95HPMC_EV_ARMV8_EVENT_96HPMC_EV_ARMV8_EVENT_97HPMC_EV_ARMV8_EVENT_98HPMC_EV_ARMV8_EVENT_99HPMC_EV_ARMV8_EVENT_9AHPMC_EV_ARMV8_EVENT_9BHPMC_EV_ARMV8_EVENT_9CHPMC_EV_ARMV8_EVENT_9DHPMC_EV_ARMV8_EVENT_9EHPMC_EV_ARMV8_EVENT_9FHPMC_EV_ARMV8_EVENT_A0HPMC_EV_ARMV8_EVENT_A1HPMC_EV_ARMV8_EVENT_A2HPMC_EV_ARMV8_EVENT_A3HPMC_EV_ARMV8_EVENT_A4HPMC_EV_ARMV8_EVENT_A5HPMC_EV_ARMV8_EVENT_A6HPMC_EV_ARMV8_EVENT_A7HPMC_EV_ARMV8_EVENT_A8HPMC_EV_ARMV8_EVENT_A9HPMC_EV_ARMV8_EVENT_AAHPMC_EV_ARMV8_EVENT_ABHPMC_EV_ARMV8_EVENT_ACHPMC_EV_ARMV8_EVENT_ADHPMC_EV_ARMV8_EVENT_AEHPMC_EV_ARMV8_EVENT_AFHPMC_EV_ARMV8_EVENT_B0HPMC_EV_ARMV8_EVENT_B1HPMC_EV_ARMV8_EVENT_B2HPMC_EV_ARMV8_EVENT_B3HPMC_EV_ARMV8_EVENT_B4HPMC_EV_ARMV8_EVENT_B5HPMC_EV_ARMV8_EVENT_B6HPMC_EV_ARMV8_EVENT_B7HPMC_EV_ARMV8_EVENT_B8HPMC_EV_ARMV8_EVENT_B9HPMC_EV_ARMV8_EVENT_BAHPMC_EV_ARMV8_EVENT_BBHPMC_EV_ARMV8_EVENT_BCHPMC_EV_ARMV8_EVENT_BDHPMC_EV_ARMV8_EVENT_BEHPMC_EV_ARMV8_EVENT_BFHPMC_EV_ARMV8_EVENT_C0HPMC_EV_ARMV8_EVENT_C1HPMC_EV_ARMV8_EVENT_C2HPMC_EV_ARMV8_EVENT_C3HPMC_EV_ARMV8_EVENT_C4HPMC_EV_ARMV8_EVENT_C5HPMC_EV_ARMV8_EVENT_C6HPMC_EV_ARMV8_EVENT_C7HPMC_EV_ARMV8_EVENT_C8HPMC_EV_ARMV8_EVENT_C9HPMC_EV_ARMV8_EVENT_CAHPMC_EV_ARMV8_EVENT_CBHPMC_EV_ARMV8_EVENT_CCHPMC_EV_ARMV8_EVENT_CDHPMC_EV_ARMV8_EVENT_CEHPMC_EV_ARMV8_EVENT_CFHPMC_EV_ARMV8_EVENT_D0HPMC_EV_ARMV8_EVENT_D1HPMC_EV_ARMV8_EVENT_D2HPMC_EV_ARMV8_EVENT_D3HPMC_EV_ARMV8_EVENT_D4HPMC_EV_ARMV8_EVENT_D5HPMC_EV_ARMV8_EVENT_D6HPMC_EV_ARMV8_EVENT_D7HPMC_EV_ARMV8_EVENT_D8HPMC_EV_ARMV8_EVENT_D9HPMC_EV_ARMV8_EVENT_DAHPMC_EV_ARMV8_EVENT_DBHPMC_EV_ARMV8_EVENT_DCHPMC_EV_ARMV8_EVENT_DDHPMC_EV_ARMV8_EVENT_DEHPMC_EV_ARMV8_EVENT_DFHPMC_EV_ARMV8_EVENT_E0HPMC_EV_ARMV8_EVENT_E1HPMC_EV_ARMV8_EVENT_E2HPMC_EV_ARMV8_EVENT_E3HPMC_EV_ARMV8_EVENT_E4HPMC_EV_ARMV8_EVENT_E5HPMC_EV_ARMV8_EVENT_E6HPMC_EV_ARMV8_EVENT_E7HPMC_EV_ARMV8_EVENT_E8HPMC_EV_ARMV8_EVENT_E9HPMC_EV_ARMV8_EVENT_EAHPMC_EV_ARMV8_EVENT_EBHPMC_EV_ARMV8_EVENT_ECHPMC_EV_ARMV8_EVENT_EDHPMC_EV_ARMV8_EVENT_EEHPMC_EV_ARMV8_EVENT_EFHPMC_EV_ARMV8_EVENT_F0HPMC_EV_ARMV8_EVENT_F1HPMC_EV_ARMV8_EVENT_F2HPMC_EV_ARMV8_EVENT_F3HPMC_EV_ARMV8_EVENT_F4HPMC_EV_ARMV8_EVENT_F5HPMC_EV_ARMV8_EVENT_F6HPMC_EV_ARMV8_EVENT_F7HPMC_EV_ARMV8_EVENT_F8HPMC_EV_ARMV8_EVENT_F9HPMC_EV_ARMV8_EVENT_FAHPMC_EV_ARMV8_EVENT_FBHPMC_EV_ARMV8_EVENT_FCHPMC_EV_ARMV8_EVENT_FDHPMC_EV_ARMV8_EVENT_FEHPMC_EV_ARMV8_EVENT_FFHpmc_eventPMC_MODE_SSPMC_MODE_SCPMC_MODE_TSPMC_MODE_TCpmc_modePMU_INVALIDPMU_INTELPMU_AMDPMC_CAP_INTERRUPTPMC_CAP_USERPMC_CAP_SYSTEMPMC_CAP_EDGEPMC_CAP_THRESHOLDPMC_CAP_READPMC_CAP_WRITEPMC_CAP_INVERTPMC_CAP_QUALIFIERPMC_CAP_PRECISEPMC_CAP_TAGGINGPMC_CAP_CASCADEpmc_capsPMC_AMD_SUB_CLASS_COREPMC_AMD_SUB_CLASS_L3_CACHEPMC_AMD_SUB_CLASS_DATA_FABRICsub_classlong long unsigned int__uint64_tuint64_tpmu_events_mfrpmu_mfr_tbufs__uint32_t__size_tsize_tmfrpmu_alias_getnamepmu_alias_tablepapmu_event_getaliaseventdesctopiclong_descpmuunitperpkgmetric_exprmetric_namemetric_grouppmu_eventcpuidevent_nameidxintpmeversiontypetablepmu_events_mapipesysctlbynamestrcasestrregcompre_magicre_nsubre_endpre_gre_gutsregexecrm_solong long int__int64_t__off_tregoff_trm_eoregfreestrsepgetenvfreepmc_pmu_intel_pmcallocatepmpm_capsuint32_tpm_cpupm_classpm_evpm_flagspm_modepm_pmcidpmc_id_tpm_countpmc_value_tpm_mdpm_amdpm_amd_configpm_amd_sub_classpmc_md_amd_op_pmcallocatepm_iappm_iap_configpm_iap_rsppmc_md_iap_op_pmcallocatepm_ucfpm_ucf_flagsunsigned short__uint16_tuint16_tpmc_md_ucf_op_pmcallocatepm_ucppm_ucp_configpmc_md_ucp_op_pmcallocate__padpmc_md_op_pmcallocatepmc_op_pmcallocatepedped_periodped_offcore_rspped_l3_threadped_l3_sliceped_eventped_frontendped_ldlatped_config1ped_umaskshort__int16_tint16_tped_cmaskunsigned char__uint8_tuint8_tped_anyped_invped_edgeped_fc_maskped_ch_maskpmu_event_descisfixediappmc_pmu_amd_pmcallocateamdpmc_pmu_enabledpmc_pmu_idx_get_by_eventpmc_pmu_event_get_by_idxpmu_events_map_getpmc_pmu_sample_rate_getpmu_parse_eventpmc_pmu_print_counterspmc_pmu_print_counter_descpmc_pmu_print_counter_desc_longpmc_pmu_print_counter_fullpmc_pmu_pmcallocatepmc_pmu_stat_moderealnamereregex_tpmatchregmatch_tmatcheventinrkvpvaluekeydebugdo_debugevcntrsFreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe)
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I8I`I�I�I�I�IJNJ{J�J�J�J�J#KOKqK�K�K�K4LdL�L�L�L�L&MSM|M�M�M�MN<N^N�N�N�NO(OFOhO�O�O�OP;PnP�P�P�PQEQlQ�Q�Q�QR"RGRdR�R�R�RS9SiS�S�S�S�ST5TQTnT�T�T�T�T�TU6UUUtU�U�U�U�UV4V]V�V�V�V�VW7WPWpW�W�W�W�WXDXmX�X�X�XYDYuY�Y�Y"ZFZaZZ�Z�Z�Z�Z[%[E[b[�[�[�[�[\$\M\o\�\�\�\�\]9]X]�]�]�]�]^9^W^�^�^�^�^_3_V_y_�_�_�_`I`p`�`�`�`�`a+a@aka�a�a�a�ab/bLbib�b�b�b�b�b4cOclc�c�c�c�cd1dSd}d�d�d�d�de(eDe_eye�e�e�e�ef4fMfkf�f�f�fg'gIgjg�g�g�gh%hIhfh�h�h�h�hi3i_i�i�i�ijFjcj�j�j�j�jk%kQkok�k�k�k�kl?lrl�l�l�l
m+mNmqm�m�m�m�mn4n_n�n�n�n�no%o?oao�o�o�o
p=pWpqp�p�p�p�pq#qCqbquq�q�q�q�qrr8rQrjr�r�r�r�r�rs2sTsws�s�s�s�s!tMttt�t�t�tu1uLuju�u�u�uv4v_v�v�v�v�vw(wBw\wvw�w�w�w�wx0xGxex�x�x�x�xy-yJycyy�y�y�y�y�yz'z>zUzlz�z�z�z�z�z�z
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uc1�QPhh��p���V�����V���������3���B
��؈�p�����p�����T�����q������F
�R
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��p�����P�����t���S��p���PW��������p����
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��s�����X�����Y�����u<�I��T����Ã����S������Ɖ�`�����
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��s�����X�����Y�����u<�I��T����Ã����S������Ɖ�`�����
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I:;�
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A
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G
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J
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c
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e
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h
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"
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"J/
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00
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00
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00
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00
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i
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j
J/-#-#l
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00�0�0�/r
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-#;$�
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�7v/*A
�7�7+B�7
�7�7*C
�7+Ev/
�7115812�/15K81D�/1E�81F�81G�81H�81I�81J91K 91L;91MQ91Nl91O�91P�91Q�91R�91S�91T:1U :1V6:1XP:1Zf:1[�:1\�:1��:1��:1��:1��:1��:1�	;1��31�]41�&;1�<;1�R;1�h;1�~;1��;1��;1��;1��;1��;1�<1�<1�.<1�D<1�Z<1�p<1��<1��<1�81��71c�/1d�<1e�<1g=1i-=1jE=1kV=1mg=1ox=1p�=1q�=1r�=1t�=1v�=1x>1z9>1{D>1|Q>1}g>1~t>1�>1��>1��>1��>1��>1��>1��>1��>1�/?1�K?1�`?1�q?1��?1��?1��?1��?1��?1�@1�@1�6@1�[@1�l@1 9y@1 :�/1 ;�21 <�@1 @A1 A(A1 B>A1 CTA1 EjA1 F�A1 G�A1 H�A1 J�A	2"jZ(
31$k�A1$l�C1$m�/1$o D1$p6D1$qGD1$rZD1$s{D1$t�D1$u�D1$v�D1$w�D1$x�D1$y(E1$zDE1${`E1$|�E1$}�E1$~�E1$�E1$��E1$��E1$�F1$�"F1$�9F1$�ZF1$�{F1$��F1$��F1$��F1$��F1$��F1$�
G1$�G1$�#G1$�1G1$�HG1$�dG1$�vG1$��G1$��G1$��G1$��G1$��G1$��G1$��G1$�H1$�H1&g/H1&h@H1&iQH1&jbH1&ksH1&l�H1&m�H1&n�H1&o�H1&p�H1&q�H1&r�H1&s�H1&tI1(>I1(?>I1(@II1(ATI1(BeI1(CvI1(D�I1(E�I1(F�I1(G�I1(H�I1(I�I1(J�I1(K�I1(LJ1(M J1(N6J1(OGJ1(PXJ1(QiJ1(RJ1*s�J1*t�/1*u�@1*vI1*w�A1*x�J1*y�J1*z�J1*{�J1*|K1*} K1*~7K1*RK1*�mK1*�~K1*��K1*��K1*��K1*��K1*��K1*�L1*�L1*�3L1*�IL1*�_L1*�zL1*��L1*��L1*��L1*��L1*��L1*�M1*�-M1*�CM1*�YM1*�tM1*��M1*��M1*��M1*��M1*��M1*�N1*�,N1*�=N1*�SN1*�nN1*��N1*��N1*��N1*��N1*��N1*�O1*�O1*�7O1*�WO1*�wO1*��O1*��O1*��O1*��O1*��O1*�P1*� P1*�6P4-�v3
5-�/5-�/
-

-
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v3�/-!
v3�/-J
v36-S

7-S
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�/(:.v/<.�/=8A�0v/�/*P
�0+T�/
�0+Xv/
�0+\v/
�0`/9�.�'.
0�
8�70�
8v/*�
8	8:�

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.�$S0U
�7�70V
�7v/*X
�7�7+Y�7
�7�7:[

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�7*e
�7�7:g

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=�w`/>
l/=w?`/{/=`/?{/�/��/s�/<>�/@�/�???�/==J/�/=�/=�>
~
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?�

1C<
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� .t1
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4
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)
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(
	

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=I

:C
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A.�3
B.]4
C.�2
D.z4
Eh4Gs4D>`/H�/C
H.�4
I.�3
J.z4
K�4��29F
N.�4
O.�3
P.�3
QF
].v/
^.]4
_.�3
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a.@5
b�3�
FL
e.�5
f.�3
g@.�3
hD.@5
iH`/�/@C
l.@5
m.�4
n.z4
oF
r.@5
s.�4
tF
w.�4
x.�4
y.@5
z.6
{]4�
F
~.�4
.�3
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�.�4
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�.z4
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�F
�.�4
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�F
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�F 
�.�4
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�.�3
�.W6
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�F
�.�3
�J72Tv/�/�7Xh4y�7K�7L00�.?�7=�.�7�7=�$�$?�7?�$.?�7=n?�7=.?.�7�-?8=�-8T�2]M134/@8,�2pV8Ea8oNjO�2kO�8m>P@v3v3�/�/PDv3v3�/�/PT[/[/v/Pg[/[/v/�/PM[/[/v/Pe[/[/v/�/P?00�/�/�/PR00v/v/Pf00v/v/�/PS00v/v/P}�/[/v/�//bv3v300�//M[/[/00PU�/v/v//T[/[/v//[[/[/00Pw�/v/v//i[/[/v/Py[/[/v/PEv3v300�/PY[/00Pa�/v/�:$�:7>
�:)�:9>�2.�23�:8�/8;=;:>1;(�:bG;)�:c];*�2ds;+�2e�;-�:~�;.;�;/�/��;0h4��;2�2^�;3�2_
<4�2`#<5�2a9<7�/zO<8�/{e<9�/|{<:h4}�<L�2[�<P�/w�<BN?.00@.00A�<GND.�2E.�2F=�N�.�2�.�2�P]>=v/>P^00v/P_�2v/P��2v/Ps>=v/�=[/Pt�=v/�=>Pw�8v/�=Pu�2v/�=00P��2v/�=00Py>v/�=00>P�s4v/�=00Qp008r�/Pbv3�/�/8fv3Pjv3�/Pqv3v3�/RZP\00�>�>STe00T�00Pg[/v/Pz00v/P`v3�/�/�/�/??00�/�/8nv3�/�/?/�8�8Ph�2�2P��2�2/�=�2�2Pi�<�2�2P�=�2�2Pk00v/�/Pm00�?v/�/�?>P{00[/�?Pl�/�?v/�/P|�/[/Q@�/V@=�?P�00�>T�00�@^>TF,!�.00!�.00!�.00!�.00!�.00!�.00!�.00!�.00!�.00!� .�2!�$.[/!�(Q!�y@P!�>=�2�2P!��2OA�@P!��2eA�2P!�[/{A�A=�@P!�[/�A�A=�2P!�OA�AP!�OA�AP!��/[/�/v/{A�A#�F�#|./C#}.00#~.00#.�:#�.�:#�.4C#�.00#�.v3#�.VC#� .fC#�$.�C#�(.�C#�,.4C#�0./C#�8.00#�<.�C#�@.�C#�C.4C#�D.00#�L.�C#�P.�C#�X.�C#�\.00#�`.00#�d.�C#�h.00#���/F#[./C#\.00#][C00v3kC00v3[/00�C�Cv3�C00�2#/�C00v3v/00�/�/�/�/
�C!�C!�C|U�y.Dz.�2{`/�/�P#�001D�AP#�001D$#
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�21D$#
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00V#
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Up
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o2"So+Si�R
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llvmorg-11.0.1-0-g43ff75f2c3fe)/usr/src/lib/libpmc/libpmc_json.cc/usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmcjsonconvertstd__1_ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv__throw_length_error_ZNKSt3__121__basic_string_commonILb1EE20__throw_out_of_rangeEv__throw_out_of_rangebool__basic_string_common<true>__short_mask_ZNSt3__116allocator_traitsINS_9allocatorIcEEE8allocateERS2_jallocateallocator_ZNKSt3__19allocatorIcE7addressERcaddresscharpointerreference_ZNKSt3__19allocatorIcE7addressERKcconst_pointerconst_reference_ZNSt3__19allocatorIcE8allocateEjunsigned int__uint32_t__size_tsize_t_ZNSt3__19allocatorIcE8allocateEjPKv_ZNSt3__19allocatorIcE10deallocateEPcjdeallocate_ZNKSt3__19allocatorIcE8max_sizeEvmax_sizesize_type_ZNSt3__19allocatorIcE7destroyEPcdestroy_Tpallocator<char>allocator_type_ZNSt3__116allocator_traitsINS_9allocatorIcEEE8allocateERS2_jPKv_ZNSt3__114pointer_traitsIPcE10pointer_toERcpointer_to_Bp__nat_If_Thenconditional<false, std::__1::pointer_traits<char *>::__nat, char>type_Ptrpointer_traits<char *>rebind<const void>const_void_pointer_ZNSt3__116allocator_traitsINS_9allocatorIcEEE10deallocateERS2_Pcj_ZNSt3__116allocator_traitsINS_9allocatorIcEEE8max_sizeERKS2__ZNSt3__116allocator_traitsINS_9allocatorIcEEE37select_on_container_copy_constructionERKS2_select_on_container_copy_construction_ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__allocateERS2_jPKvNS_17integral_constantIbLb1EEE__allocatevalue_ZNKSt3__117integral_constantIbLb1EEcvbEvoperator boolvalue_type_ZNKSt3__117integral_constantIbLb1EEclEvoperator()__vintegral_constant<bool, true>true_type_ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__allocateERS2_jPKvNS_17integral_constantIbLb0EEE_ZNKSt3__117integral_constantIbLb0EEcvbEv_ZNKSt3__117integral_constantIbLb0EEclEvintegral_constant<bool, false>false_type_ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__max_sizeENS_17integral_constantIbLb1EEERKS2___max_size_ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__max_sizeENS_17integral_constantIbLb0EEERKS2__ZNSt3__116allocator_traitsINS_9allocatorIcEEE39__select_on_container_copy_constructionENS_17integral_constantIbLb1EEERKS2___select_on_container_copy_construction_ZNSt3__116allocator_traitsINS_9allocatorIcEEE39__select_on_container_copy_constructionENS_17integral_constantIbLb0EEERKS2__Allocallocator_traits<std::__1::allocator<char> >__long_mask__r___value___l__cap___size___data___long__sunsigned char__lx__ARRAY_SIZE_TYPE____short__r__words__raw__rep__compressed_pair_elem__default_init_tag__value_init_tag_ZNSt3__122__compressed_pair_elemINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repELi0ELb0EE5__getEv__get_ZNKSt3__122__compressed_pair_elemINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repELi0ELb0EE5__getEvint_Idx_CanBeEmptyBase__compressed_pair_elem<std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep, 0, false>_ZNSt3__122__compressed_pair_elemINS_9allocatorIcEELi1ELb1EE5__getEv_ZNKSt3__122__compressed_pair_elemINS_9allocatorIcEELi1ELb1EE5__getEv__compressed_pair_elem<std::__1::allocator<char>, 1, true>_ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E5firstEvfirst_ZNKSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E5firstEv_ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E6secondEvsecond_ZNKSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E6secondEv_ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E4swapERS8_swap_T1_T2__compressed_pair<std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep, std::__1::allocator<char> >nposbasic_string__begin_initializer_list_ZNKSt16initializer_listIcE4sizeEvsize_ZNKSt16initializer_listIcE5beginEvbegin_ZNKSt16initializer_listIcE3endEvend_Epinitializer_list<char>~basic_string_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEcvNS_17basic_string_viewIcS2_EEEvoperator basic_string_view__data__sizebasic_string_view_ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEEaSERKS3_operator=_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5beginEvconst_iterator_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE3endEv_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6cbeginEvcbegin_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4cendEvcend_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6rbeginEvrbeginreverse_iterator<const char *>const_reverse_iterator_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4rendEvrend_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7crbeginEvcrbegin_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5crendEvcrend_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4sizeEv_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6lengthEvlength_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE8max_sizeEv_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5emptyEvempty_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEEixEjoperator[]_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE2atEjat_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5frontEvfront_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4backEvback_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4dataEvdata_ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE13remove_prefixEjremove_prefix_ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE13remove_suffixEjremove_suffix_ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE4swapERS3__ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4copyEPcjjcopy_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6substrEjjsubstr_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareES3_compare_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjS3__ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjS3_jj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEPKc_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjPKc_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findES3_jfind_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindES3_jrfind_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofES3_jfind_first_of_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofES3_jfind_last_of_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofES3_jfind_first_not_of_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEPKcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofES3_jfind_last_not_of_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEcj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEPKcjj_ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEPKcj_CharT_ZNSt3__111char_traitsIcE6assignERcRKcassignchar_type_ZNSt3__111char_traitsIcE2eqEcceq_ZNSt3__111char_traitsIcE2ltEcclt_ZNSt3__111char_traitsIcE7compareEPKcS3_j_ZNSt3__111char_traitsIcE6lengthEPKc_ZNSt3__111char_traitsIcE4findEPKcjRS2__ZNSt3__111char_traitsIcE4moveEPcPKcjmove_ZNSt3__111char_traitsIcE4copyEPcPKcj_ZNSt3__111char_traitsIcE6assignEPcjc_ZNSt3__111char_traitsIcE7not_eofEinot_eofint_type_ZNSt3__111char_traitsIcE12to_char_typeEito_char_type_ZNSt3__111char_traitsIcE11to_int_typeEcto_int_type_ZNSt3__111char_traitsIcE11eq_int_typeEiieq_int_type_ZNSt3__111char_traitsIcE3eofEveofchar_traits<char>_Traitsbasic_string_view<char, std::__1::char_traits<char> >__self_view_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSERKS5__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEOS5__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSESt16initializer_listIcE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5beginEv__wrap_iter<char *>iterator_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5beginEv__wrap_iter<const char *>_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE3endEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE3endEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6rbeginEvreverse_iterator<std::__1::__wrap_iter<char *> >reverse_iterator_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6rbeginEvreverse_iterator<std::__1::__wrap_iter<const char *> >_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4rendEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4rendEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6cbeginEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4cendEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7crbeginEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5crendEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4sizeEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6lengthEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8max_sizeEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8capacityEvcapacity_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6resizeEjcresize_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6resizeEj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7reserveEjreserve_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__resize_default_initEj__resize_default_init_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7reserveEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13shrink_to_fitEvshrink_to_fit_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5clearEvclear_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5emptyEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEixEj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEixEj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE2atEj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE2atEj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLERKS5_operator+=_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLEPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLEc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLESt16initializer_listIcE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendERKS5_append_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendERKS5_jj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__append_default_initEj__append_default_init_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendESt16initializer_listIcE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9push_backEcpush_back_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8pop_backEvpop_back_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5frontEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5frontEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4backEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4backEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignERKS5__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEOS5__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignERKS5_jj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignESt16initializer_listIcE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjRKS5_insert_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjRKS5_jj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEEc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEEjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEESt16initializer_listIcE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseEjjerase_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseENS_11__wrap_iterIPKcEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseENS_11__wrap_iterIPKcEES9__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjRKS5_replace_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjRKS5_jj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjPKc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_RKS5__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_S8_j_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_S8__ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_jc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_St16initializer_listIcE_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4copyEPcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6substrEjj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4swapERS5__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5c_strEvc_str_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13get_allocatorEvget_allocator_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofERKS5_j_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEPKcjj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareERKS5__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjRKS5__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjRKS5_jj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEPKc_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjPKc_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjPKcj_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12__invariantsEv__invariants_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__clear_and_shrinkEv__clear_and_shrink_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9__is_longEv__is_long_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7__allocEv__alloc_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7__allocEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16__set_short_sizeEj__set_short_size_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16__get_short_sizeEv__get_short_size_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE15__set_long_sizeEj__set_long_size_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE15__get_long_sizeEv__get_long_size_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE10__set_sizeEj__set_size_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__set_long_capEj__set_long_cap_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__get_long_capEv__get_long_cap_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__set_long_pointerEPc__set_long_pointer_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__get_long_pointerEv__get_long_pointer_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__get_long_pointerEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__get_short_pointerEv__get_short_pointer_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__get_short_pointerEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__get_pointerEv__get_pointer_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__get_pointerEv_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__zeroEv__zero_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE11__recommendEj__recommend_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcjj__init_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEjc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE25__init_copy_ctor_externalEPKcj__init_copy_ctor_external_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9__grow_byEjjjjjj__grow_by_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__grow_by_and_replaceEjjjjjjPKc__grow_by_and_replace_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__erase_to_endEj__erase_to_end_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE26__erase_external_with_moveEjj__erase_external_with_move_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5___copy_assign_alloc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5_NS_17integral_constantIbLb1EEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5_NS_17integral_constantIbLb0EEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__move_assignERS5_NS_17integral_constantIbLb0EEE__move_assign_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__move_assignERS5_NS_17integral_constantIbLb1EEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5___move_assign_alloc_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5_NS_17integral_constantIbLb1EEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5_NS_17integral_constantIbLb0EEE_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17__assign_externalEPKc__assign_external_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17__assign_externalEPKcj_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__assign_shortEPKcj__assign_short_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE26__invalidate_all_iteratorsEv__invalidate_all_iterators_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE27__invalidate_iterators_pastEj__invalidate_iterators_past_Allocatorbasic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >stringpl_statePMCLOG_OKPMCLOG_EOFPMCLOG_REQUIRE_DATAPMCLOG_ERRORpmclog_statepl_offsetlong long int__int64_t__off_toff_tpl_countpl_tstv_sec__int32_t__time_ttime_ttv_nseclong inttimespecpl_typePMCLOG_TYPE_CLOSELOGPMCLOG_TYPE_DROPNOTIFYPMCLOG_TYPE_INITIALIZEPMCLOG_TYPE_PMCALLOCATEPMCLOG_TYPE_PMCATTACHPMCLOG_TYPE_PMCDETACHPMCLOG_TYPE_PROCCSWPMCLOG_TYPE_PROCEXECPMCLOG_TYPE_PROCEXITPMCLOG_TYPE_PROCFORKPMCLOG_TYPE_SYSEXITPMCLOG_TYPE_USERDATAPMCLOG_TYPE_MAP_INPMCLOG_TYPE_MAP_OUTPMCLOG_TYPE_CALLCHAINPMCLOG_TYPE_PMCALLOCATEDYNPMCLOG_TYPE_THR_CREATEPMCLOG_TYPE_THR_EXITPMCLOG_TYPE_PROC_CREATEpmclog_typepl_datapl_lenpl_upl_ccpl_piduint32_tpl_tidpl_pmcidpl_cpuflagspl_cpuflags2pl_npcpl_pcu_intuintfptr_tpmclog_ev_callchainpl_clpmclog_ev_closelogpl_dnpmclog_ev_dropnotifypl_ipl_versionpl_archpl_tsc_freqlong long unsigned int__uint64_tuint64_tpl_cpuidpmclog_ev_initializepl_mi__pid_tpid_tpl_startpl_pathnamepmclog_ev_map_inpl_mopl_endpmclog_ev_map_outpl_apl_evnamepl_ratepl_eventpl_flagspmc_id_tpmclog_ev_pmcallocatepl_adpmclog_ev_pmcallocatedynpl_tpmclog_ev_pmcattachpl_dpmclog_ev_pmcdetachpl_cpl_valuepmc_value_tpmclog_ev_proccswpl_pcommpmclog_ev_proccreatepl_xpl_entryaddrpmclog_ev_procexecpl_epmclog_ev_procexitpl_fpl_oldpidpl_newpidpmclog_ev_procforkpl_sepmclog_ev_sysexitpl_tcpl_tdnamepmclog_ev_threadcreatepl_tepmclog_ev_threadexitpl_userdatapmclog_ev_userdatapmclog_evjconv_ZL11jsonconverttypenames_ZL9typenames__n_words__min_cap__alignment__uintmax_tuintmax_t_vptr$exception__vtbl_ptr_typeexception~exception_ZNKSt9exception4whatEvwhat__imp__ZNKSt3__118__libcpp_refstring15__uses_refcountEv__uses_refcount__libcpp_refstring_ZNSt3__118__libcpp_refstringaSERKS0_~__libcpp_refstring_ZNKSt3__118__libcpp_refstring5c_strEvlogic_error_ZNSt11logic_erroraSERKS_~logic_error_ZNKSt11logic_error4whatEvlength_error~length_error__intmax_tintmax_tdecltype(nullptr)nullptr_t__ptrdiff_tptrdiff_t__max_align1__max_align2long double__max_align_tmax_align_tmemcpymemmovestrcpystrncpystrcatstrncatmemcmpstrcmpstrncmpstrcollstrxfrm_Z6memchrUa9enable_ifIXLb1EEEPvijmemchr_Z6strchrUa9enable_ifIXLb1EEEPcistrchrstrcspn_Z7strpbrkUa9enable_ifIXLb1EEEPcPKcstrpbrk_Z7strrchrUa9enable_ifIXLb1EEEPcistrrchrstrspn_Z6strstrUa9enable_ifIXLb1EEEPcPKcstrstrstrtokmemsetstrerrorstrlensigned char__int8_tint8_tshort__int16_tint16_tint32_tint64_t__uint8_tuint8_tunsigned short__uint16_tuint16_t__int_least8_tint_least8_t__int_least16_tint_least16_t__int_least32_tint_least32_t__int_least64_tint_least64_t__uint_least8_tuint_least8_t__uint_least16_tuint_least16_t__uint_least32_tuint_least32_t__uint_least64_tuint_least64_t__int_fast8_tint_fast8_t__int_fast16_tint_fast16_t__int_fast32_tint_fast32_t__int_fast64_tint_fast64_t__uint_fast8_tuint_fast8_t__uint_fast16_tuint_fast16_t__uint_fast32_tuint_fast32_t__uint_fast64_tuint_fast64_t__intptr_tintptr_t__uintptr_tuintptr_tquotremdiv_tldiv_tlldiv_tatofdoubleatoiatolatollstrtodstrtoffloatstrtoldstrtolstrtollstrtoullong unsigned intstrtoullrandsrandcallocfreemallocreallocabortatexitexit_Exitgetenvsystembsearchqsort_Z3abseabslabsllabs_Z3divxxdivldivlldivmblenmbtowcwchar_twctombmbstowcswcstombsat_quick_exitquick_exit__clock_tclock_ttm_sectm_mintm_hourtm_mdaytm_montm_yeartm_wdaytm_ydaytm_isdsttm_gmtofftm_zonetmclockdifftimemktimetimeasctimectimegmtimelocaltimestrftimechronoliteralschrono_literals_p_r_w_flags_file_bf_base_size__sbuf_lbfsize_cookie_close_read_seekfpos_t_write_ub_up_ur_ubuf_nbuf_lb_blksize_offset_fl_mutexpthread_mutex_fl_ownerpthread_fl_count_orientation_mbstate__mbstate8_mbstateL__mbstate_t_flags2__sFILEFILEfclosefflushsetbufsetvbuffprintffscanfsnprintfsprintfsscanfvfprintf__builtin_va_list__va_listvfscanfvsscanfvsnprintfvsprintffgetcfgetsfputcfputsgetcputcungetcfreadfwritefgetposfseekfsetposftellrewindclearerrfeofferrorperrorfopenfreopenremoverenametmpfiletmpnamgetcharscanfvscanfprintfputcharputsvprintfisalnumisalphaisblankiscntrlisdigitisgraphislowerisprintispunctisspaceisupperisxdigittolowertoupper__ct_rune_t__wint_twint_twctrans_twctype_tiswalnumiswalphaiswblankiswcntrliswdigitiswgraphiswloweriswprintiswpunctiswspaceiswupperiswxdigitiswctypewctypetowlowertowuppertowctranswctransmbstate_tfwprintffwscanfswprintfvfwprintfvswprintfswscanfvfwscanfvswscanffgetwcfgetwsfputwcfputwsfwidegetwcputwcungetwcwcstodwcstofwcstoldwcstolwcstollwcstoulwcstoullwcscpywcsncpywcscatwcsncatwcscmpwcscollwcsncmpwcsxfrm_Z6wcschrUa9enable_ifIXLb1EEEPwwwcschr_Z7wcspbrkUa9enable_ifIXLb1EEEPwPKwwcspbrk_Z7wcsrchrUa9enable_ifIXLb1EEEPwwwcsrchr_Z6wcsstrUa9enable_ifIXLb1EEEPwPKwwcsstr_Z7wmemchrUa9enable_ifIXLb1EEEPwwjwmemchrwcscspnwcslenwcsspnwcstokwmemcmpwmemcpywmemmovewmemsetwcsftimebtowcwctobmbsinitmbrlenmbrtowcwcrtombmbsrtowcswcsrtombsgetwcharvwscanfwscanfputwcharvwprintfwprintferrxthis__a__i_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEC2Ev_ZL10startentryP9pmclog_evstartentryeveventbufbasic_string<nullptr_t>_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEC2IDnEEPKc__sz__p__cap__s1__s2__n__guess_ZNSt3__117__libcpp_allocateEjj__libcpp_allocate__align__c1__c2__str_ZNSt3__117_DeallocateCaller33__do_deallocate_handle_size_alignEPvjj__do_deallocate_handle_size_align_ZNSt3__117_DeallocateCaller28__do_deallocate_handle_alignEPvj__do_deallocate_handle_align_ZNSt3__117_DeallocateCaller27__do_deallocate_handle_sizeEPvj__do_deallocate_handle_size_ZNSt3__117_DeallocateCaller9__do_callEPv__do_call_DeallocateCaller__ptr_ZNSt3__119__libcpp_deallocateEPvjj__libcpp_deallocate_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev_Z13event_to_jsonP9pmclog_evevent_to_json_ZL12stub_to_jsonP9pmclog_evstub_to_json_ZL18initialize_to_jsonP9pmclog_evinitialize_to_json_ZL19pmcallocate_to_jsonP9pmclog_evpmcallocate_to_json_ZL17pmcattach_to_jsonP9pmclog_evpmcattach_to_json_ZL17pmcdetach_to_jsonP9pmclog_evpmcdetach_to_json_ZL15proccsw_to_jsonP9pmclog_evproccsw_to_json_ZL16procexec_to_jsonP9pmclog_evprocexec_to_json_ZL16procexit_to_jsonP9pmclog_evprocexit_to_json_ZL16procfork_to_jsonP9pmclog_evprocfork_to_json_ZL15sysexit_to_jsonP9pmclog_evsysexit_to_json_ZL16userdata_to_jsonP9pmclog_evuserdata_to_json_ZL14map_in_to_jsonP9pmclog_evmap_in_to_json_ZL15map_out_to_jsonP9pmclog_evmap_out_to_json_ZL17callchain_to_jsonP9pmclog_evcallchain_to_json_ZL22pmcallocatedyn_to_jsonP9pmclog_evpmcallocatedyn_to_json_ZL20threadcreate_to_jsonP9pmclog_evthreadcreate_to_json_ZL18threadexit_to_jsonP9pmclog_evthreadexit_to_json_ZL18proccreate_to_jsonP9pmclog_evproccreate_to_jsonstartentresultiFreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe)
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/usr/obj/usr/src/amd64.amd64/obj-lib32/usrtmp/usr/include/c++/v1/string
tmp/usr/include/c++/v1/memory
tmp/usr/include/x86/_types.h
tmp/usr/include/sys/types.h
tmp/usr/include/c++/v1/type_traits
tmp/usr/include/c++/v1/initializer_list
tmp/usr/include/c++/v1/string_view
tmp/usr/include/c++/v1/__string
tmp/usr/include/c++/v1/iosfwd
src/lib/libpmc/pmclog.htmp/usr/include/sys/_types.h
tmp/usr/include/sys/_timespec.h
tmp/usr/include/sys/pmclog.h
tmp/usr/include/sys/_stdint.h
tmp/usr/include/machine/profile.h
tmp/usr/include/sys/pmc.h
src/lib/libpmc/libpmc_json.cctmp/usr/include/c++/v1/exception
tmp/usr/include/c++/v1/stdexcept
tmp/usr/include/c++/v1/__nullptr
tmp/usr/include/c++/v1/stddef.h
tmp/usr/include/stddef.h
tmp/usr/include/c++/v1/cstddef
tmp/usr/include/c++/v1/cstring
tmp/usr/include/string.h
tmp/usr/include/c++/v1/string.h
tmp/usr/include/c++/v1/cstdint
tmp/usr/include/stdint.h
tmp/usr/include/c++/v1/cstdlib
tmp/usr/include/stdlib.h
tmp/usr/include/c++/v1/stdlib.h
tmp/usr/include/c++/v1/ctime
tmp/usr/include/time.h
tmp/usr/include/c++/v1/chrono
tmp/usr/include/stdio.h
tmp/usr/include/c++/v1/cstdio
tmp/usr/include/ctype.h
tmp/usr/include/c++/v1/cctype
tmp/usr/include/wchar.h
tmp/usr/include/c++/v1/cwctype
tmp/usr/include/wctype.h
tmp/usr/include/c++/v1/cwchar
tmp/usr/include/c++/v1/wchar.h
tmp/usr/include/err.h
tmp/usr/include/c++/v1/new
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��#�xJ5)t8�wfIg�
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#

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t

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t

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GenuineIntel-6-56v5coreGenuineIntel-6-3Dv17GenuineIntel-6-47GenuineIntel-6-4Fv10GenuineIntel-6-1Cv4GenuineIntel-6-26GenuineIntel-6-27GenuineIntel-6-36GenuineIntel-6-35GenuineIntel-6-5Cv8GenuineIntel-6-5FGenuineIntel-6-7Av1GenuineIntel-6-3Cv24GenuineIntel-6-45GenuineIntel-6-46GenuineIntel-6-3FGenuineIntel-6-3Av18GenuineIntel-6-3Ev19GenuineIntel-6-2Dv20GenuineIntel-6-57v9GenuineIntel-6-85GenuineIntel-6-1Ev2GenuineIntel-6-1FGenuineIntel-6-1AGenuineIntel-6-2EGenuineIntel-6-[4589]EGenuineIntel-6-37v13GenuineIntel-6-4DGenuineIntel-6-4CGenuineIntel-6-2Av15GenuineIntel-6-2CGenuineIntel-6-25GenuineIntel-6-2FGenuineIntel-6-55-[01234]GenuineIntel-6-55-[56789ABCDEF]GenuineIntel-6-7DGenuineIntel-6-7EGenuineIntel-6-86AuthenticAMD-23-[012][0-9A-F]AuthenticAMD-23-[[:xdigit:]]+HygonGenuine-24-00Instructions Per Cycle (per logical thread)bdwde metricsinst_retired.any / cpu_clk_unhalted.threadIPCTopDownL1Uops Per Instructionuops_retired.retire_slots / inst_retired.anyUPIPipelineRough Estimation of fraction of fetched lines bytes that were likely consumed by program instructionsmin( 1 , idq.mite_uops / ( uops_retired.retire_slots / inst_retired.any * 16 * ( icache.hit + icache.misses ) / 4.0 ) )IFetch_Line_UtilizationFrontendFraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)idq.dsb_uops / ( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops )DSB_CoverageDSB; Frontend_BandwidthCycles Per Instruction (threaded)1 / inst_retired.any / cyclesCPIPipeline;SummaryPer-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTunecpu_clk_unhalted.threadCLKSSummaryTotal issue-pipeline slots4*( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesSLOTSTotal number of retired Instructionsinst_retired.anyInstructionsInstructions Per Cycle (per physical core)inst_retired.any / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesCoreIPCSMTInstruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)uops_executed.thread / ( cpu@uops_executed.core\,cmask\=1@ / 2) if #smt_on else uops_executed.cycles_ge_1_uop_execILPPipeline;Ports_UtilizationAverage Branch Address Clear Cost (fraction of cycles)2* ( rs_events.empty_cycles - icache.ifdata_stall  - ( 14 * itlb_misses.stlb_hit + cpu@itlb_misses.walk_duration\,cmask\=1@ + 7* itlb_misses.walk_completed ) ) / rs_events.empty_endBAClear_CostUnknown_BranchesCore actual clocks when any thread is active on the physical core( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cpu_clk_unhalted.threadCORE_CLKSActual Average Latency for L1 data-cache miss demand loadsl1d_pend_miss.pending / ( mem_load_uops_retired.l1_miss + mem_load_uops_retired.hit_lfb )Load_Miss_Real_LatencyMemory_Bound;Memory_LatMemory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)l1d_pend_miss.pending / ( cpu@l1d_pend_miss.pending_cycles\,any\=1@ / 2) if #smt_on else l1d_pend_miss.pending_cyclesMLPMemory_Bound;Memory_BWUtilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7*(dtlb_store_misses.walk_completed+dtlb_load_misses.walk_completed+itlb_misses.walk_completed)) / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesPage_Walks_UtilizationTLBAverage CPU Utilizationcpu_clk_unhalted.ref_tsc / msr@tsc@CPU_UtilizationGiga Floating Point Operations Per Second( 1*( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2* fp_arith_inst_retired.128b_packed_double + 4*( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8* fp_arith_inst_retired.256b_packed_single ) / 1000000000 / duration_timeGFLOPsFLOPS;SummaryAverage Frequency Utilization relative nominal frequencycpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tscTurbo_UtilizationPowerFraction of cycles where both hardware threads were active1 - cpu_clk_thread_unhalted.one_thread_active / ( cpu_clk_thread_unhalted.ref_xclk_any / 2 ) if #smt_on else 0SMT_2T_UtilizationSMT;SummaryFraction of cycles spent in Kernel modecpu_clk_unhalted.ref_tsc:k / cpu_clk_unhalted.ref_tscKernel_UtilizationC3 residency percent per core(cstate_core@c3\-residency@ / msr@tsc@) * 100C3_Core_ResidencyC6 residency percent per core(cstate_core@c6\-residency@ / msr@tsc@) * 100C6_Core_ResidencyC7 residency percent per core(cstate_core@c7\-residency@ / msr@tsc@) * 100C7_Core_ResidencyC2 residency percent per package(cstate_pkg@c2\-residency@ / msr@tsc@) * 100C2_Pkg_ResidencyC3 residency percent per package(cstate_pkg@c3\-residency@ / msr@tsc@) * 100C3_Pkg_ResidencyC6 residency percent per package(cstate_pkg@c6\-residency@ / msr@tsc@) * 100C6_Pkg_ResidencyC7 residency percent per package(cstate_pkg@c7\-residency@ / msr@tsc@) * 100C7_Pkg_Residencyl2_rqsts.demand_data_rd_missumask=0x21,period=200003,event=0x24Demand Data Read miss L2, no rejectscacheThis event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedl2_rqsts.rfo_missumask=0x22,period=200003,event=0x24RFO requests that miss L2 cachel2_rqsts.code_rd_missumask=0x24,period=200003,event=0x24L2 cache misses when fetching instructionsl2_rqsts.all_demand_missumask=0x27,period=200003,event=0x24Demand requests that miss L2 cachel2_rqsts.l2_pf_missumask=0x30,period=200003,event=0x24L2 prefetch requests that miss L2 cacheThis event counts the number of requests from the L2 hardware prefetchers that miss L2 cachel2_rqsts.missumask=0x3f,period=200003,event=0x24All requests that miss L2 cachel2_rqsts.demand_data_rd_hitumask=0x41,period=200003,event=0x24Demand Data Read requests that hit L2 cacheThis event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are countedl2_rqsts.rfo_hitumask=0x42,period=200003,event=0x24RFO requests that hit L2 cachel2_rqsts.code_rd_hitumask=0x44,period=200003,event=0x24L2 cache hits when fetching instructions, code readsl2_rqsts.l2_pf_hitumask=0x50,period=200003,event=0x24L2 prefetch requests that hit L2 cacheThis event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new typesl2_rqsts.all_demand_data_rdumask=0xe1,period=200003,event=0x24Demand Data Read requestsThis event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedl2_rqsts.all_rfoumask=0xe2,period=200003,event=0x24RFO requests to L2 cacheThis event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesl2_rqsts.all_code_rdumask=0xe4,period=200003,event=0x24L2 code requestsThis event counts the total number of L2 code requestsl2_rqsts.all_demand_referencesumask=0xe7,period=200003,event=0x24Demand requests to L2 cachel2_rqsts.all_pfumask=0xf8,period=200003,event=0x24Requests from L2 hardware prefetchersThis event counts the total number of requests from the L2 hardware prefetchersl2_rqsts.referencesumask=0xff,period=200003,event=0x24All L2 requestsl2_demand_rqsts.wb_hitumask=0x50,period=200003,event=0x27Not rejected writebacks that hit L2 cacheThis event counts the number of WB requests that hit L2 cachelongest_lat_cache.missumask=0x41,period=100003,event=0x2eCore-originated cacheable demand requests missed L3This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUlongest_lat_cache.referenceumask=0x4f,period=100003,event=0x2eCore-originated cacheable demand requests that refer to L3This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUl1d_pend_miss.pendingumask=0x1,period=2000003,event=0x48L1D miss oustandings duration in cyclesThis event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typel1d_pend_miss.pending_cyclesumask=0x1,cmask=1,period=2000003,event=0x48Cycles with L1D load Misses outstandingThis event counts duration of L1D miss outstanding in cyclesl1d_pend_miss.pending_cycles_anyumask=0x1,any=1,cmask=1,period=2000003,event=0x48Cycles with L1D load Misses outstanding from any thread on physical corel1d_pend_miss.fb_fullumask=0x2,cmask=1,period=2000003,event=0x48Cycles a demand request was blocked due to Fill Buffers inavailabilityl1d.replacementumask=0x1,period=2000003,event=0x51L1D data line replacementsThis event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replaceoffcore_requests_outstanding.demand_data_rdumask=0x1,period=2000003,event=0x60Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point  Spec update: BDM76offcore_requests_outstanding.cycles_with_demand_data_rdumask=0x1,cmask=1,period=2000003,event=0x60Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)  Spec update: BDM76offcore_requests_outstanding.demand_data_rd_ge_6umask=0x1,cmask=6,period=2000003,event=0x60Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76offcore_requests_outstanding.demand_code_rdumask=0x2,period=2000003,event=0x60Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.demand_rfoumask=0x4,period=2000003,event=0x60Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.cycles_with_demand_rfoumask=0x4,cmask=1,period=2000003,event=0x60Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.all_data_rdumask=0x8,period=2000003,event=0x60Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.cycles_with_data_rdumask=0x8,cmask=1,period=2000003,event=0x60Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76lock_cycles.cache_lock_durationumask=0x2,period=2000003,event=0x63Cycles when L1D is lockedThis event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION)offcore_requests.demand_data_rdumask=0x1,period=100003,event=0xb0Demand Data Read requests sent to uncoreThis event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoreoffcore_requests.demand_code_rdumask=0x2,period=100003,event=0xb0Cacheable and noncachaeble code read requestsThis event counts both cacheable and noncachaeble code read requestsoffcore_requests.demand_rfoumask=0x4,period=100003,event=0xb0Demand RFO requests including regular RFOs, locks, ItoMThis event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMoffcore_requests.all_data_rdumask=0x8,period=100003,event=0xb0Demand and prefetch data readsThis event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeoffcore_requests_buffer.sq_fullumask=0x1,period=2000003,event=0xb2Offcore requests buffer cannot take more entries for this thread coreThis event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entriesoffcore_responseumask=0x1,period=100003,event=0xb7Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transactionmem_uops_retired.stlb_miss_loadsumask=0x11,period=100003,event=0xd0Retired load uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)mem_uops_retired.stlb_miss_storesumask=0x12,period=100003,event=0xd0Retired store uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)mem_uops_retired.lock_loadsumask=0x21,period=100007,event=0xd0Retired load uops with locked access. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)mem_uops_retired.split_loadsumask=0x41,period=100003,event=0xd0Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_uops_retired.split_storesumask=0x42,period=100003,event=0xd0Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_uops_retired.all_loadsumask=0x81,period=2000003,event=0xd0All retired load uops. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)mem_uops_retired.all_storesumask=0x82,period=2000003,event=0xd0This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)mem_load_uops_retired.l1_hitumask=0x1,period=2000003,event=0xd1Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)mem_load_uops_retired.l2_hitumask=0x2,period=100003,event=0xd1Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)mem_load_uops_retired.l3_hitumask=0x4,period=50021,event=0xd1Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_retired.l1_missumask=0x8,period=100003,event=0xd1Retired load uops misses in L1 cache as data sources. Uses PEBS  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)mem_load_uops_retired.l2_missumask=0x10,period=50021,event=0xd1Retired load uops with L2 cache misses as data sources. Uses PEBS  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)mem_load_uops_retired.l3_missumask=0x20,period=100007,event=0xd1Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)mem_load_uops_retired.hit_lfbumask=0x40,period=100003,event=0xd1Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)mem_load_uops_l3_hit_retired.xsnp_missumask=0x1,period=20011,event=0xd2Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_hitumask=0x2,period=20011,event=0xd2Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_hitmumask=0x4,period=20011,event=0xd2Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_noneumask=0x8,period=100003,event=0xd2Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_miss_retired.local_dramumask=0x1,period=100007,event=0xd3(null)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Supports address when precise.  Spec update: BDE70, BDM100mem_load_uops_l3_miss_retired.remote_dramumask=0x4,period=100007,event=0xd3Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)  Supports address when precise.  Spec update: BDE70mem_load_uops_l3_miss_retired.remote_hitmumask=0x10,period=100007,event=0xd3Retired load uop whose Data Source was: Remote cache HITM (Precise Event)  Supports address when precise.  Spec update: BDE70mem_load_uops_l3_miss_retired.remote_fwdumask=0x20,period=100007,event=0xd3Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)  Supports address when precise.  Spec update: BDE70l2_trans.demand_data_rdumask=0x1,period=200003,event=0xf0Demand Data Read requests that access L2 cacheThis event counts Demand Data Read requests that access L2 cache, including rejectsl2_trans.rfoumask=0x2,period=200003,event=0xf0RFO requests that access L2 cacheThis event counts Read for Ownership (RFO) requests that access L2 cachel2_trans.code_rdumask=0x4,period=200003,event=0xf0L2 cache accesses when fetching instructionsThis event counts the number of L2 cache accesses when fetching instructionsl2_trans.all_pfumask=0x8,period=200003,event=0xf0L2 or L3 HW prefetches that access L2 cacheThis event counts L2 or L3 HW prefetches that access L2 cache including rejectsl2_trans.l1d_wbumask=0x10,period=200003,event=0xf0L1D writebacks that access L2 cacheThis event counts L1D writebacks that access L2 cachel2_trans.l2_fillumask=0x20,period=200003,event=0xf0L2 fill requests that access L2 cacheThis event counts L2 fill requests that access L2 cachel2_trans.l2_wbumask=0x40,period=200003,event=0xf0L2 writebacks that access L2 cacheThis event counts L2 writebacks that access L2 cachel2_trans.all_requestsumask=0x80,period=200003,event=0xf0Transactions accessing L2 pipeThis event counts transactions that access the L2 pipe including snoops, pagewalks, and so onl2_lines_in.iumask=0x1,period=100003,event=0xf1L2 cache lines in I state filling L2This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejectsl2_lines_in.sumask=0x2,period=100003,event=0xf1L2 cache lines in S state filling L2This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejectsl2_lines_in.eumask=0x4,period=100003,event=0xf1L2 cache lines in E state filling L2This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejectsl2_lines_in.allumask=0x7,period=100003,event=0xf1L2 cache lines filling L2This event counts the number of L2 cache lines filling the L2. Counting does not cover rejectsl2_lines_out.demand_cleanumask=0x5,period=100003,event=0xf2Clean L2 cache lines evicted by demandsq_misc.split_lockumask=0x10,period=100003,event=0xf4Split locks in SQThis event counts the number of split locks in the super queueother_assists.avx_to_sseumask=0x8,period=100003,event=0xc1Number of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: BDM30floating pointThis event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30other_assists.sse_to_avxumask=0x10,period=100003,event=0xc1Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: BDM30This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30fp_arith_inst_retired.scalar_doubleumask=0x1,period=2000003,event=0xc7Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalar_singleumask=0x2,period=2000003,event=0xc7Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalarumask=0x3,period=2000003,event=0xc7Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.128b_packed_doubleumask=0x4,period=2000003,event=0xc7Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.128b_packed_singleumask=0x8,period=2000003,event=0xc7Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.256b_packed_doubleumask=0x10,period=2000003,event=0xc7Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.doubleumask=0x15,period=2000006,event=0xc7Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?fp_arith_inst_retired.256b_packed_singleumask=0x20,period=2000003,event=0xc7Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.singleumask=0x2a,period=2000005,event=0xc7Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?fp_arith_inst_retired.packedumask=0x3c,period=2000004,event=0xc7Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_assist.x87_outputumask=0x2,period=100003,event=0xcaNumber of X87 assists due to output valueThis event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalidfp_assist.x87_inputumask=0x4,period=100003,event=0xcaNumber of X87 assists due to input valueThis event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalidfp_assist.simd_outputumask=0x8,period=100003,event=0xcaNumber of SIMD FP assists due to Output valuesThis event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist interventionfp_assist.simd_inputumask=0x10,period=100003,event=0xcaNumber of SIMD FP assists due to input valuesThis event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist interventionfp_assist.anyumask=0x1e,cmask=1,period=100003,event=0xcaCycles with any input/output SSE or FP assistThis event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1idq.emptyumask=0x2,period=2000003,event=0x79Instruction Decode Queue (IDQ) empty cyclesfrontendThis counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is emptyidq.mite_uopsumask=0x4,period=2000003,event=0x79Uops delivered to Instruction Decode Queue (IDQ) from MITE pathThis event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.mite_cyclesumask=0x4,cmask=1,period=2000003,event=0x79Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQidq.dsb_uopsumask=0x8,period=2000003,event=0x79Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathThis event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.dsb_cyclesumask=0x8,cmask=1,period=2000003,event=0x79Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.ms_dsb_uopsumask=0x10,period=2000003,event=0x79Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_dsb_cyclesumask=0x10,cmask=1,period=2000003,event=0x79Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_dsb_occuredge=1,umask=0x10,cmask=1,period=2000003,event=0x79Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busyThis event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.all_dsb_cycles_4_uopsumask=0x18,cmask=4,period=2000003,event=0x79Cycles Decode Stream Buffer (DSB) is delivering 4 UopsThis event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.all_dsb_cycles_any_uopsumask=0x18,cmask=1,period=2000003,event=0x79Cycles Decode Stream Buffer (DSB) is delivering any UopThis event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.ms_mite_uopsumask=0x20,period=2000003,event=0x79Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQidq.all_mite_cycles_4_uopsumask=0x24,cmask=4,period=2000003,event=0x79Cycles MITE is delivering 4 UopsThis event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.all_mite_cycles_any_uopsumask=0x24,cmask=1,period=2000003,event=0x79Cycles MITE is delivering any UopThis event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.ms_uopsumask=0x30,period=2000003,event=0x79Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEidq.ms_cyclesumask=0x30,cmask=1,period=2000003,event=0x79Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEidq.ms_switchesedge=1,umask=0x30,cmask=1,period=2000003,event=0x79Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequenceridq.mite_all_uopsumask=0x3c,period=2000003,event=0x79icache.hitumask=0x1,period=2000003,event=0x80Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetchesThis event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetchesicache.missesumask=0x2,period=200003,event=0x80Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accessesicache.ifdata_stallumask=0x4,period=2000003,event=0x80Cycles where a code fetch is stalled due to L1 instruction-cache missThis event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit)idq_uops_not_delivered.coreumask=0x1,period=2000003,event=0x9cUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalledThis event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
 a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
 b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); 
 c. Instruction Decode Queue (IDQ) delivers four uopsidq_uops_not_delivered.cycles_0_uops_deliv.coreumask=0x1,cmask=4,period=2000003,event=0x9cCycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledThis event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4idq_uops_not_delivered.cycles_le_1_uop_deliv.coreumask=0x1,cmask=3,period=2000003,event=0x9cCycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledThis event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3idq_uops_not_delivered.cycles_le_2_uop_deliv.coreumask=0x1,cmask=2,period=2000003,event=0x9cCycles with less than 2 uops delivered by the front endidq_uops_not_delivered.cycles_le_3_uop_deliv.coreumask=0x1,cmask=1,period=2000003,event=0x9cCycles with less than 3 uops delivered by the front endidq_uops_not_delivered.cycles_fe_was_okinv=1,umask=0x1,cmask=1,period=2000003,event=0x9cCounts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FEdsb2mite_switches.penalty_cyclesumask=0x2,period=2000003,event=0xabDecode Stream Buffer (DSB)-to-MITE switch true penalty cyclesThis event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. 
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclesmisalign_mem_ref.loadsumask=0x1,period=2000003,event=0x5Speculative cache line split load uops dispatched to L1 cachememoryThis event counts speculative cache-line split load uops dispatched to the L1 cachemisalign_mem_ref.storesumask=0x2,period=2000003,event=0x5Speculative cache line split STA uops dispatched to L1 cacheThis event counts speculative cache line split store-address (STA) uops dispatched to the L1 cachetx_mem.abort_conflictumask=0x1,period=2000003,event=0x54Number of times a TSX line had a cache conflicttx_mem.abort_capacity_writeumask=0x2,period=2000003,event=0x54Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflowtx_mem.abort_hle_store_to_elided_lockumask=0x4,period=2000003,event=0x54Number of times a TSX Abort was triggered due to a non-release/commit store to locktx_mem.abort_hle_elision_buffer_not_emptyumask=0x8,period=2000003,event=0x54Number of times a TSX Abort was triggered due to commit but Lock Buffer not emptytx_mem.abort_hle_elision_buffer_mismatchumask=0x10,period=2000003,event=0x54Number of times a TSX Abort was triggered due to release/commit but data and address mismatchtx_mem.abort_hle_elision_buffer_unsupported_alignmentumask=0x20,period=2000003,event=0x54Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffertx_mem.hle_elision_buffer_fullumask=0x40,period=2000003,event=0x54Number of times we could not allocate Lock Buffertx_exec.misc1umask=0x1,period=2000003,event=0x5dCounts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional aborttx_exec.misc2umask=0x2,period=2000003,event=0x5dCounts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional regionUnfriendly TSX abort triggered by  a vzeroupper instructiontx_exec.misc3umask=0x4,period=2000003,event=0x5dCounts the number of times an instruction execution caused the transactional nest count supported to be exceededUnfriendly TSX abort triggered by a nest count that is too deeptx_exec.misc4umask=0x8,period=2000003,event=0x5dCounts the number of times a XBEGIN instruction was executed inside an HLE transactional regionRTM region detected inside HLEtx_exec.misc5umask=0x10,period=2000003,event=0x5dCounts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional regionmachine_clears.memory_orderingumask=0x2,period=100003,event=0xc3Counts the number of machine clears due to memory order conflictsThis event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load bufferhle_retired.startumask=0x1,period=2000003,event=0xc8Number of times we entered an HLE region; does not count nested transactionsNumber of times we entered an HLE region
 does not count nested transactionshle_retired.commitumask=0x2,period=2000003,event=0xc8Number of times HLE commit succeededhle_retired.abortedumask=0x4,period=2000003,event=0xc8Number of times HLE abort was triggered (PEBS) (Precise event)hle_retired.aborted_misc1umask=0x8,period=2000003,event=0xc8Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)hle_retired.aborted_misc2umask=0x10,period=2000003,event=0xc8Number of times an HLE execution aborted due to uncommon conditionsNumber of times the TSX watchdog signaled an HLE aborthle_retired.aborted_misc3umask=0x20,period=2000003,event=0xc8Number of times an HLE execution aborted due to HLE-unfriendly instructionsNumber of times a disallowed operation caused an HLE aborthle_retired.aborted_misc4umask=0x40,period=2000003,event=0xc8Number of times an HLE execution aborted due to incompatible memory typeNumber of times HLE caused a faulthle_retired.aborted_misc5umask=0x80,period=2000003,event=0xc8Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)Number of times HLE aborted and was not due to the abort conditions in subevents 3-6rtm_retired.startumask=0x1,period=2000003,event=0xc9Number of times we entered an RTM region; does not count nested transactionsNumber of times we entered an RTM region
 does not count nested transactionsrtm_retired.commitumask=0x2,period=2000003,event=0xc9Number of times RTM commit succeededrtm_retired.abortedumask=0x4,period=2000003,event=0xc9Number of times RTM abort was triggered (PEBS) (Precise event)rtm_retired.aborted_misc1umask=0x8,period=2000003,event=0xc9Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)rtm_retired.aborted_misc2umask=0x10,period=2000003,event=0xc9Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts)Number of times the TSX watchdog signaled an RTM abortrtm_retired.aborted_misc3umask=0x20,period=2000003,event=0xc9Number of times an RTM execution aborted due to HLE-unfriendly instructionsNumber of times a disallowed operation caused an RTM abortrtm_retired.aborted_misc4umask=0x40,period=2000003,event=0xc9Number of times an RTM execution aborted due to incompatible memory typeNumber of times a RTM caused a faultrtm_retired.aborted_misc5umask=0x80,period=2000003,event=0xc9Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)Number of times RTM aborted and was not due to the abort conditions in subevents 3-6mem_trans_retired.load_latency_gt_4umask=0x1,period=100003,event=0xcd,ldlat=0x4Loads with latency value being above 4  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above four  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_8umask=0x1,period=50021,event=0xcd,ldlat=0x8Loads with latency value being above 8  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above eight  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_16umask=0x1,period=20011,event=0xcd,ldlat=0x10Loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_32umask=0x1,period=100007,event=0xcd,ldlat=0x20Loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_64umask=0x1,period=2003,event=0xcd,ldlat=0x40Loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_128umask=0x1,period=1009,event=0xcd,ldlat=0x80Loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_256umask=0x1,period=503,event=0xcd,ldlat=0x100Loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_512umask=0x1,period=101,event=0xcd,ldlat=0x200Loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)cpl_cycles.ring0umask=0x1,period=2000003,event=0x5cUnhalted core cycles when the thread is in ring 0otherThis event counts the unhalted core cycles during which the thread is in the ring 0 privileged modecpl_cycles.ring0_transedge=1,umask=0x1,cmask=1,period=100007,event=0x5cNumber of intervals between processor halts while thread is in ring 0This event counts when there is a transition from ring 1,2 or 3 to ring0cpl_cycles.ring123umask=0x2,period=2000003,event=0x5cUnhalted core cycles when thread is in rings 1, 2, or 3This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3lock_cycles.split_lock_uc_lock_durationumask=0x1,period=2000003,event=0x63Cycles when L1 and L2 are locked due to UC or split lockThis event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accessevent=0xc0Instructions retired from executionpipelineThis event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. 
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. 
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructionsevent=0x3cCore cycles when the thread is not in halt stateThis event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventscpu_clk_unhalted.thread_anyevent=0x3c,any=1Core cycles when at least one thread on the physical core is not in halt statecpu_clk_unhalted.ref_tscumask=0x3,period=2000003,event=0Reference cycles when the core is not in halt stateThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. 
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseld_blocks.store_forwardumask=0x2,period=100003,event=0x3Cases when loads get true Block-on-Store blocking code preventing store forwardingThis event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
 - preceding store conflicts with the load (incomplete overlap);
 - store forwarding is impossible due to u-arch limitations;
 - preceding lock RMW operations are not forwarded;
 - store has the no-forward bit set (uncacheable/page-split/masked stores);
 - all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guideld_blocks.no_srumask=0x8,period=100003,event=0x3This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useld_blocks_partial.address_aliasumask=0x1,period=100003,event=0x7False dependencies in MOB due to partial compareThis event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedint_misc.recovery_cyclesumask=0x3,cmask=1,period=2000003,event=0xdCore cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clearint_misc.recovery_cycles_anyumask=0x3,any=1,cmask=1,period=2000003,event=0xdCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)int_misc.rat_stall_cyclesumask=0x8,period=2000003,event=0xdCycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the threadThis event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another threaduops_issued.anyumask=0x1,period=2000003,event=0xeUops that Resource Allocation Table (RAT) issues to Reservation Station (RS)This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS)uops_issued.stall_cyclesinv=1,umask=0x1,cmask=1,period=2000003,event=0xeCycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the threadThis event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threaduops_issued.flags_mergeumask=0x10,period=2000003,event=0xeNumber of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-archNumber of flags-merge uops being allocated. Such uops considered perf sensitive
 added by GSR u-archuops_issued.slow_leaumask=0x20,period=2000003,event=0xeNumber of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notuops_issued.single_mulumask=0x40,period=2000003,event=0xeNumber of Multiply packed/scalar single precision uops allocatedarith.fpu_div_activeumask=0x1,period=2000003,event=0x14Cycles when divider is busy executing divide operationsThis event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executedcpu_clk_unhalted.thread_pumask=0x0,period=2000003,event=0x3cThread cycles when thread is not in halt stateThis is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock timecpu_clk_unhalted.thread_p_anyumask=0x0,any=1,period=2000003,event=0x3ccpu_clk_thread_unhalted.ref_xclkumask=0x1,period=2000003,event=0x3cReference cycles when the thread is unhalted (counts at 100 MHz rate)This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhzcpu_clk_thread_unhalted.ref_xclk_anyumask=0x1,any=1,period=2000003,event=0x3cReference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)cpu_clk_unhalted.ref_xclkcpu_clk_unhalted.ref_xclk_anycpu_clk_thread_unhalted.one_thread_activeumask=0x2,period=2000003,event=0x3cCount XClk pulses when this thread is unhalted and the other thread is haltedcpu_clk_unhalted.one_thread_activeload_hit_pre.sw_pfumask=0x1,period=100003,event=0x4cNot software-prefetch load dispatches that hit FB allocated for software prefetchThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructionsload_hit_pre.hw_pfumask=0x2,period=100003,event=0x4cNot software-prefetch load dispatches that hit FB allocated for hardware prefetchThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetchmove_elimination.int_eliminatedumask=0x1,period=1000003,event=0x58Number of integer Move Elimination candidate uops that were eliminatedmove_elimination.simd_eliminatedumask=0x2,period=1000003,event=0x58Number of SIMD Move Elimination candidate uops that were eliminatedmove_elimination.int_not_eliminatedumask=0x4,period=1000003,event=0x58Number of integer Move Elimination candidate uops that were not eliminatedmove_elimination.simd_not_eliminatedumask=0x8,period=1000003,event=0x58Number of SIMD Move Elimination candidate uops that were not eliminatedrs_events.empty_cyclesumask=0x1,period=2000003,event=0x5eCycles when Reservation Station (RS) is empty for the threadThis event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesrs_events.empty_endedge=1,inv=1,umask=0x1,cmask=1,period=200003,event=0x5eCounts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issuesild_stall.lcpumask=0x1,period=2000003,event=0x87Stalls caused by changing prefix length of the instructionThis event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunkbr_inst_exec.nontaken_conditionalumask=0x41,period=200003,event=0x88Not taken macro-conditional branchesThis event counts not taken macro-conditional branch instructionsbr_inst_exec.taken_conditionalumask=0x81,period=200003,event=0x88Taken speculative and retired macro-conditional branchesThis event counts taken speculative and retired macro-conditional branch instructionsbr_inst_exec.taken_direct_jumpumask=0x82,period=200003,event=0x88Taken speculative and retired macro-conditional branch instructions excluding calls and indirectsThis event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branchesbr_inst_exec.taken_indirect_jump_non_call_retumask=0x84,period=200003,event=0x88Taken speculative and retired indirect branches excluding calls and returnsThis event counts taken speculative and retired indirect branches excluding calls and return branchesbr_inst_exec.taken_indirect_near_returnumask=0x88,period=200003,event=0x88Taken speculative and retired indirect branches with return mnemonicThis event counts taken speculative and retired indirect branches that have a return mnemonicbr_inst_exec.taken_direct_near_callumask=0x90,period=200003,event=0x88Taken speculative and retired direct near callsThis event counts taken speculative and retired direct near callsbr_inst_exec.taken_indirect_near_callumask=0xa0,period=200003,event=0x88Taken speculative and retired indirect callsThis event counts taken speculative and retired indirect calls including both register and memory indirectbr_inst_exec.all_conditionalumask=0xc1,period=200003,event=0x88Speculative and retired macro-conditional branchesThis event counts both taken and not taken speculative and retired macro-conditional branch instructionsbr_inst_exec.all_direct_jmpumask=0xc2,period=200003,event=0x88Speculative and retired macro-unconditional branches excluding calls and indirectsThis event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirectsbr_inst_exec.all_indirect_jump_non_call_retumask=0xc4,period=200003,event=0x88Speculative and retired indirect branches excluding calls and returnsThis event counts both taken and not taken speculative and retired indirect branches excluding calls and return branchesbr_inst_exec.all_indirect_near_returnumask=0xc8,period=200003,event=0x88Speculative and retired indirect return branchesThis event counts both taken and not taken speculative and retired indirect branches that have a return mnemonicbr_inst_exec.all_direct_near_callumask=0xd0,period=200003,event=0x88Speculative and retired direct near callsThis event counts both taken and not taken speculative and retired direct near callsbr_inst_exec.all_branchesumask=0xff,period=200003,event=0x88Speculative and retired  branchesThis event counts both taken and not taken speculative and retired branch instructionsbr_misp_exec.nontaken_conditionalumask=0x41,period=200003,event=0x89Not taken speculative and retired mispredicted macro conditional branchesThis event counts not taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.taken_conditionalumask=0x81,period=200003,event=0x89Taken speculative and retired mispredicted macro conditional branchesThis event counts taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.taken_indirect_jump_non_call_retumask=0x84,period=200003,event=0x89Taken speculative and retired mispredicted indirect branches excluding calls and returnsThis event counts taken speculative and retired mispredicted indirect branches excluding calls and returnsbr_misp_exec.taken_return_nearumask=0x88,period=200003,event=0x89Taken speculative and retired mispredicted indirect branches with return mnemonicThis event counts taken speculative and retired mispredicted indirect branches that have a return mnemonicbr_misp_exec.taken_indirect_near_callumask=0xa0,period=200003,event=0x89Taken speculative and retired mispredicted indirect callsbr_misp_exec.all_conditionalumask=0xc1,period=200003,event=0x89Speculative and retired mispredicted macro conditional branchesThis event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.all_indirect_jump_non_call_retumask=0xc4,period=200003,event=0x89Mispredicted indirect branches excluding calls and returnsThis event counts both taken and not taken mispredicted indirect branches excluding calls and returnsbr_misp_exec.all_branchesumask=0xff,period=200003,event=0x89This event counts both taken and not taken speculative and retired mispredicted branch instructionsuop_dispatches_cancelled.simd_prfumask=0x3,period=2000003,event=0xa0Micro-op dispatches cancelled due to insufficient SIMD physical register file read portsThis event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more informationuops_dispatched_port.port_0umask=0x1,period=2000003,event=0xa1Cycles per thread when uops are executed in port 0This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0uops_executed_port.port_0_coreumask=0x1,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 0uops_executed_port.port_0uops_dispatched_port.port_1umask=0x2,period=2000003,event=0xa1Cycles per thread when uops are executed in port 1This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1uops_executed_port.port_1_coreumask=0x2,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 1uops_executed_port.port_1uops_dispatched_port.port_2umask=0x4,period=2000003,event=0xa1Cycles per thread when uops are executed in port 2This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2uops_executed_port.port_2_coreumask=0x4,any=1,period=2000003,event=0xa1Cycles per core when uops are dispatched to port 2uops_executed_port.port_2uops_dispatched_port.port_3umask=0x8,period=2000003,event=0xa1Cycles per thread when uops are executed in port 3This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3uops_executed_port.port_3_coreumask=0x8,any=1,period=2000003,event=0xa1Cycles per core when uops are dispatched to port 3uops_executed_port.port_3uops_dispatched_port.port_4umask=0x10,period=2000003,event=0xa1Cycles per thread when uops are executed in port 4This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4uops_executed_port.port_4_coreumask=0x10,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 4uops_executed_port.port_4uops_dispatched_port.port_5umask=0x20,period=2000003,event=0xa1Cycles per thread when uops are executed in port 5This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5uops_executed_port.port_5_coreumask=0x20,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 5uops_executed_port.port_5uops_dispatched_port.port_6umask=0x40,period=2000003,event=0xa1Cycles per thread when uops are executed in port 6This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6uops_executed_port.port_6_coreumask=0x40,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 6uops_executed_port.port_6uops_dispatched_port.port_7umask=0x80,period=2000003,event=0xa1Cycles per thread when uops are executed in port 7This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7uops_executed_port.port_7_coreumask=0x80,any=1,period=2000003,event=0xa1Cycles per core when uops are dispatched to port 7uops_executed_port.port_7resource_stalls.anyumask=0x1,period=2000003,event=0xa2Resource-related stall cyclesThis event counts resource-related stall cycles. Reasons for stalls can be as follows:
 - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
 - *any* u-arch structure got empty (like INT/SIMD FreeLists)
 - FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.rsumask=0x4,period=2000003,event=0xa2Cycles stalled due to no eligible RS entry availableThis event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.sbumask=0x8,period=2000003,event=0xa2Cycles stalled due to no store buffers available. (not including draining form sync)This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.robumask=0x10,period=2000003,event=0xa2Cycles stalled due to re-order buffer fullThis event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front endcycle_activity.cycles_l2_pendingumask=0x1,cmask=1,period=2000003,event=0xa3Cycles while L2 cache miss demand load is outstandingCounts number of cycles the CPU has at least one pending  demand* load request missing the L2 cachecycle_activity.cycles_l2_misscycle_activity.cycles_ldm_pendingumask=0x2,cmask=2,period=2000003,event=0xa3Cycles while memory subsystem has an outstanding loadCounts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)cycle_activity.cycles_mem_anycycle_activity.cycles_no_executeumask=0x4,cmask=4,period=2000003,event=0xa3This event increments by 1 for every cycle where there was no execute for this threadCounts number of cycles nothing is executed on any execution portcycle_activity.stalls_totalTotal execution stallscycle_activity.stalls_l2_pendingumask=0x5,cmask=5,period=2000003,event=0xa3Execution stalls while L2 cache miss demand load is outstandingCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demandscycle_activity.stalls_l2_misscycle_activity.stalls_ldm_pendingumask=0x6,cmask=6,period=2000003,event=0xa3Execution stalls while memory subsystem has an outstanding loadCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand load requestcycle_activity.stalls_mem_anycycle_activity.cycles_l1d_pendingumask=0x8,cmask=8,period=2000003,event=0xa3Cycles while L1 cache miss demand load is outstandingCounts number of cycles the CPU has at least one pending  demand load request missing the L1 data cachecycle_activity.cycles_l1d_misscycle_activity.stalls_l1d_pendingumask=0xc,cmask=12,period=2000003,event=0xa3Execution stalls while L1 cache miss demand load is outstandingCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cachecycle_activity.stalls_l1d_misslsd.uopsumask=0x1,period=2000003,event=0xa8Number of Uops delivered by the LSDlsd.cycles_4_uopsumask=0x1,cmask=4,period=2000003,event=0xa8Cycles 4 Uops delivered by the LSD, but didn't come from the decoderlsd.cycles_activeumask=0x1,cmask=1,period=2000003,event=0xa8Cycles Uops delivered by the LSD, but didn't come from the decoderuops_executed.threadumask=0x1,period=2000003,event=0xb1Counts the number of uops to be executed per-thread each cycleNumber of uops to be executed per-thread each cycleuops_executed.stall_cyclesinv=1,umask=0x1,cmask=1,period=2000003,event=0xb1Counts number of cycles no uops were dispatched to be executed on this threadThis event counts cycles during which no uops were dispatched from the Reservation Station (RS) per threaduops_executed.cycles_ge_1_uop_execumask=0x1,cmask=1,period=2000003,event=0xb1Cycles where at least 1 uop was executed per-threaduops_executed.cycles_ge_2_uops_execumask=0x1,cmask=2,period=2000003,event=0xb1Cycles where at least 2 uops were executed per-threaduops_executed.cycles_ge_3_uops_execumask=0x1,cmask=3,period=2000003,event=0xb1Cycles where at least 3 uops were executed per-threaduops_executed.cycles_ge_4_uops_execumask=0x1,cmask=4,period=2000003,event=0xb1Cycles where at least 4 uops were executed per-threaduops_executed.coreumask=0x2,period=2000003,event=0xb1Number of uops executed on the coreNumber of uops executed from any threaduops_executed.core_cycles_ge_1umask=0x2,cmask=1,period=2000003,event=0xb1Cycles at least 1 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_2umask=0x2,cmask=2,period=2000003,event=0xb1Cycles at least 2 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_3umask=0x2,cmask=3,period=2000003,event=0xb1Cycles at least 3 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_4umask=0x2,cmask=4,period=2000003,event=0xb1Cycles at least 4 micro-op is executed from any thread on physical coreuops_executed.core_cycles_noneinv=1,umask=0x2,period=2000003,event=0xb1Cycles with no micro-ops executed from any thread on physical coreinst_retired.any_pNumber of instructions retired. General Counter   - architectural event  Spec update: BDM61This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: BDM61inst_retired.prec_distumask=0x1,period=2000003,event=0xc0Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: BDM11, BDM55 (Must be precise)This is a precise version (that is, uses PEBS) of the event that counts instructions retired  Spec update: BDM11, BDM55 (Must be precise)inst_retired.x87umask=0x2,period=2000003,event=0xc0FP operations  retired. X87 FP operations that have no exceptions:This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingother_assists.any_wb_assistumask=0x40,period=100003,event=0xc1Number of times any microcode assist is invoked by HW upon uop writebackuops_retired.allumask=0x1,period=2000003,event=0xc2Actually retired uops. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight  Supports address when precise (Precise event)uops_retired.stall_cyclesinv=1,umask=0x1,cmask=1,period=2000003,event=0xc2Cycles without actually retired uopsThis event counts cycles without actually retired uopsuops_retired.total_cyclesinv=1,umask=0x1,cmask=10,period=2000003,event=0xc2Cycles with less than 10 actually retired uopsNumber of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired eventuops_retired.retire_slotsumask=0x2,period=2000003,event=0xc2Retirement slots used. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event)machine_clears.cyclesumask=0x1,period=2000003,event=0xc3Cycles there was a Nuke. Account for both thread-specific and All Thread NukesThis event counts both thread-specific (TS) and all-thread (AT) nukesmachine_clears.countedge=1,umask=0x1,cmask=1,period=100003,event=0xc3Number of machine clears (nukes) of any typemachine_clears.smcumask=0x4,period=100003,event=0xc3Self-modifying code (SMC) detectedThis event counts self-modifying code (SMC) detected, which causes a machine clearmachine_clears.maskmovumask=0x20,period=100003,event=0xc3This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a faultbr_inst_retired.all_branchesumask=0x0,period=400009,event=0xc4All (macro) branch instructions retiredThis event counts all (macro) branch instructions retiredbr_inst_retired.conditionalumask=0x1,period=400009,event=0xc4Conditional branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event)br_inst_retired.near_callumask=0x2,period=100007,event=0xc4Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event)br_inst_retired.near_call_r3Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)br_inst_retired.all_branches_pebsumask=0x4,period=400009,event=0xc4All (macro) branch instructions retired. (Precise Event - PEBS)  Spec update: BDW98 (Must be precise)This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: BDW98 (Must be precise)br_inst_retired.near_returnumask=0x8,period=100007,event=0xc4Return instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event)br_inst_retired.not_takenumask=0x10,period=400009,event=0xc4Not taken branch instructions retiredThis event counts not taken branch instructions retiredbr_inst_retired.near_takenumask=0x20,period=400009,event=0xc4Taken branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event)br_inst_retired.far_branchumask=0x40,period=100007,event=0xc4Far branch instructions retired  Spec update: BDW98This event counts far branch instructions retired  Spec update: BDW98br_misp_retired.all_branchesumask=0x0,period=400009,event=0xc5All mispredicted macro branch instructions retiredThis event counts all mispredicted macro branch instructions retiredbr_misp_retired.conditionalumask=0x1,period=400009,event=0xc5Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event)br_misp_retired.all_branches_pebsumask=0x4,period=400009,event=0xc5Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise)This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise)br_misp_retired.retumask=0x8,period=100007,event=0xc5This event counts the number of mispredicted ret instructions retired.(Precise Event)This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retiredbr_misp_retired.near_takenumask=0x20,period=400009,event=0xc5number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)rob_misc_events.lbr_insertsumask=0x20,period=2000003,event=0xccCount cases of saving new LBRThis event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT registerbaclears.anyumask=0x1f,period=100003,event=0xe6Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endunc_c_clockticksevent=0Uncore cache clock ticks. Unit: uncore_cbox uncore cacheuncore_cbox1unc_c_llc_lookup.anyumask=0x11,event=0x34,filter_state=0x1All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox 64Bytesunc_c_llc_victims.m_stateumask=0x1,event=0x37M line evictions from LLC (writebacks to memory). Unit: uncore_cbox llc_misses.data_readumask=0x3,event=0x35,filter_opc=0x182LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.uncacheableumask=0x3,event=0x35,filter_opc=0x187LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_readumask=0x3,event=0x35,filter_opc=0x187,filter_nc=1MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_writeumask=0x3,event=0x35,filter_opc=0x18f,filter_nc=1MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.rfo_llc_prefetchumask=0x3,event=0x35,filter_opc=0x190LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.code_llc_prefetchumask=0x3,event=0x35,filter_opc=0x191LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.data_llc_prefetchumask=0x3,event=0x35,filter_opc=0x192LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_readumask=0x3,event=0x35,filter_opc=0x19eLLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_writeumask=0x3,event=0x35,filter_opc=0x1c8ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_non_snoop_writeumask=0x3,event=0x35,filter_opc=0x1c8,filter_tid=0x3ePCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.pcie_ns_partial_writeumask=0x1,event=0x35,filter_opc=0x180,filter_tid=0x3ePCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.code_llc_prefetchumask=0x1,event=0x35,filter_opc=0x181L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_fullumask=0x1,event=0x35,filter_opc=0x18cStreaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_partialumask=0x1,event=0x35,filter_opc=0x18dStreaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_readumask=0x1,event=0x35,filter_opc=0x19ePCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_writeumask=0x1,event=0x35,filter_opc=0x1c8,filter_tid=0x3ePCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_c_tor_occupancy.llc_data_readumask=0x3,event=0x36,filter_opc=0x182Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_requests.readsumask=0x3,event=0x1read requests to home agent. Unit: uncore_ha uncore_haunc_h_requests.reads_localumask=0x1,event=0x1read requests to local home agent. Unit: uncore_ha unc_h_requests.reads_remoteumask=0x2,event=0x1read requests to remote home agent. Unit: uncore_ha unc_h_requests.writesumask=0xC,event=0x1write requests to home agent. Unit: uncore_ha unc_h_requests.writes_localumask=0x4,event=0x1write requests to local home agent. Unit: uncore_ha unc_h_requests.writes_remoteumask=0x8,event=0x1write requests to remote home agent. Unit: uncore_ha unc_h_snoop_resp.rspcnflctumask=0x40,event=0x21Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha unc_h_snoop_resp.rsp_fwd_wbumask=0x20,event=0x21M line forwarded from remote cache along with writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rspifwdumask=0x4,event=0x21M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rspsumask=0x2,event=0x21Shared line response from remote cache. Unit: uncore_ha unc_h_snoop_resp.rspsfwdumask=0x8,event=0x21Shared line forwarded from remote cache. Unit: uncore_ha llc_misses.mem_readumask=0x3,event=0x4read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc uncore memoryuncore_imcllc_misses.mem_writeumask=0xC,event=0x4write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc unc_m_dclockticksMemory controller clock ticks. Unit: uncore_imc unc_m_power_channel_ppdevent=0x85Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc (unc_m_power_channel_ppd / unc_m_dclockticks) * 100.power_channel_ppd %unc_m_power_critical_throttle_cyclesevent=0x86Cycles all ranks are in critical thermal throttle. Unit: uncore_imc (unc_m_power_critical_throttle_cycles / unc_m_dclockticks) * 100.power_critical_throttle_cycles %unc_m_power_self_refreshevent=0x43Cycles Memory is in self refresh power mode. Unit: uncore_imc (unc_m_power_self_refresh / unc_m_dclockticks) * 100.power_self_refresh %unc_m_pre_count.page_missumask=0x1,event=0x2Pre-charges due to page misses. Unit: uncore_imc unc_m_pre_count.rdumask=0x4,event=0x2Pre-charge for reads. Unit: uncore_imc unc_m_pre_count.wrumask=0x8,event=0x2Pre-charge for writes. Unit: uncore_imc unc_p_clockticksPCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu uncore poweruncore_pcuunc_p_power_state_occupancy.cores_c0event=0x80,occ_sel=1This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100.power_state_occupancy.cores_c0 %unc_p_power_state_occupancy.cores_c3event=0x80,occ_sel=2This is an occupancy event that tracks the number of cores that are in C3.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c3 / unc_p_clockticks) * 100.power_state_occupancy.cores_c3 %unc_p_power_state_occupancy.cores_c6event=0x80,occ_sel=3This is an occupancy event that tracks the number of cores that are in C6.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c6 / unc_p_clockticks) * 100.power_state_occupancy.cores_c6 %unc_p_prochot_external_cyclesevent=0xaCounts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu (unc_p_prochot_external_cycles / unc_p_clockticks) * 100.prochot_external_cycles %unc_p_freq_max_limit_thermal_cyclesevent=0x4Counts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_limit_thermal_cycles / unc_p_clockticks) * 100.freq_max_limit_thermal_cycles %unc_p_freq_max_os_cyclesevent=0x6Counts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_os_cycles / unc_p_clockticks) * 100.freq_max_os_cycles %unc_p_freq_max_power_cyclesevent=0x5Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_power_cycles / unc_p_clockticks) * 100.freq_max_power_cycles %unc_p_freq_trans_cyclesevent=0x74Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_trans_cycles / unc_p_clockticks) * 100.freq_trans_cycles %dtlb_load_misses.miss_causes_a_walkumask=0x1,period=100003,event=0x8Load misses in all DTLB levels that cause page walks  Spec update: BDM69virtual memoryThis event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69dtlb_load_misses.walk_completed_4kumask=0x2,period=2000003,event=0x8Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_completed_2m_4mumask=0x4,period=2000003,event=0x8Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_completed_1gumask=0x8,period=2000003,event=0x8Load miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_completedumask=0xe,period=100003,event=0x8Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size  Spec update: BDM69dtlb_load_misses.walk_durationumask=0x10,period=2000003,event=0x8Cycles when PMH is busy with page walks  Spec update: BDM69This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69dtlb_load_misses.stlb_hit_4kumask=0x20,period=2000003,event=0x8Load misses that miss the  DTLB and hit the STLB (4K)dtlb_load_misses.stlb_hit_2mumask=0x40,period=2000003,event=0x8Load misses that miss the  DTLB and hit the STLB (2M)dtlb_load_misses.stlb_hitumask=0x60,period=2000003,event=0x8Load operations that miss the first DTLB level but hit the second and do not cause page walksdtlb_store_misses.miss_causes_a_walkumask=0x1,period=100003,event=0x49Store misses in all DTLB levels that cause page walks  Spec update: BDM69This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69dtlb_store_misses.walk_completed_4kumask=0x2,period=100003,event=0x49Store miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_completed_2m_4mumask=0x4,period=100003,event=0x49Store misses in all DTLB levels that cause completed page walks (2M/4M)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_completed_1gumask=0x8,period=100003,event=0x49Store misses in all DTLB levels that cause completed page walks (1G)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_completedumask=0xe,period=100003,event=0x49Store misses in all DTLB levels that cause completed page walks  Spec update: BDM69dtlb_store_misses.walk_durationumask=0x10,period=100003,event=0x49dtlb_store_misses.stlb_hit_4kumask=0x20,period=100003,event=0x49Store misses that miss the  DTLB and hit the STLB (4K)dtlb_store_misses.stlb_hit_2mumask=0x40,period=100003,event=0x49Store misses that miss the  DTLB and hit the STLB (2M)dtlb_store_misses.stlb_hitumask=0x60,period=100003,event=0x49Store operations that miss the first TLB level but hit the second and do not cause page walksept.walk_cyclesumask=0x10,period=2000003,event=0x4fCycle count for an Extended Page table walkThis event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB cachesitlb_misses.miss_causes_a_walkumask=0x1,period=100003,event=0x85Misses at all ITLB levels that cause page walks  Spec update: BDM69itlb_misses.walk_completed_4kumask=0x2,period=100003,event=0x85Code miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69itlb_misses.walk_completed_2m_4mumask=0x4,period=100003,event=0x85Code miss in all TLB levels causes a page walk that completes. (2M/4M)  Spec update: BDM69itlb_misses.walk_completed_1gumask=0x8,period=100003,event=0x85Store miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69itlb_misses.walk_completedumask=0xe,period=100003,event=0x85Misses in all ITLB levels that cause completed page walks  Spec update: BDM69itlb_misses.walk_durationumask=0x10,period=100003,event=0x85itlb_misses.stlb_hit_4kumask=0x20,period=100003,event=0x85Core misses that miss the  DTLB and hit the STLB (4K)itlb_misses.stlb_hit_2mumask=0x40,period=100003,event=0x85Code misses that miss the  DTLB and hit the STLB (2M)itlb_misses.stlb_hitumask=0x60,period=100003,event=0x85Operations that miss the first ITLB level but hit the second and do not cause any page walksitlb.itlb_flushumask=0x1,period=100007,event=0xaeFlushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pagesThis event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)page_walker_loads.dtlb_l1umask=0x11,period=2000003,event=0xbcNumber of DTLB page walker hits in the L1+FB  Spec update: BDM69, BDM98page_walker_loads.dtlb_l2umask=0x12,period=2000003,event=0xbcNumber of DTLB page walker hits in the L2  Spec update: BDM69, BDM98page_walker_loads.dtlb_l3umask=0x14,period=2000003,event=0xbcNumber of DTLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98page_walker_loads.dtlb_memoryumask=0x18,period=2000003,event=0xbcNumber of DTLB page walker hits in Memory  Spec update: BDM69, BDM98page_walker_loads.itlb_l1umask=0x21,period=2000003,event=0xbcNumber of ITLB page walker hits in the L1+FB  Spec update: BDM69, BDM98page_walker_loads.itlb_l2umask=0x22,period=2000003,event=0xbcNumber of ITLB page walker hits in the L2  Spec update: BDM69, BDM98page_walker_loads.itlb_l3umask=0x24,period=2000003,event=0xbcNumber of ITLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98tlb_flush.dtlb_threadumask=0x1,period=100007,event=0xbdDTLB flush attempts of the thread-specific entriesThis event counts the number of DTLB flush attempts of the thread-specific entriestlb_flush.stlb_anyumask=0x20,period=100007,event=0xbdSTLB flush attemptsThis event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on)This category represents fraction of slots where the processor's Frontend undersupplies its Backendbdw metricsThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Boundidq_uops_not_delivered.core / (4 * cycles)Frontend_BoundTopdownL1This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPUidq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))Frontend_Bound_SMTTopdownL1_SMTThis category represents fraction of slots wasted due to incorrect speculationsThis category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)Bad_SpeculationThis category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))Bad_Speculation_SMTThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the BackendThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound1 - ( (idq_uops_not_delivered.core / (4 * cycles)) + (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)) + (uops_retired.retire_slots / (4 * cycles)) )Backend_BoundThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU1 - ( (idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) )Backend_Bound_SMTThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retiredThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoideduops_retired.retire_slots / (4 * cycles)RetiringThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPUuops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))Retiring_SMTInstructions Per Cycle (per Logical Processor)Pipeline;RetireInstruction per taken branchinst_retired.any / br_inst_retired.near_takenIpTBBranches;Fetch_BW;PGOBranch instructions per taken branchbr_inst_retired.all_branches / br_inst_retired.near_takenBpTBBranches;PGORough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructionsmin( 1 , idq.mite_uops / ( (uops_retired.retire_slots / inst_retired.any) * 16 * ( icache.hit + icache.misses ) / 4.0 ) )PGO;IcMissFraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)idq.dsb_uops / (( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) )DSB;Fetch_BWCycles Per Instruction (per Logical Processor)1 / (inst_retired.any / cycles)Per-Logical Processor actual clocks when the Logical Processor is activeTotal issue-pipeline slots (per-Physical Core)4 * cycles4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))SLOTS_SMTTopDownL1_SMTInstructions per Load (lower number means higher occurance rate)inst_retired.any / mem_uops_retired.all_loadsIpLInstruction_TypeInstructions per Store (lower number means higher occurance rate)inst_retired.any / mem_uops_retired.all_storesIpSInstructions per Branch (lower number means higher occurance rate)inst_retired.any / br_inst_retired.all_branchesIpBBranches;Instruction_TypeInstruction per (near) call (lower number means higher occurance rate)inst_retired.any / br_inst_retired.near_callIpCallBranchesinst_retired.any / cyclesinst_retired.any / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))CoreIPC_SMTFloating Point Operations Per Cycle(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / cyclesFLOPcFLOPS(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))FLOPc_SMTFLOPS_SMTuops_executed.thread / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else uops_executed.cycles_ge_1_uop_exec)Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branchesBranch_Misprediction_CostBrMispredicts( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branchesBranch_Misprediction_Cost_SMTBrMispredicts_SMTNumber of Instructions per non-speculative Branch Misprediction (JEClear)inst_retired.any / br_misp_retired.all_branchesIpMispredictCore actual clocks when any Logical Processor is active on the Physical Core( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )Actual Average Latency for L1 data-cache miss demand loads (in core cycles)Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)l1d_pend_miss.pending / l1d_pend_miss.pending_cycles( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / cycles( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Page_Walks_Utilization_SMTTLB_SMTAverage data fill bandwidth to the L1 data cache [GB / sec]64 * l1d.replacement / 1000000000 / duration_timeL1D_Cache_Fill_BWMemory_BWAverage data fill bandwidth to the L2 cache [GB / sec]64 * l2_lines_in.all / 1000000000 / duration_timeL2_Cache_Fill_BWAverage per-core data fill bandwidth to the L3 cache [GB / sec]64 * longest_lat_cache.miss / 1000000000 / duration_timeL3_Cache_Fill_BWL1 cache true misses per kilo instruction for retired demand loads1000 * mem_load_uops_retired.l1_miss / inst_retired.anyL1MPKICache_MissesL2 cache true misses per kilo instruction for retired demand loads1000 * mem_load_uops_retired.l2_miss / inst_retired.anyL2MPKIL2 cache misses per kilo instruction for all request types (including speculative)1000 * l2_rqsts.miss / inst_retired.anyL2MPKI_AllL2 cache hits per kilo instruction for all request types (including speculative)1000 * ( l2_rqsts.references - l2_rqsts.miss ) / inst_retired.anyL2HPKI_AllL3 cache true misses per kilo instruction for retired demand loads1000 * mem_load_uops_retired.l3_miss / inst_retired.anyL3MPKI( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / 1000000000 ) / duration_timeFraction of cycles where both hardware Logical Processors were activeAverage external Memory Bandwidth Use for reads and writes [GB / sec]64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000DRAM_BW_Useumask=0xc1,period=200003,event=0x24Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cacheumask=0xc2,period=200003,event=0x24umask=0xc4,period=200003,event=0x24umask=0xd0,period=200003,event=0x24umask=0x1,period=2000003,cmask=1,event=0x48umask=0x1,any=1,period=2000003,cmask=1,event=0x48umask=0x2,period=2000003,cmask=1,event=0x48umask=0x1,period=2000003,cmask=1,event=0x60umask=0x1,period=2000003,cmask=6,event=0x60umask=0x4,period=2000003,cmask=1,event=0x60umask=0x8,period=2000003,cmask=1,event=0x60Retired load uops with locked access. (Precise Event - PEBS)  Spec update: BDM35.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path  Spec update: BDM35.  Supports address when precise (Precise event)Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)  Spec update: BDM35.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache  Spec update: BDM35.  Supports address when precise (Precise event)Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Spec update: BDM100.  Supports address when precise (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Spec update: BDM100, BDE70.  Supports address when precise (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Spec update: BDM100.  Supports address when precise (Precise event)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Spec update: BDM100.  Supports address when precise (Precise event)Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Spec update: BDM100.  Supports address when precise (Precise event)Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Spec update: BDM100.  Supports address when precise (Precise event)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Spec update: BDE70, BDM100.  Supports address when preciseoffcore_response.demand_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010001Counts demand data reads have any response typeoffcore_response.demand_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020001Counts demand data readsoffcore_response.demand_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020001offcore_response.demand_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020001offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020001offcore_response.demand_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020001offcore_response.demand_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020001offcore_response.demand_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0001offcore_response.demand_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0001offcore_response.demand_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0001offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0001offcore_response.demand_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0001offcore_response.demand_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0001offcore_response.demand_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010002Counts all demand data writes (RFOs) have any response typeoffcore_response.demand_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0002Counts all demand data writes (RFOs)offcore_response.demand_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0002offcore_response.demand_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0002offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0002offcore_response.demand_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0002offcore_response.demand_rfo.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0002offcore_response.demand_code_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010004Counts all demand code reads have any response typeoffcore_response.demand_code_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020004Counts all demand code readsoffcore_response.demand_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020004offcore_response.demand_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020004offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020004offcore_response.demand_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020004offcore_response.demand_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020004offcore_response.demand_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0004offcore_response.demand_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0004offcore_response.demand_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0004offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0004offcore_response.demand_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0004offcore_response.demand_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0004offcore_response.corewb.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010008Counts writebacks (modified to exclusive) have any response typeoffcore_response.corewb.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020008Counts writebacks (modified to exclusive)offcore_response.corewb.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020008offcore_response.corewb.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020008offcore_response.corewb.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020008offcore_response.corewb.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020008offcore_response.corewb.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020008offcore_response.corewb.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0008offcore_response.corewb.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0008offcore_response.corewb.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0008offcore_response.corewb.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0008offcore_response.corewb.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0008offcore_response.corewb.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0008offcore_response.pf_l2_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010010Counts prefetch (that bring data to L2) data reads have any response typeoffcore_response.pf_l2_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020010Counts prefetch (that bring data to L2) data readsoffcore_response.pf_l2_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020010offcore_response.pf_l2_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020010offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020010offcore_response.pf_l2_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020010offcore_response.pf_l2_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020010offcore_response.pf_l2_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0010offcore_response.pf_l2_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0010offcore_response.pf_l2_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010020Counts all prefetch (that bring data to L2) RFOs have any response typeoffcore_response.pf_l2_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020020Counts all prefetch (that bring data to L2) RFOsoffcore_response.pf_l2_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020020offcore_response.pf_l2_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020020offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020020offcore_response.pf_l2_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020020offcore_response.pf_l2_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020020offcore_response.pf_l2_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0020offcore_response.pf_l2_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0020offcore_response.pf_l2_rfo.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0020offcore_response.pf_l2_code_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010040Counts all prefetch (that bring data to LLC only) code reads have any response typeoffcore_response.pf_l2_code_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020040Counts all prefetch (that bring data to LLC only) code readsoffcore_response.pf_l2_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020040offcore_response.pf_l2_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020040offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020040offcore_response.pf_l2_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020040offcore_response.pf_l2_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020040offcore_response.pf_l2_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0040offcore_response.pf_l2_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0040offcore_response.pf_l3_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010080Counts all prefetch (that bring data to LLC only) data reads have any response typeoffcore_response.pf_l3_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020080Counts all prefetch (that bring data to LLC only) data readsoffcore_response.pf_l3_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020080offcore_response.pf_l3_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020080offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020080offcore_response.pf_l3_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020080offcore_response.pf_l3_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020080offcore_response.pf_l3_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0080offcore_response.pf_l3_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0080offcore_response.pf_l3_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010100Counts all prefetch (that bring data to LLC only) RFOs have any response typeoffcore_response.pf_l3_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020100Counts all prefetch (that bring data to LLC only) RFOsoffcore_response.pf_l3_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020100offcore_response.pf_l3_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020100offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020100offcore_response.pf_l3_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020100offcore_response.pf_l3_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020100offcore_response.pf_l3_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0100offcore_response.pf_l3_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0100offcore_response.pf_l3_rfo.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0100offcore_response.pf_l3_code_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010200Counts prefetch (that bring data to LLC only) code reads have any response typeoffcore_response.pf_l3_code_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020200Counts prefetch (that bring data to LLC only) code readsoffcore_response.pf_l3_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020200offcore_response.pf_l3_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020200offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020200offcore_response.pf_l3_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020200offcore_response.pf_l3_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020200offcore_response.pf_l3_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0200offcore_response.pf_l3_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0200offcore_response.other.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000018000Counts any other requests have any response typeoffcore_response.other.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080028000Counts any other requestsoffcore_response.other.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100028000offcore_response.other.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200028000offcore_response.other.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400028000offcore_response.other.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000028000offcore_response.other.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80028000offcore_response.other.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C8000offcore_response.other.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C8000offcore_response.other.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C8000offcore_response.other.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C8000offcore_response.other.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C8000offcore_response.other.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8000offcore_response.all_pf_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010090Counts all prefetch data reads have any response typeoffcore_response.all_pf_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020090Counts all prefetch data readsoffcore_response.all_pf_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020090offcore_response.all_pf_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020090offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020090offcore_response.all_pf_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020090offcore_response.all_pf_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020090offcore_response.all_pf_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0090offcore_response.all_pf_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0090offcore_response.all_pf_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0090offcore_response.all_pf_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010120Counts prefetch RFOs have any response typeoffcore_response.all_pf_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020120Counts prefetch RFOsoffcore_response.all_pf_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020120offcore_response.all_pf_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020120offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020120offcore_response.all_pf_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020120offcore_response.all_pf_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020120offcore_response.all_pf_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0120offcore_response.all_pf_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0120offcore_response.all_pf_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0120offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0120offcore_response.all_pf_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0120offcore_response.all_pf_rfo.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0120offcore_response.all_pf_code_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010240Counts all prefetch code reads have any response typeoffcore_response.all_pf_code_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020240Counts all prefetch code readsoffcore_response.all_pf_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020240offcore_response.all_pf_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020240offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020240offcore_response.all_pf_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020240offcore_response.all_pf_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020240offcore_response.all_pf_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0240offcore_response.all_pf_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0240offcore_response.all_pf_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0240offcore_response.all_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010091Counts all demand & prefetch data reads have any response typeoffcore_response.all_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020091Counts all demand & prefetch data readsoffcore_response.all_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020091offcore_response.all_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020091offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020091offcore_response.all_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020091offcore_response.all_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020091offcore_response.all_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0091offcore_response.all_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0091offcore_response.all_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0091offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0091offcore_response.all_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0091offcore_response.all_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0091offcore_response.all_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010122Counts all demand & prefetch RFOs have any response typeoffcore_response.all_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020122Counts all demand & prefetch RFOsoffcore_response.all_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020122offcore_response.all_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020122offcore_response.all_rfo.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020122offcore_response.all_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020122offcore_response.all_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020122offcore_response.all_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0122offcore_response.all_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0122offcore_response.all_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0122offcore_response.all_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0122offcore_response.all_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0122offcore_response.all_rfo.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0122Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event)  Spec update: BDM30This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event)  Spec update: BDM30This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)output - Numeric Overflow, Numeric Underflow, Inexact Result  (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalidinput - Invalid Operation, Denormal Operand, SNaN Operand  (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalidSSE* FP micro-code assist when output value is invalid. (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist interventionAny input SSE* FP Assist -   (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist interventionumask=0x1e,period=100003,cmask=1,event=0xcaCounts any FP_ASSIST umask was incrementing   (Precise Event)This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBSumask=0x4,period=2000003,cmask=1,event=0x79umask=0x8,period=2000003,cmask=1,event=0x79umask=0x10,period=2000003,cmask=1,event=0x79umask=0x10,edge=1,period=2000003,cmask=1,event=0x79umask=0x18,period=2000003,cmask=4,event=0x79umask=0x18,period=2000003,cmask=1,event=0x79umask=0x24,period=2000003,cmask=4,event=0x79umask=0x24,period=2000003,cmask=1,event=0x79umask=0x30,period=2000003,cmask=1,event=0x79umask=0x30,edge=1,period=2000003,cmask=1,event=0x79This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
 a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
 b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); 
 c. Instruction Decode Queue (IDQ) delivers four uopsumask=0x1,period=2000003,cmask=4,event=0x9cumask=0x1,period=2000003,cmask=3,event=0x9cumask=0x1,period=2000003,cmask=2,event=0x9cumask=0x1,period=2000003,cmask=1,event=0x9cinv=1,umask=0x1,period=2000003,cmask=1,event=0x9cThis event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. 
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cyclesRandomly selected loads with latency value being above 4  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above four  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 8  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above eight  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020001offcore_response.demand_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000001offcore_response.demand_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000001offcore_response.demand_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000001offcore_response.demand_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000001offcore_response.demand_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000001offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000001offcore_response.demand_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0002offcore_response.demand_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000002offcore_response.demand_rfo.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000002offcore_response.demand_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000002offcore_response.demand_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000002offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000002offcore_response.demand_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020004offcore_response.demand_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000004offcore_response.demand_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000004offcore_response.demand_code_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000004offcore_response.demand_code_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000004offcore_response.demand_code_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000004offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000004offcore_response.corewb.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020008offcore_response.corewb.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0008offcore_response.corewb.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000008offcore_response.corewb.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000008offcore_response.corewb.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000008offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000008offcore_response.corewb.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000008offcore_response.corewb.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000008offcore_response.corewb.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000008offcore_response.corewb.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000008offcore_response.corewb.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000008offcore_response.corewb.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000008offcore_response.corewb.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000008offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020010offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000010offcore_response.pf_l2_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000010offcore_response.pf_l2_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000010offcore_response.pf_l2_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000010offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000010offcore_response.pf_l2_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020020offcore_response.pf_l2_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000020offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000020offcore_response.pf_l2_rfo.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000020offcore_response.pf_l2_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000020offcore_response.pf_l2_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000020offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000020offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020040offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000040offcore_response.pf_l2_code_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000040offcore_response.pf_l2_code_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000040offcore_response.pf_l2_code_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000040offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000040offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020080offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000080offcore_response.pf_l3_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000080offcore_response.pf_l3_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000080offcore_response.pf_l3_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000080offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000080offcore_response.pf_l3_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020100offcore_response.pf_l3_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000100offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000100offcore_response.pf_l3_rfo.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000100offcore_response.pf_l3_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000100offcore_response.pf_l3_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000100offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000100offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020200offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000200offcore_response.pf_l3_code_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000200offcore_response.pf_l3_code_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000200offcore_response.pf_l3_code_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000200offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000200offcore_response.other.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000028000offcore_response.other.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C8000offcore_response.other.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084008000offcore_response.other.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104008000offcore_response.other.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204008000offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404008000offcore_response.other.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004008000offcore_response.other.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004008000offcore_response.other.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84008000offcore_response.other.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC008000offcore_response.other.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C008000offcore_response.other.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C008000offcore_response.other.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C008000offcore_response.all_pf_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020090offcore_response.all_pf_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000090offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000090offcore_response.all_pf_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000090offcore_response.all_pf_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000090offcore_response.all_pf_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000090offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000090offcore_response.all_pf_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020120offcore_response.all_pf_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000120offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000120offcore_response.all_pf_rfo.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000120offcore_response.all_pf_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000120offcore_response.all_pf_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000120offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000120offcore_response.all_pf_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020240offcore_response.all_pf_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000240offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000240offcore_response.all_pf_code_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000240offcore_response.all_pf_code_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000240offcore_response.all_pf_code_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000240offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000240offcore_response.all_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020091offcore_response.all_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0091offcore_response.all_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000091offcore_response.all_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000091offcore_response.all_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000091offcore_response.all_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000091offcore_response.all_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000091offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000091offcore_response.all_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020122offcore_response.all_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0122offcore_response.all_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000122offcore_response.all_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000122offcore_response.all_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000122offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000122offcore_response.all_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000122offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000122offcore_response.all_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000122offcore_response.all_rfo.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000122offcore_response.all_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000122offcore_response.all_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000122offcore_response.all_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000122umask=0x1,edge=1,period=100007,cmask=1,event=0x5cumask=0x3,period=2000003,cmask=1,event=0xdumask=0x3,any=1,period=2000003,cmask=1,event=0xdinv=1,umask=0x1,period=2000003,cmask=1,event=0xeinv=1,umask=0x1,edge=1,period=200003,cmask=1,event=0x5eThis event counts resource-related stall cyclesumask=0x1,period=2000003,cmask=1,event=0xa3umask=0x2,period=2000003,cmask=2,event=0xa3umask=0x4,period=2000003,cmask=4,event=0xa3umask=0x5,period=2000003,cmask=5,event=0xa3umask=0x6,period=2000003,cmask=6,event=0xa3umask=0x8,period=2000003,cmask=8,event=0xa3umask=0xc,period=2000003,cmask=12,event=0xa3umask=0x1,period=2000003,cmask=4,event=0xa8umask=0x1,period=2000003,cmask=1,event=0xa8inv=1,umask=0x1,period=2000003,cmask=1,event=0xb1umask=0x1,period=2000003,cmask=1,event=0xb1umask=0x1,period=2000003,cmask=2,event=0xb1umask=0x1,period=2000003,cmask=3,event=0xb1umask=0x1,period=2000003,cmask=4,event=0xb1umask=0x2,period=2000003,cmask=1,event=0xb1umask=0x2,period=2000003,cmask=2,event=0xb1umask=0x2,period=2000003,cmask=3,event=0xb1umask=0x2,period=2000003,cmask=4,event=0xb1FP operations  retired. X87 FP operations that have no exceptions: (Precise event)This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling (Precise event)inv=1,umask=0x1,period=2000003,cmask=1,event=0xc2Cycles no executable uops retired (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uopsinv=1,umask=0x1,period=2000003,cmask=10,event=0xc2Number of cycles using always true condition applied to  PEBS uops retired event (Precise event)Number of cycles using always true condition (uops_ret < 16) applied to  PEBS uops retired event (Precise event)umask=0x1,edge=1,period=100003,cmask=1,event=0xc3Counts all not taken macro branch instructions retired. (Precise Event)This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retiredCounts the number of far branch instructions retired.(Precise Event)  Spec update: BDW98This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired  Spec update: BDW98unc_cbo_xsnp_response.miss_xcoreumask=0x41,event=0x22Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor coreuncoreA cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor coreunc_cbo_xsnp_response.miss_evictionumask=0x81,event=0x22Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which misses in some processor coreA cross-core snoop resulted from L3 Eviction which misses in some processor coreunc_cbo_xsnp_response.hit_xcoreumask=0x44,event=0x22Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor coreA cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor coreunc_cbo_xsnp_response.hitm_xcoreumask=0x48,event=0x22Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor coreA cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor coreunc_cbo_cache_lookup.read_mumask=0x11,event=0x34Unit: uncore_cbox L3 Lookup read request that access cache and found line in M-stateL3 Lookup read request that access cache and found line in M-stateunc_cbo_cache_lookup.write_mumask=0x21,event=0x34Unit: uncore_cbox L3 Lookup write request that access cache and found line in M-stateL3 Lookup write request that access cache and found line in M-stateunc_cbo_cache_lookup.any_mumask=0x81,event=0x34Unit: uncore_cbox L3 Lookup any request that access cache and found line in M-stateL3 Lookup any request that access cache and found line in M-stateunc_cbo_cache_lookup.read_iumask=0x18,event=0x34Unit: uncore_cbox L3 Lookup read request that access cache and found line in I-stateL3 Lookup read request that access cache and found line in I-stateunc_cbo_cache_lookup.any_iumask=0x88,event=0x34Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-stateL3 Lookup any request that access cache and found line in I-stateunc_cbo_cache_lookup.read_mesiumask=0x1f,event=0x34Unit: uncore_cbox L3 Lookup read request that access cache and found line in any MESI-stateL3 Lookup read request that access cache and found line in any MESI-stateunc_cbo_cache_lookup.write_mesiumask=0x2f,event=0x34Unit: uncore_cbox L3 Lookup write request that access cache and found line in MESI-stateL3 Lookup write request that access cache and found line in MESI-stateunc_cbo_cache_lookup.any_mesiumask=0x8f,event=0x34Unit: uncore_cbox L3 Lookup any request that access cache and found line in MESI-stateL3 Lookup any request that access cache and found line in MESI-stateunc_cbo_cache_lookup.any_esumask=0x86,event=0x34Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-stateL3 Lookup any request that access cache and found line in E or S-stateunc_cbo_cache_lookup.read_esumask=0x16,event=0x34Unit: uncore_cbox L3 Lookup read request that access cache and found line in E or S-stateL3 Lookup read request that access cache and found line in E or S-stateunc_cbo_cache_lookup.write_esumask=0x26,event=0x34Unit: uncore_cbox L3 Lookup write request that access cache and found line in E or S-stateL3 Lookup write request that access cache and found line in E or S-stateunc_arb_trk_occupancy.allumask=0x01,event=0x80Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficEach cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficuncore_arbunc_arb_trk_occupancy.drd_directumask=0x02,event=0x80Unit: uncore_arb Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal caseEach cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal caseunc_arb_trk_requests.allumask=0x01,event=0x81Unit: uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent trafficTotal number of Core outgoing entries allocated. Accounts for Coherent and non-coherent trafficunc_arb_trk_requests.drd_directumask=0x02,event=0x81Unit: uncore_arb Number of Core coherent Data Read entries allocated in DirectData modeNumber of Core coherent Data Read entries allocated in DirectData modeunc_arb_trk_requests.writesumask=0x20,event=0x81Unit: uncore_arb Number of Writes allocated - any write transactions: full/partials writes and evictionsNumber of Writes allocated - any write transactions: full/partials writes and evictionsunc_arb_coh_trk_requests.allumask=0x01,event=0x84Unit: uncore_arb Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etcNumber of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etcunc_arb_trk_occupancy.cycles_with_any_requestumask=0x01,cmask=1,event=0x80Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCunc_clock.socketumask=0x01,event=0Unit: uncore_ncu This 48-bit fixed counter counts the UCLK cyclesThis 48-bit fixed counter counts the UCLK cyclesuncore_ncubdx metrics( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * cycles )( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) )( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_timeAverage latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time )DRAM_Read_LatencyMemory_LatAverage number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetchescbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@DRAM_Parallel_ReadsSocket actual clocks when any core is active on that socketcbox_0@event\=0x0@Socket_CLKSRetired load uops that miss the STLB  Supports address when precise (Precise event)This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)Retired store uops that miss the STLB  Supports address when precise (Precise event)This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)Retired load uops with locked access  Supports address when precise.  Spec update: BDM35 (Precise event)This event counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)Retired load uops that split across a cacheline boundary  Supports address when precise (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)Retired store uops that split across a cacheline boundary  Supports address when precise (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)All retired load uops  Supports address when precise (Precise event)This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)All retired store uops  Supports address when precise (Precise event)This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)Retired load uops with L1 cache hits as data sources  Supports address when precise (Precise event)This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: BDM35 (Precise event)This event counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops misses in L1 cache as data sources  Supports address when precise (Precise event)This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise (Precise event)This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70 (Precise event)Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: BDE70 (Precise event)Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: BDE70 (Precise event)offcore_response.all_requests.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8FFFCounts all requests hit in the L3offcore_response.all_reads.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C07F7Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C07F7Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_code_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0244Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_rfo.llc_hit.hitm_other_coreCounts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_rfo.llc_hit.hit_other_core_no_fwdCounts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_data_rd.llc_hit.hitm_other_coreCounts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_data_rd.llc_hit.hit_other_core_no_fwdCounts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_code_rd.llc_hit.any_responseCounts prefetch (that bring data to LLC only) code reads hit in the L3offcore_response.pf_llc_rfo.llc_hit.any_responseCounts all prefetch (that bring data to LLC only) RFOs hit in the L3offcore_response.demand_rfo.llc_hit.hitm_other_coreCounts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_rfo.llc_hit.any_responseCounts all demand data writes (RFOs) hit in the L3Number of times HLE abort was triggered (Precise event)Number of times RTM abort was triggered (Precise event)Number of times RTM abort was triggered  (Precise event)offcore_response.all_requests.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC08FFFCounts all requests miss in the L3offcore_response.all_reads.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_reads.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_reads.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dramoffcore_response.all_reads.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x06040007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dramoffcore_response.all_reads.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC007F7Counts all data/code/rfo reads (demand & prefetch) miss in the L3offcore_response.all_code_rd.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000244Counts all demand & prefetch code reads miss the L3 and the data is returned from local dramoffcore_response.all_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00244Counts all demand & prefetch code reads miss in the L3offcore_response.all_rfo.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000122Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dramoffcore_response.all_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00122Counts all demand & prefetch RFOs miss in the L3offcore_response.all_data_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC00091Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_data_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00091Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_data_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC00091Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dramoffcore_response.all_data_rd.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000091Counts all demand & prefetch data reads miss the L3 and the data is returned from local dramoffcore_response.all_data_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00091Counts all demand & prefetch data reads miss in the L3offcore_response.pf_llc_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00200Counts prefetch (that bring data to LLC only) code reads miss in the L3offcore_response.pf_llc_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00100Counts all prefetch (that bring data to LLC only) RFOs miss in the L3offcore_response.demand_rfo.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00002Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cacheoffcore_response.demand_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00002Counts all demand data writes (RFOs) miss in the L3Actually retired uops  Supports address when precise (Precise event)This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight  Supports address when precise (Precise event)Retirement slots used (Precise event)This event counts the number of retirement slots used (Precise event)Conditional branch instructions retired (Precise event)This event counts conditional branch instructions retired (Precise event)Direct and indirect near call instructions retired (Precise event)This event counts both direct and indirect near call instructions retired (Precise event)Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)Return instructions retired (Precise event)This event counts return instructions retired (Precise event)Taken branch instructions retired (Precise event)This event counts taken branch instructions retired (Precise event)Mispredicted conditional branch instructions retired (Precise event)This event counts mispredicted conditional branch instructions retired (Precise event)This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event)This event counts mispredicted return instructions retired (Precise event)number of near branch instructions retired that were mispredicted and taken (Precise event)Number of near branch instructions retired that were mispredicted and taken (Precise event)unc_q_clockticksevent=0x14QPI clock ticks. Unit: uncore_qpi uncore interconnectuncore_qpiqpi_data_bandwidth_txumask=0x2,event=0Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi 8Bytesqpi_ctl_bandwidth_txumask=0x4,event=0Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi unc_m_clockticks(unc_m_power_channel_ppd / unc_m_clockticks) * 100.(unc_m_power_critical_throttle_cycles / unc_m_clockticks) * 100.(unc_m_power_self_refresh / unc_m_clockticks) * 100.l2_ads.selfumask=0x40,period=200000,event=0x21Cycles L2 address bus is in usel2_dbus_busy.selfumask=0x40,period=200000,event=0x22Cycles the L2 cache data bus is busyl2_dbus_busy_rd.selfumask=0x40,period=200000,event=0x23Cycles the L2 transfers data to the corel2_lines_in.self.anyumask=0x70,period=200000,event=0x24L2 cache missesl2_lines_in.self.demandumask=0x40,period=200000,event=0x24l2_lines_in.self.prefetchumask=0x50,period=200000,event=0x24l2_m_lines_in.selfumask=0x40,period=200000,event=0x25L2 cache line modificationsl2_lines_out.self.anyumask=0x70,period=200000,event=0x26L2 cache lines evictedl2_lines_out.self.demandumask=0x40,period=200000,event=0x26l2_lines_out.self.prefetchumask=0x50,period=200000,event=0x26l2_m_lines_out.self.anyumask=0x70,period=200000,event=0x27Modified lines evicted from the L2 cachel2_m_lines_out.self.demandumask=0x40,period=200000,event=0x27l2_m_lines_out.self.prefetchumask=0x50,period=200000,event=0x27l2_ifetch.self.e_stateumask=0x44,period=200000,event=0x28L2 cacheable instruction fetch requestsl2_ifetch.self.i_stateumask=0x41,period=200000,event=0x28l2_ifetch.self.m_stateumask=0x48,period=200000,event=0x28l2_ifetch.self.s_stateumask=0x42,period=200000,event=0x28l2_ifetch.self.mesiumask=0x4f,period=200000,event=0x28l2_ld.self.any.e_stateumask=0x74,period=200000,event=0x29L2 cache readsl2_ld.self.any.i_stateumask=0x71,period=200000,event=0x29l2_ld.self.any.m_stateumask=0x78,period=200000,event=0x29l2_ld.self.any.s_stateumask=0x72,period=200000,event=0x29l2_ld.self.any.mesiumask=0x7f,period=200000,event=0x29l2_ld.self.demand.e_stateumask=0x44,period=200000,event=0x29l2_ld.self.demand.i_stateumask=0x41,period=200000,event=0x29l2_ld.self.demand.m_stateumask=0x48,period=200000,event=0x29l2_ld.self.demand.s_stateumask=0x42,period=200000,event=0x29l2_ld.self.demand.mesiumask=0x4f,period=200000,event=0x29l2_ld.self.prefetch.e_stateumask=0x54,period=200000,event=0x29l2_ld.self.prefetch.i_stateumask=0x51,period=200000,event=0x29l2_ld.self.prefetch.m_stateumask=0x58,period=200000,event=0x29l2_ld.self.prefetch.s_stateumask=0x52,period=200000,event=0x29l2_ld.self.prefetch.mesiumask=0x5f,period=200000,event=0x29l2_st.self.e_stateumask=0x44,period=200000,event=0x2aL2 store requestsl2_st.self.i_stateumask=0x41,period=200000,event=0x2al2_st.self.m_stateumask=0x48,period=200000,event=0x2al2_st.self.s_stateumask=0x42,period=200000,event=0x2al2_st.self.mesiumask=0x4f,period=200000,event=0x2al2_lock.self.e_stateumask=0x44,period=200000,event=0x2bL2 locked accessesl2_lock.self.i_stateumask=0x41,period=200000,event=0x2bl2_lock.self.m_stateumask=0x48,period=200000,event=0x2bl2_lock.self.s_stateumask=0x42,period=200000,event=0x2bl2_lock.self.mesiumask=0x4f,period=200000,event=0x2bl2_data_rqsts.self.e_stateumask=0x44,period=200000,event=0x2cAll data requests from the L1 data cachel2_data_rqsts.self.i_stateumask=0x41,period=200000,event=0x2cl2_data_rqsts.self.m_stateumask=0x48,period=200000,event=0x2cl2_data_rqsts.self.s_stateumask=0x42,period=200000,event=0x2cl2_data_rqsts.self.mesiumask=0x4f,period=200000,event=0x2cl2_ld_ifetch.self.e_stateumask=0x44,period=200000,event=0x2dAll read requests from L1 instruction and data cachesl2_ld_ifetch.self.i_stateumask=0x41,period=200000,event=0x2dl2_ld_ifetch.self.m_stateumask=0x48,period=200000,event=0x2dl2_ld_ifetch.self.s_stateumask=0x42,period=200000,event=0x2dl2_ld_ifetch.self.mesiumask=0x4f,period=200000,event=0x2dl2_rqsts.self.any.e_stateumask=0x74,period=200000,event=0x2eL2 cache requestsl2_rqsts.self.any.i_stateumask=0x71,period=200000,event=0x2el2_rqsts.self.any.m_stateumask=0x78,period=200000,event=0x2el2_rqsts.self.any.s_stateumask=0x72,period=200000,event=0x2el2_rqsts.self.any.mesiumask=0x7f,period=200000,event=0x2el2_rqsts.self.demand.e_stateumask=0x44,period=200000,event=0x2el2_rqsts.self.demand.m_stateumask=0x48,period=200000,event=0x2el2_rqsts.self.demand.s_stateumask=0x42,period=200000,event=0x2el2_rqsts.self.prefetch.e_stateumask=0x54,period=200000,event=0x2el2_rqsts.self.prefetch.i_stateumask=0x51,period=200000,event=0x2el2_rqsts.self.prefetch.m_stateumask=0x58,period=200000,event=0x2el2_rqsts.self.prefetch.s_stateumask=0x52,period=200000,event=0x2el2_rqsts.self.prefetch.mesiumask=0x5f,period=200000,event=0x2el2_rqsts.self.demand.i_stateumask=0x41,period=200000,event=0x2eL2 cache demand requests from this core that missed the L2l2_rqsts.self.demand.mesiumask=0x4f,period=200000,event=0x2eL2 cache demand requests from this corel2_reject_busq.self.any.e_stateumask=0x74,period=200000,event=0x30Rejected L2 cache requestsl2_reject_busq.self.any.i_stateumask=0x71,period=200000,event=0x30l2_reject_busq.self.any.m_stateumask=0x78,period=200000,event=0x30l2_reject_busq.self.any.s_stateumask=0x72,period=200000,event=0x30l2_reject_busq.self.any.mesiumask=0x7f,period=200000,event=0x30l2_reject_busq.self.demand.e_stateumask=0x44,period=200000,event=0x30l2_reject_busq.self.demand.i_stateumask=0x41,period=200000,event=0x30l2_reject_busq.self.demand.m_stateumask=0x48,period=200000,event=0x30l2_reject_busq.self.demand.s_stateumask=0x42,period=200000,event=0x30l2_reject_busq.self.demand.mesiumask=0x4f,period=200000,event=0x30l2_reject_busq.self.prefetch.e_stateumask=0x54,period=200000,event=0x30l2_reject_busq.self.prefetch.i_stateumask=0x51,period=200000,event=0x30l2_reject_busq.self.prefetch.m_stateumask=0x58,period=200000,event=0x30l2_reject_busq.self.prefetch.s_stateumask=0x52,period=200000,event=0x30l2_reject_busq.self.prefetch.mesiumask=0x5f,period=200000,event=0x30l2_no_req.selfumask=0x40,period=200000,event=0x32Cycles no L2 cache requests are pendingl1d_cache.ldumask=0xa1,period=2000000,event=0x40L1 Cacheable Data Readsl1d_cache.stumask=0xa2,period=2000000,event=0x40L1 Cacheable Data Writesl1d_cache.all_refumask=0x83,period=2000000,event=0x40L1 Data reads and writesl1d_cache.all_cache_refumask=0xa3,period=2000000,event=0x40L1 Data Cacheable reads and writesl1d_cache.replumask=0x8,period=200000,event=0x40L1 Data line replacementsl1d_cache.replmumask=0x48,period=200000,event=0x40Modified cache lines allocated in the L1 data cachel1d_cache.evictumask=0x10,period=200000,event=0x40Modified cache lines evicted from the L1 data cachemem_load_retired.l2_hitumask=0x1,period=200000,event=0xcbRetired loads that hit the L2 cache (precise event)mem_load_retired.l2_missumask=0x2,period=10000,event=0xcbRetired loads that miss the L2 cachex87_comp_ops_exe.any.sumask=0x1,period=2000000,event=0x10Floating point computational micro-ops executedx87_comp_ops_exe.any.arumask=0x81,period=2000000,event=0x10Floating point computational micro-ops retired (Must be precise)x87_comp_ops_exe.fxch.sumask=0x2,period=2000000,event=0x10FXCH uops executedx87_comp_ops_exe.fxch.arumask=0x82,period=2000000,event=0x10FXCH uops retired (Must be precise)fp_assist.sumask=0x1,period=10000,event=0x11Floating point assistsfp_assist.arumask=0x81,period=10000,event=0x11Floating point assists for retired operationssimd_uops_exec.sumask=0x0,period=2000000,event=0xb0SIMD micro-ops executed (excluding stores)simd_uops_exec.arumask=0x80,period=2000000,event=0xb0SIMD micro-ops retired (excluding stores) (Must be precise)simd_sat_uop_exec.sumask=0x0,period=2000000,event=0xb1SIMD saturated arithmetic micro-ops executedsimd_sat_uop_exec.arumask=0x80,period=2000000,event=0xb1SIMD saturated arithmetic micro-ops retiredsimd_uop_type_exec.mul.sumask=0x1,period=2000000,event=0xb3SIMD packed multiply micro-ops executedsimd_uop_type_exec.mul.arumask=0x81,period=2000000,event=0xb3SIMD packed multiply micro-ops retiredsimd_uop_type_exec.shift.sumask=0x2,period=2000000,event=0xb3SIMD packed shift micro-ops executedsimd_uop_type_exec.shift.arumask=0x82,period=2000000,event=0xb3SIMD packed shift micro-ops retiredsimd_uop_type_exec.pack.sumask=0x4,period=2000000,event=0xb3SIMD packed micro-ops executedsimd_uop_type_exec.pack.arumask=0x84,period=2000000,event=0xb3SIMD packed micro-ops retiredsimd_uop_type_exec.unpack.sumask=0x8,period=2000000,event=0xb3SIMD unpacked micro-ops executedsimd_uop_type_exec.unpack.arumask=0x88,period=2000000,event=0xb3SIMD unpacked micro-ops retiredsimd_uop_type_exec.logical.sumask=0x10,period=2000000,event=0xb3SIMD packed logical micro-ops executedsimd_uop_type_exec.logical.arumask=0x90,period=2000000,event=0xb3SIMD packed logical micro-ops retiredsimd_uop_type_exec.arithmetic.sumask=0x20,period=2000000,event=0xb3SIMD packed arithmetic micro-ops executedsimd_uop_type_exec.arithmetic.arumask=0xa0,period=2000000,event=0xb3SIMD packed arithmetic micro-ops retiredsimd_inst_retired.packed_singleumask=0x1,period=2000000,event=0xc7Retired Streaming SIMD Extensions (SSE) packed-single instructionssimd_inst_retired.scalar_singleumask=0x2,period=2000000,event=0xc7Retired Streaming SIMD Extensions (SSE) scalar-single instructionssimd_inst_retired.scalar_doubleumask=0x8,period=2000000,event=0xc7Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionssimd_inst_retired.vectorumask=0x10,period=2000000,event=0xc7Retired Streaming SIMD Extensions 2 (SSE2) vector instructionssimd_comp_inst_retired.packed_singleumask=0x1,period=2000000,event=0xcaRetired computational Streaming SIMD Extensions (SSE) packed-single instructionssimd_comp_inst_retired.scalar_singleumask=0x2,period=2000000,event=0xcaRetired computational Streaming SIMD Extensions (SSE) scalar-single instructionssimd_comp_inst_retired.scalar_doubleumask=0x8,period=2000000,event=0xcaRetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionssimd_assistumask=0x0,period=100000,event=0xcdSIMD assists invokedsimd_instr_retiredumask=0x0,period=2000000,event=0xceSIMD Instructions retiredsimd_sat_instr_retiredumask=0x0,period=2000000,event=0xcfSaturated arithmetic instructions retiredicache.accessesumask=0x3,period=200000,event=0x80Instruction fetchesumask=0x1,period=200000,event=0x80Icache hitumask=0x2,period=200000,event=0x80Icache misscycles_icache_mem_stalled.icache_mem_stalledumask=0x1,period=2000000,event=0x86Cycles during which instruction fetches are  stalleddecode_stall.pfb_emptyumask=0x1,period=2000000,event=0x87Decode stall due to PFB emptydecode_stall.iq_fullumask=0x2,period=2000000,event=0x87Decode stall due to IQ fullmacro_insts.non_cisc_decodedumask=0x1,period=2000000,event=0xaaNon-CISC nacro instructions decodedmacro_insts.cisc_decodedumask=0x2,period=2000000,event=0xaaCISC macro instructions decodedmacro_insts.all_decodedumask=0x3,period=2000000,event=0xaaAll Instructions decodeduops.ms_cyclesumask=0x1,period=2000000,cmask=1,event=0xa9This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQmisalign_mem_ref.splitumask=0xf,period=200000,event=0x5Memory references that cross an 8-byte boundarymisalign_mem_ref.ld_splitumask=0x9,period=200000,event=0x5Load splitsmisalign_mem_ref.st_splitumask=0xa,period=200000,event=0x5Store splitsmisalign_mem_ref.split.arumask=0x8f,period=200000,event=0x5Memory references that cross an 8-byte boundary (At Retirement)misalign_mem_ref.ld_split.arumask=0x89,period=200000,event=0x5Load splits (At Retirement)misalign_mem_ref.st_split.arumask=0x8a,period=200000,event=0x5Store splits (Ar Retirement)misalign_mem_ref.rmw_splitumask=0x8c,period=200000,event=0x5ld-op-st splitsmisalign_mem_ref.bubbleumask=0x97,period=200000,event=0x5Nonzero segbase 1 bubblemisalign_mem_ref.ld_bubbleumask=0x91,period=200000,event=0x5Nonzero segbase load 1 bubblemisalign_mem_ref.st_bubbleumask=0x92,period=200000,event=0x5Nonzero segbase store 1 bubblemisalign_mem_ref.rmw_bubbleumask=0x94,period=200000,event=0x5Nonzero segbase ld-op-st 1 bubbleprefetch.prefetcht0umask=0x81,period=200000,event=0x7Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedprefetch.prefetcht1umask=0x82,period=200000,event=0x7Streaming SIMD Extensions (SSE) PrefetchT1 instructions executedprefetch.prefetcht2umask=0x84,period=200000,event=0x7Streaming SIMD Extensions (SSE) PrefetchT2 instructions executedprefetch.sw_l2umask=0x86,period=200000,event=0x7Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedprefetch.prefetchntaumask=0x88,period=200000,event=0x7Streaming SIMD Extensions (SSE) Prefetch NTA instructions executedprefetch.hw_prefetchumask=0x10,period=2000000,event=0x7L1 hardware prefetch requestprefetch.software_prefetchumask=0xf,period=200000,event=0x7Any Software prefetchprefetch.software_prefetch.arumask=0x8f,period=200000,event=0x7segment_reg_loads.anyumask=0x80,period=200000,event=0x6Number of segment register loadsdispatch_blocked.anyumask=0x20,period=200000,event=0x9Memory cluster signals to block micro-op dispatch for any reasoneist_transumask=0x0,period=200000,event=0x3aNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsthermal_tripumask=0xc0,period=200000,event=0x3bNumber of thermal tripsbus_request_outstanding.all_agentsumask=0xe0,period=200000,event=0x60Outstanding cacheable data read bus requests durationbus_request_outstanding.selfumask=0x40,period=200000,event=0x60bus_bnr_drv.all_agentsumask=0x20,period=200000,event=0x61Number of Bus Not Ready signals assertedbus_bnr_drv.this_agentumask=0x0,period=200000,event=0x61bus_drdy_clocks.all_agentsumask=0x20,period=200000,event=0x62Bus cycles when data is sent on the busbus_drdy_clocks.this_agentumask=0x0,period=200000,event=0x62bus_lock_clocks.all_agentsumask=0xe0,period=200000,event=0x63Bus cycles when a LOCK signal is assertedbus_lock_clocks.selfumask=0x40,period=200000,event=0x63bus_data_rcv.selfumask=0x40,period=200000,event=0x64Bus cycles while processor receives databus_trans_brd.all_agentsumask=0xe0,period=200000,event=0x65Burst read bus transactionsbus_trans_brd.selfumask=0x40,period=200000,event=0x65bus_trans_rfo.all_agentsumask=0xe0,period=200000,event=0x66RFO bus transactionsbus_trans_rfo.selfumask=0x40,period=200000,event=0x66bus_trans_wb.all_agentsumask=0xe0,period=200000,event=0x67Explicit writeback bus transactionsbus_trans_wb.selfumask=0x40,period=200000,event=0x67bus_trans_ifetch.all_agentsumask=0xe0,period=200000,event=0x68Instruction-fetch bus transactionsbus_trans_ifetch.selfumask=0x40,period=200000,event=0x68bus_trans_inval.all_agentsumask=0xe0,period=200000,event=0x69Invalidate bus transactionsbus_trans_inval.selfumask=0x40,period=200000,event=0x69bus_trans_pwr.all_agentsumask=0xe0,period=200000,event=0x6aPartial write bus transactionbus_trans_pwr.selfumask=0x40,period=200000,event=0x6abus_trans_p.all_agentsumask=0xe0,period=200000,event=0x6bPartial bus transactionsbus_trans_p.selfumask=0x40,period=200000,event=0x6bbus_trans_io.all_agentsumask=0xe0,period=200000,event=0x6cIO bus transactionsbus_trans_io.selfumask=0x40,period=200000,event=0x6cbus_trans_def.all_agentsumask=0xe0,period=200000,event=0x6dDeferred bus transactionsbus_trans_def.selfumask=0x40,period=200000,event=0x6dbus_trans_burst.all_agentsumask=0xe0,period=200000,event=0x6eBurst (full cache-line) bus transactionsbus_trans_burst.selfumask=0x40,period=200000,event=0x6ebus_trans_mem.all_agentsumask=0xe0,period=200000,event=0x6fMemory bus transactionsbus_trans_mem.selfumask=0x40,period=200000,event=0x6fbus_trans_any.all_agentsumask=0xe0,period=200000,event=0x70All bus transactionsbus_trans_any.selfumask=0x40,period=200000,event=0x70ext_snoop.this_agent.anyumask=0xb,period=200000,event=0x77External snoopsext_snoop.this_agent.cleanumask=0x1,period=200000,event=0x77ext_snoop.this_agent.hitumask=0x2,period=200000,event=0x77ext_snoop.this_agent.hitmumask=0x8,period=200000,event=0x77ext_snoop.all_agents.anyumask=0x2b,period=200000,event=0x77ext_snoop.all_agents.cleanumask=0x21,period=200000,event=0x77ext_snoop.all_agents.hitumask=0x22,period=200000,event=0x77ext_snoop.all_agents.hitmumask=0x28,period=200000,event=0x77bus_hit_drv.all_agentsumask=0x20,period=200000,event=0x7aHIT signal assertedbus_hit_drv.this_agentumask=0x0,period=200000,event=0x7abus_hitm_drv.all_agentsumask=0x20,period=200000,event=0x7bHITM signal assertedbus_hitm_drv.this_agentumask=0x0,period=200000,event=0x7bbusq_empty.selfumask=0x40,period=200000,event=0x7dBus queue is emptysnoop_stall_drv.all_agentsumask=0xe0,period=200000,event=0x7eBus stalled for snoopssnoop_stall_drv.selfumask=0x40,period=200000,event=0x7ebus_io_wait.selfumask=0x40,period=200000,event=0x7fIO requests waiting in the bus queuecycles_int_masked.cycles_int_maskedumask=0x1,period=2000000,event=0xc6Cycles during which interrupts are disabledcycles_int_masked.cycles_int_pending_and_maskedumask=0x2,period=2000000,event=0xc6Cycles during which interrupts are pending and disabledhw_int_rcvumask=0x0,period=200000,event=0xc8Hardware interrupts receivedstore_forwards.anyumask=0x83,period=200000,event=0x2All store forwardsstore_forwards.goodumask=0x81,period=200000,event=0x2Good store forwardsreissue.anyumask=0x7f,period=200000,event=0x3Micro-op reissues for any causereissue.any.arumask=0xff,period=200000,event=0x3Micro-op reissues for any cause (At Retirement)mul.sumask=0x1,period=2000000,event=0x12Multiply operations executedmul.arumask=0x81,period=2000000,event=0x12Multiply operations retireddiv.sumask=0x1,period=2000000,event=0x13Divide operations executeddiv.arumask=0x81,period=2000000,event=0x13Divide operations retiredcycles_div_busyumask=0x1,period=2000000,event=0x14Cycles the divider is busycpu_clk_unhalted.core_pumask=0x0,period=2000000,event=0x3cCore cycles when core is not haltedcpu_clk_unhalted.busumask=0x1,period=200000,event=0x3cBus cycles when core is not haltedcpu_clk_unhalted.coreumask=0x0,period=2000000,event=0xacpu_clk_unhalted.refevent=0x0,umask=0x03Reference cycles when core is not haltedbr_inst_type_retired.condumask=0x1,period=2000000,event=0x88All macro conditional branch instructionsbr_inst_type_retired.uncondumask=0x2,period=2000000,event=0x88All macro unconditional branch instructions, excluding calls and indirectsbr_inst_type_retired.indumask=0x4,period=2000000,event=0x88All indirect branches that are not callsbr_inst_type_retired.retumask=0x8,period=2000000,event=0x88All indirect branches that have a return mnemonicbr_inst_type_retired.dir_callumask=0x10,period=2000000,event=0x88All non-indirect callsbr_inst_type_retired.ind_callumask=0x20,period=2000000,event=0x88All indirect calls, including both register and memory indirectbr_inst_type_retired.cond_takenumask=0x41,period=2000000,event=0x88Only taken macro conditional branch instructionsbr_missp_type_retired.condumask=0x1,period=200000,event=0x89Mispredicted cond branch instructions retiredbr_missp_type_retired.indumask=0x2,period=200000,event=0x89Mispredicted ind branches that are not callsbr_missp_type_retired.returnumask=0x4,period=200000,event=0x89Mispredicted return branchesbr_missp_type_retired.ind_callumask=0x8,period=200000,event=0x89Mispredicted indirect calls, including both register and memory indirectbr_missp_type_retired.cond_takenumask=0x11,period=200000,event=0x89Mispredicted and taken cond branch instructions retiredInstructions retired (precise event) (Must be precise)Instructions retireduops_retired.anyumask=0x10,period=2000000,event=0xc2Micro-ops retireduops_retired.stalled_cyclesCycles no micro-ops retireduops_retired.stallsPeriods no micro-ops retiredumask=0x1,period=200000,event=0xc3Self-Modifying Code detectedbr_inst_retired.anyumask=0x0,period=2000000,event=0xc4Retired branch instructionsbr_inst_retired.pred_not_takenumask=0x1,period=2000000,event=0xc4Retired branch instructions that were predicted not-takenbr_inst_retired.mispred_not_takenumask=0x2,period=200000,event=0xc4Retired branch instructions that were mispredicted not-takenbr_inst_retired.pred_takenumask=0x4,period=2000000,event=0xc4Retired branch instructions that were predicted takenbr_inst_retired.mispred_takenumask=0x8,period=200000,event=0xc4Retired branch instructions that were mispredicted takenbr_inst_retired.takenumask=0xc,period=2000000,event=0xc4Retired taken branch instructionsbr_inst_retired.any1umask=0xf,period=2000000,event=0xc4br_inst_retired.mispredumask=0x0,period=200000,event=0xc5Retired mispredicted branch instructions (precise event) (Precise event)resource_stalls.div_busyumask=0x2,period=2000000,event=0xdcCycles issue is stalled due to div busybr_inst_decodedumask=0x1,period=2000000,event=0xe0Branch instructions decodedbogus_brumask=0x1,period=2000000,event=0xe4Bogus branchesumask=0x1,period=2000000,event=0xe6BACLEARS assertedreissue.overlap_storeumask=0x1,period=200000,event=0x3Micro-op reissues on a store-load collisionreissue.overlap_store.arumask=0x81,period=200000,event=0x3Micro-op reissues on a store-load collision (At Retirement)data_tlb_misses.dtlb_missumask=0x7,period=200000,event=0x8Memory accesses that missed the DTLBdata_tlb_misses.dtlb_miss_ldumask=0x5,period=200000,event=0x8DTLB misses due to load operationsdata_tlb_misses.l0_dtlb_miss_ldumask=0x9,period=200000,event=0x8L0 DTLB misses due to load operationsdata_tlb_misses.dtlb_miss_stumask=0x6,period=200000,event=0x8DTLB misses due to store operationsdata_tlb_misses.l0_dtlb_miss_stumask=0xa,period=200000,event=0x8L0 DTLB misses due to store operationspage_walks.walksumask=0x3,period=200000,event=0xcNumber of page-walks executedpage_walks.cyclesumask=0x3,period=2000000,event=0xcDuration of page-walks in core cyclespage_walks.d_side_walksumask=0x1,period=200000,event=0xcNumber of D-side only page walkspage_walks.d_side_cyclesumask=0x1,period=2000000,event=0xcDuration of D-side only page walkspage_walks.i_side_walksumask=0x2,period=200000,event=0xcNumber of I-Side page walkspage_walks.i_side_cyclesumask=0x2,period=2000000,event=0xcDuration of I-Side page walksitlb.hitumask=0x1,period=200000,event=0x82ITLB hitsitlb.flushumask=0x4,period=200000,event=0x82ITLB flushesitlb.missesumask=0x2,period=200000,event=0x82ITLB misses (Must be precise)mem_load_retired.dtlb_missumask=0x4,period=200000,event=0xcbRetired loads that miss the DTLB (precise event) (Precise event)umask=0x41,period=200003,event=0x2eL2 cache request missesCounts memory requests originating from the core that miss in the L2 cacheumask=0x4f,period=200003,event=0x2eCounts memory requests originating from the core that reference a cache line in the L2 cachel2_reject_xq.allumask=0x0,period=200003,event=0x30Requests rejected by the XQCounts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victimscore_reject_l2q.allumask=0x0,period=200003,event=0x31Requests rejected by the L2QCounts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsdl1.dirty_evictionumask=0x1,period=200003,event=0x51L1 Cache evictions for dirty dataCounts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writebackfetch_stall.icache_fill_pending_cyclesumask=0x2,period=200003,event=0x86Cycles code-fetch stalled due to an outstanding ICache missCounts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchyumask=0x1,period=100007,event=0xb7Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x21,period=200003,event=0xd0Locked load uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks  Supports address when precise (Must be precise)umask=0x41,period=200003,event=0xd0Load uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)umask=0x42,period=200003,event=0xd0Stores uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts store uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)mem_uops_retired.splitumask=0x43,period=200003,event=0xd0Memory uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts memory uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)umask=0x81,period=200003,event=0xd0Load uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of load uops retired  Supports address when precise (Must be precise)umask=0x82,period=200003,event=0xd0Store uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of store uops retired  Supports address when precise (Must be precise)mem_uops_retired.allumask=0x83,period=200003,event=0xd0Memory uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of memory uops retired that is either a loads or a store or both  Supports address when precise (Must be precise)umask=0x1,period=200003,event=0xd1Load uops retired that hit L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that hit the L1 data cache  Supports address when precise (Must be precise)umask=0x2,period=200003,event=0xd1Load uops retired that hit L2 (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that hit in the L2 cache  Supports address when precise (Must be precise)umask=0x8,period=200003,event=0xd1Load uops retired that missed L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that miss the L1 data cache  Supports address when precise (Must be precise)umask=0x10,period=200003,event=0xd1Load uops retired that missed L2 (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that miss in the L2 cache  Supports address when precise (Must be precise)mem_load_uops_retired.hitmumask=0x20,period=200003,event=0xd1Memory uop retired where cross core or cross module HITM occurred (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks  Supports address when precise (Must be precise)mem_load_uops_retired.wcb_hitumask=0x40,period=200003,event=0xd1Loads retired that hit WCB (Precise event capable)  Supports address when precise (Must be precise)Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs  Supports address when precise (Must be precise)mem_load_uops_retired.dram_hitumask=0x80,period=200003,event=0xd1Loads retired that came from DRAM (Precise event capable)  Supports address when precise (Must be precise)Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response  Supports address when precise (Must be precise)offcore_response.any_read.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x36000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x04000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x02000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000432b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000022Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040022Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003091Counts data reads (demand & prefetch) that miss the L2 cacheCounts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003091Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003091Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003091Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043091Counts data reads (demand & prefetch) that hit the L2 cacheCounts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cacheCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003010Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043010Counts data reads generated by L1 or L2 prefetchers that hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008000Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008000Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008000Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor moduleCounts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000048000Counts requests to the uncore subsystem that hit the L2 cacheCounts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018000Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystemCounts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004800Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044800Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor moduleCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200002000Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000042000Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600001000Counts data cache lines requests by software prefetch instructions that miss the L2 cacheCounts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000001000Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400001000Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200001000Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000041000Counts data cache lines requests by software prefetch instructions that hit the L2 cacheCounts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010400Counts bus lock and split lock requests that have any transaction responses from the uncore subsystemCounts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_writes.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000100Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cacheCounts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_reads.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000080Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cacheCounts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040020Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000010Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040010Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor moduleCounts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040008Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000001Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000001Counts demand cacheable data reads of full cache lines that miss the L2 cacheCounts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000001Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000001Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000001Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040001Counts demand cacheable data reads of full cache lines that hit the L2 cacheCounts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=200003,event=0x80References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitectureReferences per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitectureumask=0x3,period=200003,event=0x80References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecturems_decoded.ms_entryumask=0x1,period=200003,event=0xe7MS decode startsCounts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine cleardecode_restriction.predecode_wrongumask=0x1,period=200003,event=0xe9Decode restrictions due to predicting wrong instruction lengthCounts the number of times the prediction (from the predecode cache) for instruction length is incorrectmisalign_mem_ref.load_page_splitumask=0x2,period=200003,event=0x13Load uops that split a page (Precise event capable) (Must be precise)Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise)misalign_mem_ref.store_page_splitumask=0x4,period=200003,event=0x13Store uops that split a page (Precise event capable) (Must be precise)Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise)umask=0x2,period=200003,event=0xc3Machine clears due to memory ordering issueCounts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the datafetch_stall.allumask=0x0,period=200003,event=0x86Cycles code-fetch stalled due to any reasonCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsfetch_stall.itlb_fill_pending_cyclesumask=0x1,period=200003,event=0x86Cycles code-fetch stalled due to an outstanding ITLB missCounts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translationissue_slots_not_consumed.anyumask=0x0,period=200003,event=0xcaUnfilled issue slots per cycleCounts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY)issue_slots_not_consumed.resource_fullumask=0x1,period=200003,event=0xcaUnfilled issue slots per cycle because of a full resource in the backendCounts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not countissue_slots_not_consumed.recoveryumask=0x2,period=200003,event=0xcaUnfilled issue slots per cycle to recoverCounts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queuehw_interrupts.receivedumask=0x1,period=203,event=0xcbCounts hardware interrupts received by the processorhw_interrupts.maskedumask=0x2,period=200003,event=0xcbCycles hardware interrupts are maskedCounts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or nothw_interrupts.pending_and_maskedumask=0x4,period=200003,event=0xcbCycles pending interrupts are maskedCounts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0)Instructions retired (Fixed event)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this eventumask=0x2,period=2000003,event=0Core cycles when core is not halted  (Fixed event)Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this eventReference cycles when core is not halted  (Fixed event)Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this eventld_blocks.data_unknownumask=0x1,period=200003,event=0x3Loads blocked due to store data not ready (Precise event capable) (Must be precise)Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available (Must be precise)umask=0x2,period=200003,event=0x3Loads blocked due to store forward restriction (Precise event capable) (Must be precise)Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise)ld_blocks.4k_aliasumask=0x4,period=200003,event=0x3Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise)Counts loads that block because their address modulo 4K matches a pending store (Must be precise)ld_blocks.utlb_missumask=0x8,period=200003,event=0x3Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise)Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise)ld_blocks.all_blockumask=0x10,period=200003,event=0x3Loads blocked (Precise event capable) (Must be precise)Counts anytime a load that retires is blocked for any reason (Must be precise)umask=0x0,period=200003,event=0xeUops issued to the back end per cycleCounts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clearCore cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterReference cycles when core is not halted.  This event uses a programmable general purpose performance counteruops_not_delivered.anyumask=0x0,period=200003,event=0x9cUops requested but not-delivered to the back-end per cycleThis event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issueInstructions retired (Precise event capable) (Must be precise)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise)umask=0x0,period=2000003,event=0xc2Uops retired (Precise event capable) (Must be precise)Counts uops which retired (Must be precise)uops_retired.msMS uops retired (Precise event capable) (Must be precise)Counts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise)uops_retired.fpdivumask=0x8,period=2000003,event=0xc2Floating point divide uops retired. (Precise Event Capable) (Must be precise)Counts the number of floating point divide uops retired (Must be precise)uops_retired.idivumask=0x10,period=2000003,event=0xc2Integer divide uops retired. (Precise Event Capable) (Must be precise)Counts the number of integer divide uops retired (Must be precise)machine_clears.allumask=0x0,period=200003,event=0xc3All machine clearsCounts machine clears for any reasonumask=0x1,period=200003,event=0xc3Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processorsmachine_clears.fp_assistumask=0x4,period=200003,event=0xc3Machine clears due to FP assistsCounts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal resultmachine_clears.disambiguationumask=0x8,period=200003,event=0xc3Machine clears due to memory disambiguationCounts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load addressumask=0x0,period=200003,event=0xc4Retired branch instructions (Precise event capable) (Must be precise)Counts branch instructions retired for all branch types.  This is an architectural performance event (Must be precise)br_inst_retired.jccumask=0x7e,period=200003,event=0xc4Retired conditional branch instructions (Precise event capable) (Must be precise)Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise)br_inst_retired.all_taken_branchesumask=0x80,period=200003,event=0xc4Retired taken branch instructions (Precise event capable) (Must be precise)Counts the number of taken branch instructions retired (Must be precise)umask=0xbf,period=200003,event=0xc4Retired far branch instructions (Precise event capable) (Must be precise)Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return (Must be precise)br_inst_retired.non_return_indumask=0xeb,period=200003,event=0xc4Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise)Counts near indirect call or near indirect jmp branch instructions retired (Must be precise)br_inst_retired.returnumask=0xf7,period=200003,event=0xc4Retired near return instructions (Precise event capable) (Must be precise)Counts near return branch instructions retired (Must be precise)br_inst_retired.callumask=0xf9,period=200003,event=0xc4Retired near call instructions (Precise event capable) (Must be precise)Counts near CALL branch instructions retired (Must be precise)br_inst_retired.ind_callumask=0xfb,period=200003,event=0xc4Retired near indirect call instructions (Precise event capable) (Must be precise)Counts near indirect CALL branch instructions retired (Must be precise)br_inst_retired.rel_callumask=0xfd,period=200003,event=0xc4Retired near relative call instructions (Precise event capable) (Must be precise)Counts near relative CALL branch instructions retired (Must be precise)br_inst_retired.taken_jccumask=0xfe,period=200003,event=0xc4Retired conditional branch instructions that were taken (Precise event capable) (Must be precise)Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise)umask=0x0,period=200003,event=0xc5Retired mispredicted branch instructions (Precise event capable) (Must be precise)Counts mispredicted branch instructions retired including all branch types (Must be precise)br_misp_retired.jccumask=0x7e,period=200003,event=0xc5Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise)br_misp_retired.non_return_indumask=0xeb,period=200003,event=0xc5Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise)Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise)br_misp_retired.returnumask=0xf7,period=200003,event=0xc5Retired mispredicted near return instructions (Precise event capable) (Must be precise)Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise)br_misp_retired.ind_callumask=0xfb,period=200003,event=0xc5Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise)Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise)br_misp_retired.taken_jccumask=0xfe,period=200003,event=0xc5Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise)cycles_div_busy.allumask=0x0,period=2000003,event=0xcdCycles a divider is busyCounts core cycles if either divide unit is busycycles_div_busy.idivumask=0x1,period=200003,event=0xcdCycles the integer divide unit is busyCounts core cycles the integer divide unit is busycycles_div_busy.fpdivumask=0x2,period=200003,event=0xcdCycles the FP divide unit is busyCounts core cycles the floating point divide unit is busybaclears.allumask=0x1,period=200003,event=0xe6BACLEARs asserted for any branch typeCounts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returnsbaclears.returnumask=0x8,period=200003,event=0xe6BACLEARs asserted for return branchCounts BACLEARS on return instructionsbaclears.condumask=0x10,period=200003,event=0xe6BACLEARs asserted for conditional branchCounts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branchesumask=0x1,period=200003,event=0x5Duration of D-side page-walks in cyclesCounts every core cycle when a Data-side (walks due to a data operation) page walk is in progressumask=0x2,period=200003,event=0x5Duration of I-side pagewalks in cyclesCounts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progressumask=0x3,period=200003,event=0x5Duration of page-walks in cyclesCounts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetchitlb.missumask=0x4,period=200003,event=0x81ITLB missesCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBmem_uops_retired.dtlb_miss_loadsumask=0x11,period=200003,event=0xd0Load uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that caused a DTLB miss  Supports address when precise (Must be precise)mem_uops_retired.dtlb_miss_storesumask=0x12,period=200003,event=0xd0Store uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts store uops retired that caused a DTLB miss  Supports address when precise (Must be precise)mem_uops_retired.dtlb_missumask=0x13,period=200003,event=0xd0Memory uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss  Supports address when precise (Must be precise)Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsdl1.replacementumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010001Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystemCounts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines hit the L2 cacheCounts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystemCounts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystemCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010008Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystemCounts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor moduleCounts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000008Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010010Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystemCounts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000010Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010020Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000020Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests have any transaction responses from the uncore subsystemCounts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040400Counts bus lock and split lock requests hit the L2 cacheCounts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000400Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor moduleCounts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000400Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000400Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystemCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000011000Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystemCounts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions hit the L2 cacheCounts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000001000Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000012000Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystemCounts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000002000Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014800Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystemCounts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004800Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor moduleCounts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004800Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000004800Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem have any transaction responses from the uncore subsystemCounts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem hit the L2 cacheCounts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor moduleCounts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000008000Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013010Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystemCounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003010Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013091Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystemCounts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) hit the L2 cacheCounts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003091Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010022Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000022Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x2,period=20003,event=0xc3Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the dataCycles the code-fetch stalls and an ITLB miss is outstandingInstructions retired (Fixed event) (Must be precise)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event (Must be precise)Reference cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterumask=0x0,period=2000003,event=0xc0Instructions retired - using Reduced Skid PEBS feature (Must be precise)Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise)Floating point divide uops retired (Precise Event Capable) (Must be precise)Integer divide uops retired (Precise Event Capable) (Must be precise)umask=0x0,period=20003,event=0xc3umask=0x1,period=20003,event=0xc3umask=0x4,period=20003,event=0xc3umask=0x8,period=20003,event=0xc3machine_clears.page_faultumask=0x20,period=20003,event=0xc3Machines clear due to a page faultCounts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violationRetired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise)umask=0x2,period=200003,event=0x8Page walk completed due to a demand load to a 4K pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page faultumask=0x4,period=200003,event=0x8Page walk completed due to a demand load to a 2M or 4M pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultdtlb_load_misses.walk_completed_1gbumask=0x8,period=200003,event=0x8Page walk completed due to a demand load to a 1GB pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages.  The page walks can end with or without a page faultdtlb_load_misses.walk_pendingumask=0x10,period=200003,event=0x8Page walks outstanding due to a demand load every cycleCounts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksumask=0x2,period=2000003,event=0x49Page walk completed due to a demand data store to a 4K pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultumask=0x4,period=2000003,event=0x49Page walk completed due to a demand data store to a 2M or 4M pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultdtlb_store_misses.walk_completed_1gbumask=0x8,period=2000003,event=0x49Page walk completed due to a demand data store to a 1GB pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultdtlb_store_misses.walk_pendingumask=0x10,period=200003,event=0x49Page walks outstanding due to a demand data store every cycleCounts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksept.walk_pendingumask=0x10,period=200003,event=0x4fPage walks outstanding due to walking the EPT every cycleCounts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation.  The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs).  Average cycles per walk can be calculated by dividing the count by number of walksumask=0x2,period=2000003,event=0x85Page walk completed due to an instruction fetch in a 4K pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultumask=0x4,period=2000003,event=0x85Page walk completed due to an instruction fetch in a 2M or 4M pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultitlb_misses.walk_completed_1gbumask=0x8,period=2000003,event=0x85Page walk completed due to an instruction fetch in a 1GB pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultitlb_misses.walk_pendingumask=0x10,period=200003,event=0x85Page walks outstanding due to an instruction fetch every cycleCounts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walkstlb_flushes.stlb_anyumask=0x20,period=20003,event=0xbdSTLB flushesCounts STLB flushes.  The TLBs are flushed on instructions like INVLPG and MOV to CR3Demand Data Read miss L2, no rejects  Spec update: HSD78Demand data read requests that missed L2, no rejects  Spec update: HSD78Counts the number of store RFO requests that miss the L2 cacheNumber of instruction fetches that missed the L2 cacheDemand requests that miss L2 cache  Spec update: HSD78Counts all L2 HW prefetcher requests that missed L2All requests that miss L2 cache  Spec update: HSD78All requests that missed L2  Spec update: HSD78Demand Data Read requests that hit L2 cache  Spec update: HSD78Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache  Spec update: HSD78Counts the number of store RFO requests that hit the L2 cacheNumber of instruction fetches that hit the L2 cacheCounts all L2 HW prefetcher requests that hit L2Demand Data Read requests  Spec update: HSD78Counts any demand and L1 HW prefetch data load requests to L2  Spec update: HSD78Counts all L2 store RFO requestsCounts all L2 code requestsDemand requests to L2 cache  Spec update: HSD78Counts all L2 HW prefetcher requestsAll L2 requests  Spec update: HSD78All requests to L2 cache  Spec update: HSD78This event counts each cache miss condition for references to the last level cacheThis event counts requests originating from the core that reference a cache line in the last level cacheIncrements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrencesl1d_pend_miss.request_fb_fullumask=0x2,period=2000003,event=0x48Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are eThis event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cacheOffcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD78, HSD62, HSD61Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD78, HSD62, HSD61Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61Cycles in which the L1D is lockedDemand Data Read requests sent to uncore  Spec update: HSD78Demand data read requests sent to uncore  Spec update: HSD78Demand code read requests sent to uncoreDemand RFO read requests sent to uncore, including regular RFOs, locks, ItoMData read requests sent to uncore (demand and prefetch)Retired load uops that miss the STLB. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired store uops that miss the STLB. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)umask=0x21,period=100003,event=0xd0Retired load uops with locked access. (precise Event)  Spec update: HSD76, HSD29, HSM30.  Supports address when precise (Precise event)Retired load uops that split across a cacheline boundary. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired store uops that split across a cacheline boundary. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)All retired load uops. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)All retired store uops. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts all store uops retired. This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired load uops with L1 cache hits as data sources  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired load uops with L2 cache hits as data sources  Spec update: HSD76, HSD29, HSM30.  Supports address when precise (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Retired load uops misses in L1 cache as data sources  Spec update: HSM30.  Supports address when precise (Precise event)This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event  Spec update: HSM30.  Supports address when precise (Precise event)Retired load uops with L2 cache misses as data sources  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)umask=0x20,period=100003,event=0xd1Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Spec update: HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were HitM responses from shared L3  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xd3This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Spec update: HSD74, HSD29, HSD25, HSM30.  Supports address when preciseDemand data read requests that access L2 cacheAny MLC or L3 HW prefetch accessing L2, including rejectsThis event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 missl2_lines_out.demand_dirtyumask=0x6,period=100003,event=0xf2Dirty L2 cache lines evicted by demandoffcore_response.all_requests.l3_hit.any_responseoffcore_response.all_reads.l3_hit.hitm_other_corehit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.l3_hit.hit_other_core_no_fwdhit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_code_rd.l3_hit.hit_other_core_no_fwdoffcore_response.all_rfo.l3_hit.hitm_other_coreoffcore_response.all_rfo.l3_hit.hit_other_core_no_fwdoffcore_response.all_data_rd.l3_hit.hitm_other_coreoffcore_response.all_data_rd.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l3_code_rd.l3_hit.any_responseoffcore_response.pf_l3_rfo.l3_hit.any_responseoffcore_response.pf_l3_data_rd.l3_hit.any_responseCounts all prefetch (that bring data to LLC only) data reads hit in the L3offcore_response.pf_l2_code_rd.l3_hit.any_responseCounts all prefetch (that bring data to LLC only) code reads hit in the L3offcore_response.pf_l2_rfo.l3_hit.any_responseCounts all prefetch (that bring data to L2) RFOs hit in the L3offcore_response.pf_l2_data_rd.l3_hit.any_responseCounts prefetch (that bring data to L2) data reads hit in the L3offcore_response.demand_code_rd.l3_hit.hitm_other_coreCounts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwdCounts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.l3_hit.hitm_other_coreoffcore_response.demand_rfo.l3_hit.hit_other_core_no_fwdCounts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_data_rd.l3_hit.hitm_other_coreCounts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwdCounts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedNumber of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57 (Precise event) Spec update: HSD56, HSM57 (Precise event)Number of transitions from legacy SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57 (Precise event)avx_insts.allumask=0x7,period=2000003,event=0xc6Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMXNote that a whole rep string only counts AVX_INST.ALL onceoutput - Numeric Overflow, Numeric Underflow, Inexact Result (Precise event)(Precise event)input - Invalid Operation, Denormal Operand, SNaN Operand (Precise event)SSE* FP micro-code assist when output value is invalid (Precise event)Any input SSE* FP Assist (Precise event)Counts any FP_ASSIST umask was incrementing (Precise event)Instruction Decode Queue (IDQ) empty cycles  Spec update: HSD135Counts cycles the IDQ is empty  Spec update: HSD135Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cyclesIncrement each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cyclesIncrement each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of deliveryCounts cycles DSB is delivered four uops. Set Cmask = 4Counts cycles DSB is delivered at least one uops. Set Cmask = 1Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cyclesCounts cycles MITE is delivered four uops. Set Cmask = 4Counts cycles MITE is delivered at least one uop. Set Cmask = 1This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceThis event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceNumber of uops delivered to IDQ from any pathThis event counts Instruction Cache (ICACHE) missesicache.ifetch_stallUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled  Spec update: HSD135This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis  Spec update: HSD135Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis  Spec update: HSD135Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135Cycles with less than 2 uops delivered by the front end  Spec update: HSD135Cycles with less than 3 uops delivered by the front end  Spec update: HSD135Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE  Spec update: HSD135hsw metrics( uops_executed.core / 2 / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) ) if #smt_on else uops_executed.core / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@)( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / cycles( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Speculative cache-line split load uops dispatched to L1DSpeculative cache-line split store-address uops dispatched to L1DNumber of times a transactional abort was signaled due to a data conflict on a transactionally accessed addressNumber of times a transactional abort was signaled due to a data capacity limitation for transactional writesNumber of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision bufferNumber of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroNumber of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision bufferNumber of times an HLE transactional execution aborted due to an unsupported read alignment from the elision bufferNumber of times HLE lock could not be elided due to ElisionBufferAvailable being zeroThis event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequentlyNumber of times an HLE execution startedNumber of times an HLE execution successfully committedNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event)Number of times an HLE execution aborted due to incompatible memory type  Spec update: HSD65Number of times an RTM execution startedNumber of times an RTM execution successfully committedNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event)Number of times an RTM execution aborted due to incompatible memory type  Spec update: HSD65Randomly selected loads with latency value being above 4  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 8  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 16  Spec update: HSD76, HSD25, HSM26 (Must be precise)umask=0x1,period=100003,event=0xcd,ldlat=0x20Randomly selected loads with latency value being above 32  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 64  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 128  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 256  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 512  Spec update: HSD76, HSD25, HSM26 (Must be precise)offcore_response.all_requests.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC08FFFoffcore_response.all_reads.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01004007F7miss the L3 and the data is returned from local dramoffcore_response.all_reads.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC007F7miss in the L3offcore_response.all_code_rd.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400244offcore_response.all_code_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00244offcore_response.all_rfo.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400122offcore_response.all_rfo.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00122offcore_response.all_data_rd.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400091offcore_response.all_data_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00091offcore_response.pf_l3_code_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00200offcore_response.pf_l3_rfo.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00100offcore_response.pf_l3_data_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00080Counts all prefetch (that bring data to LLC only) data reads miss in the L3offcore_response.pf_l2_code_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00040Counts all prefetch (that bring data to LLC only) code reads miss in the L3offcore_response.pf_l2_rfo.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00020Counts all prefetch (that bring data to L2) RFOs miss in the L3offcore_response.pf_l2_data_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00010Counts prefetch (that bring data to L2) data reads miss in the L3offcore_response.demand_code_rd.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400004Counts all demand code reads miss the L3 and the data is returned from local dramoffcore_response.demand_code_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00004Counts all demand code reads miss in the L3offcore_response.demand_rfo.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400002Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dramoffcore_response.demand_rfo.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00002offcore_response.demand_data_rd.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400001Counts demand data reads miss the L3 and the data is returned from local dramoffcore_response.demand_data_rd.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00001Counts demand data reads miss in the L3umask=0x1,edge=1,period=100003,cmask=1,event=0x5cUnhalted core cycles when the thread is not in ring 0Cycles in which the L1D and L2 are locked, due to a UC lock or split lockInstructions retired from execution  Spec update: HSD140, HSD143This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions  Spec update: HSD140, HSD143This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt stateloads blocked by overlapping with store buffer that cannot be forwardedThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issuedThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useFalse dependencies in MOB due to partial compare on addressAliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impactThis event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etcThis event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uopsuops_issued.core_stall_cyclesinv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xeCycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threadsNumber of flags-merge uops allocated. Such uops add delayNumber of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or notNumber of multiply packed/scalar single precision uops allocatedarith.divider_uopsumask=0x2,period=2000003,event=0x14Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingIncrements at the frequency of XCLK (100 MHz) when not haltedReference cycles when the thread is unhalted. (counts at 100 MHz rate)Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetchNon-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetchNumber of integer move elimination candidate uops that were eliminatedNumber of SIMD move elimination candidate uops that were eliminatedNumber of integer move elimination candidate uops that were not eliminatedNumber of SIMD move elimination candidate uops that were not eliminatedThis event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-endThis event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP)ild_stall.iq_fullumask=0x4,period=2000003,event=0x87Stall cycles because IQ is fullStall cycles due to IQ is fullCounts all near executed branches (not necessarily retired)Cycles which a uop is dispatched on port 0 in this threadCycles per core when uops are executed in port 0Cycles which a uop is dispatched on port 1 in this threadCycles per core when uops are executed in port 1Cycles which a uop is dispatched on port 2 in this threadCycles which a uop is dispatched on port 3 in this threadCycles which a uop is dispatched on port 4 in this threadCycles per core when uops are executed in port 4Cycles which a uop is dispatched on port 5 in this threadCycles per core when uops are executed in port 5Cycles which a uop is dispatched on port 6 in this threadCycles per core when uops are executed in port 6Cycles which a uop is dispatched on port 7 in this threadResource-related stall cycles  Spec update: HSD135Cycles allocation is stalled due to resource related reason  Spec update: HSD135This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were availableCycles with pending L2 cache miss loads  Spec update: HSD78Cycles with pending L2 miss loads. Set Cmask=2 to count cycle  Spec update: HSD78Cycles with pending memory loadsCycles with pending memory loads. Set Cmask=2 to count cycleThis event counts cycles during which no instructions were executed in the execution stage of the pipelineExecution stalls due to L2 cache missesNumber of loads missed L2Execution stalls due to memory subsystemThis event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data)Cycles with pending L1 cache miss loadsCycles with pending L1 data cache miss loads. Set Cmask=8 to count cycleExecution stalls due to L1 data cache missesExecution stalls due to L1 data cache miss loads. Set Cmask=0CHNumber of uops delivered by the LSDCounts number of cycles no uops were dispatched to be executed on this thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 1 uop was executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least one uop was executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 2 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least two uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 3 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least three uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 4 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31Number of uops executed on the core  Spec update: HSD30, HSM31Counts total number of uops to be executed per-core each cycle  Spec update: HSD30, HSM31Cycles at least 1 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 2 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 3 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 4 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles with no micro-ops executed from any thread on physical core  Spec update: HSD30, HSM31Number of instructions retired. General Counter   - architectural event  Spec update: HSD11, HSD140Number of instructions at retirement  Spec update: HSD11, HSD140Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: HSD140 (Must be precise)FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling (Precise event)Cycles no executable uops retired (Precise event)uops_retired.core_stall_cyclesinv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xc2Cycles no executable uops retired on core (Precise event)This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequentlyBranch instructions at retirementumask=0x2,period=100003,event=0xc4All (macro) branch instructions retired (Must be precise)umask=0x8,period=100003,event=0xc4Counts all not taken macro branch instructions retired (Precise event)umask=0x40,period=100003,event=0xc4Counts the number of far branch instructions retired (Precise event)Mispredicted branch instructions at retirementMispredicted macro branch instructions retired (Must be precise)This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise)Count cases of saving new LBR records by hardwareNumber of front end re-steers due to BPU mispredictionunc_cbo_xsnp_response.miss_externalumask=0x21,event=0x22Unit: uncore_cbox An external snoop misses in some processor coreAn external snoop misses in some processor coreunc_cbo_xsnp_response.hit_externalumask=0x24,event=0x22Unit: uncore_cbox An external snoop hits a non-modified line in some processor coreAn external snoop hits a non-modified line in some processor coreunc_cbo_xsnp_response.hit_evictionumask=0x84,event=0x22Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor coreA cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor coreunc_cbo_xsnp_response.hitm_externalumask=0x28,event=0x22Unit: uncore_cbox An external snoop hits a modified line in some processor coreAn external snoop hits a modified line in some processor coreunc_cbo_xsnp_response.hitm_evictionumask=0x88,event=0x22Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor coreA cross-core snoop resulted from L3 Eviction which hits a modified line in some processor coreunc_cbo_cache_lookup.extsnp_mumask=0x41,event=0x34Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-stateL3 Lookup external snoop request that access cache and found line in M-stateunc_cbo_cache_lookup.write_iumask=0x28,event=0x34Unit: uncore_cbox L3 Lookup write request that access cache and found line in I-stateL3 Lookup write request that access cache and found line in I-stateunc_cbo_cache_lookup.extsnp_iumask=0x48,event=0x34Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-stateL3 Lookup external snoop request that access cache and found line in I-stateunc_cbo_cache_lookup.extsnp_mesiumask=0x4f,event=0x34Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in MESI-stateL3 Lookup external snoop request that access cache and found line in MESI-stateunc_cbo_cache_lookup.extsnp_esumask=0x46,event=0x34Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in E or S-stateL3 Lookup external snoop request that access cache and found line in E or S-stateunc_arb_coh_trk_occupancy.allumask=0x01,event=0x83Unit: uncore_arb Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)Load misses in all DTLB levels that cause page walksMisses in all TLB levels that cause a page walk of any page sizeDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)Completed page walks due to demand load misses that caused 4K page walks in any TLB levelsDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levelsLoad miss in all TLB levels causes a page walk that completes. (1G)Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page sizeCompleted page walks in any TLB of any page size due to demand load missesCycles when PMH is busy with page walksThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load missesThis event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksThis event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksNumber of cache load STLB hits. No page walkdtlb_load_misses.pde_cache_missumask=0x80,period=100003,event=0x8DTLB demand load misses with low part of linear-to-physical address translation missedStore misses in all DTLB levels that cause page walksMiss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G)Store miss in all TLB levels causes a page walk that completes. (4K)Completed page walks due to store misses in one or more TLB levels of 4K page structureStore misses in all DTLB levels that cause completed page walks (2M/4M)Completed page walks due to store misses in one or more TLB levels of 2M/4M page structureStore misses in all DTLB levels that cause completed page walks. (1G)Store misses in all DTLB levels that cause completed page walksCompleted page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G)This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store missesThis event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksThis event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksdtlb_store_misses.pde_cache_missumask=0x80,period=100003,event=0x49DTLB store misses with low part of linear-to-physical address translation missedMisses at all ITLB levels that cause page walksMisses in ITLB that causes a page walk of any page sizeCode miss in all TLB levels causes a page walk that completes. (4K)Completed page walks due to misses in ITLB 4K page entriesCode miss in all TLB levels causes a page walk that completes. (2M/4M)Completed page walks due to misses in ITLB 2M/4M page entriesStore miss in all TLB levels causes a page walk that completes. (1G)Misses in all ITLB levels that cause completed page walksCompleted page walks in ITLB of any page sizeThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB missesITLB misses that hit STLB (4K)ITLB misses that hit STLB (2M)ITLB misses that hit STLB. No page walkumask=0x1,period=100003,event=0xaeCounts the number of ITLB flushes, includes 4k/2M/4M pagesNumber of DTLB page walker hits in the L1+FBNumber of DTLB page walker loads that hit in the L1+FBNumber of DTLB page walker hits in the L2Number of DTLB page walker loads that hit in the L2Number of DTLB page walker hits in the L3 + XSNP  Spec update: HSD25Number of DTLB page walker loads that hit in the L3  Spec update: HSD25Number of DTLB page walker hits in Memory  Spec update: HSD25Number of DTLB page walker loads from memory  Spec update: HSD25Number of ITLB page walker hits in the L1+FBNumber of ITLB page walker loads that hit in the L1+FBNumber of ITLB page walker hits in the L2Number of ITLB page walker loads that hit in the L2Number of ITLB page walker hits in the L3 + XSNP  Spec update: HSD25Number of ITLB page walker loads that hit in the L3  Spec update: HSD25page_walker_loads.itlb_memoryumask=0x28,period=2000003,event=0xbcNumber of ITLB page walker hits in Memory  Spec update: HSD25Number of ITLB page walker loads from memory  Spec update: HSD25page_walker_loads.ept_dtlb_l1umask=0x41,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the DTLB that hit in the L1 and FBpage_walker_loads.ept_dtlb_l2umask=0x42,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the DTLB that hit in the L2page_walker_loads.ept_dtlb_l3umask=0x44,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the DTLB that hit in the L3page_walker_loads.ept_dtlb_memoryumask=0x48,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the DTLB that hit in memorypage_walker_loads.ept_itlb_l1umask=0x81,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the ITLB that hit in the L1 and FBpage_walker_loads.ept_itlb_l2umask=0x82,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the ITLB that hit in the L2page_walker_loads.ept_itlb_l3umask=0x84,period=2000003,event=0xbcpage_walker_loads.ept_itlb_memoryumask=0x88,period=2000003,event=0xbcCounts the number of Extended Page Table walks from the ITLB that hit in memoryumask=0x1,period=100003,event=0xbdumask=0x20,period=100003,event=0xbdCount number of STLB flush attemptsRetired load uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired store uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops with locked access  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)Retired load uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired store uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)All retired load uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)All retired store uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops with L1 cache hits as data sources  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops with L3 cache hits as data sources  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops misses in L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops missed L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops missed L2. Unknown data source excluded  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops missed L3. Excludes unknown data source   Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)umask=0x4,period=100003,event=0xd3Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)umask=0x10,period=100003,event=0xd3Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: HSM30 (Precise event)umask=0x20,period=100003,event=0xd3Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwdoffcore_response.demand_data_rd.llc_hit.hitm_other_coreoffcore_response.demand_rfo.llc_hit.hit_other_core_no_fwdoffcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwdoffcore_response.demand_code_rd.llc_hit.hitm_other_coreoffcore_response.pf_l2_data_rd.llc_hit.any_responseoffcore_response.pf_l2_rfo.llc_hit.any_responseoffcore_response.pf_l2_code_rd.llc_hit.any_responseoffcore_response.pf_llc_data_rd.llc_hit.any_responseNumber of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57Number of X87 FP assists due to output valuesNumber of X87 FP assists due to input valuesNumber of SIMD FP assists due to output valuesCycles with any input/output SSE* or FP assistshsx metricsoffcore_response.demand_data_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00001offcore_response.demand_data_rd.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400001offcore_response.demand_rfo.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400002offcore_response.demand_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00004offcore_response.demand_code_rd.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400004offcore_response.pf_l2_data_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00010offcore_response.pf_l2_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00020offcore_response.pf_l2_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00040offcore_response.pf_llc_data_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F800091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400122umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x06004007F7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F8007F7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC007F7edge=1,umask=0x1,cmask=1,period=100003,event=0x5cinv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xeFP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handlingThis is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingNumber of microcode assists invoked by HW upon uop writebackCounts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles  Supports address when precise (Precise event)inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xc2This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event)Counts the number of conditional branch instructions retired (Precise event)Counts the number of near return instructions retired (Precise event)Counts the number of not taken branch instructions retiredNumber of near taken branches retired (Precise event)Far branch instructions retiredNumber of far branches retiredNumber of near branch instructions retired that were taken but mispredicted (Precise event)umask=0x1,period=200003,event=0x24umask=0x3,period=200003,event=0x24Counts any demand and L1 HW prefetch data load requests to L2umask=0x4,period=200003,event=0x24umask=0x8,period=200003,event=0x24umask=0xc,period=200003,event=0x24umask=0x10,period=200003,event=0x24umask=0x20,period=200003,event=0x24l2_rqsts.pf_hitumask=0x40,period=200003,event=0x24Requests from the L2 hardware prefetchers that hit L2 cachel2_rqsts.pf_missumask=0x80,period=200003,event=0x24Requests from the L2 hardware prefetchers that miss L2 cacheumask=0xc0,period=200003,event=0x24l2_store_lock_rqsts.missumask=0x1,period=200003,event=0x27RFOs that miss cache linesl2_store_lock_rqsts.hit_mumask=0x8,period=200003,event=0x27RFOs that hit cache lines in M statel2_store_lock_rqsts.allumask=0xf,period=200003,event=0x27RFOs that access cache lines in any statel2_l1d_wb_rqsts.missumask=0x1,period=200003,event=0x28Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)Not rejected writebacks that missed LLCl2_l1d_wb_rqsts.hit_eumask=0x4,period=200003,event=0x28Not rejected writebacks from L1D to L2 cache lines in E statel2_l1d_wb_rqsts.hit_mumask=0x8,period=200003,event=0x28Not rejected writebacks from L1D to L2 cache lines in M statel2_l1d_wb_rqsts.allumask=0xf,period=200003,event=0x28Not rejected writebacks from L1D to L2 cache lines in any stateCore-originated cacheable demand requests missed LLCCore-originated cacheable demand requests that refer to LLCCounts the number of lines brought into the L1 data cacheOffcore outstanding Demand Data Read transactions in uncore queueOffcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cyclesCycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncoreCycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queueOffcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycleOffcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cyclesoffcore_requests_outstanding.cycles_with_demand_code_rdumask=0x2,period=2000003,cmask=1,event=0x60Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncoreOffcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cyclesOffcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycleOffcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncoreOffcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cyclesCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncoreDemand data read requests sent to uncoreCases when offcore requests buffer cannot take more entries for coreRetired load uops that miss the STLB. (Precise Event)Retired store uops that miss the STLB. (Precise Event)Retired load uops with locked access. (Precise Event)Retired load uops that split across a cacheline boundary. (Precise Event)Retired store uops that split across a cacheline boundary. (Precise Event)All retired load uops. (Precise Event)All retired store uops. (Precise Event)Retired load uops with L1 cache hits as data sources (Precise event)Retired load uops with L2 cache hits as data sources (Precise event)mem_load_uops_retired.llc_hitRetired load uops which data sources were data hits in LLC without snoops required (Precise event)Retired load uops which data sources following L1 data-cache miss (Precise event)Retired load uops with L2 cache misses as data sources (Precise event)mem_load_uops_retired.llc_missMiss in last-level (L3) cache. Excludes Unknown data-source (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event)mem_load_uops_llc_hit_retired.xsnp_missRetired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event)mem_load_uops_llc_hit_retired.xsnp_hitRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event)mem_load_uops_llc_hit_retired.xsnp_hitmRetired load uops which data sources were HitM responses from shared LLC (Precise event)mem_load_uops_llc_hit_retired.xsnp_noneRetired load uops which data sources were hits in LLC without snoops required (Precise event)mem_load_uops_llc_miss_retired.local_dramRetired load uops which data sources missed LLC but serviced from local dramRetired load uops whose data source was local memory (cross-socket snoop not needed or missed)L2 or LLC HW prefetches that access L2 cacheAny MLC or LLC HW prefetch accessing L2, including rejectsumask=0x1,period=100003,event=0xf2umask=0x2,period=100003,event=0xf2l2_lines_out.pf_cleanumask=0x4,period=100003,event=0xf2Clean L2 cache lines evicted by L2 prefetchClean L2 cache lines evicted by the MLC prefetcherl2_lines_out.pf_dirtyumask=0x8,period=100003,event=0xf2Dirty L2 cache lines evicted by L2 prefetchDirty L2 cache lines evicted by the MLC prefetcherl2_lines_out.dirty_allumask=0xa,period=100003,event=0xf2Dirty L2 cache lines filling the L2offcore_response.all_code_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0244Counts all demand & prefetch code reads that hit in the LLCoffcore_response.all_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0244Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_data_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0091Counts all demand & prefetch data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0091Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0091Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_data_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0091Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0122Counts all demand & prefetch RFOs that hit in the LLCoffcore_response.all_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0122Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10008Counts all writebacks from the core to the LLCoffcore_response.demand_code_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0004Counts all demand code reads that hit in the LLCoffcore_response.demand_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0004Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.demand_data_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0001Counts all demand data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0001Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0001Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_data_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0001Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0002Counts all demand data writes (RFOs) that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0002Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x18000Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core cachesoffcore_response.split_lock_uc_lock.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10400Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable addressumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10800Counts non-temporal storesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010001Counts all demand data readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010002Counts all demand rfo'sumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000105B3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010122Counts all demand & prefetch prefetch RFOsoffcore_response.all_reads.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000107F7Counts all data/code/rfo references (demand & prefetch)fp_comp_ops_exe.x87umask=0x1,period=2000003,event=0x10Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a sCounts number of X87 uops executedfp_comp_ops_exe.sse_packed_doubleumask=0x10,period=2000003,event=0x10Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cyclefp_comp_ops_exe.sse_scalar_singleumask=0x20,period=2000003,event=0x10Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cyclefp_comp_ops_exe.sse_packed_singleumask=0x40,period=2000003,event=0x10Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cyclefp_comp_ops_exe.sse_scalar_doubleumask=0x80,period=2000003,event=0x10Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycleCounts number of SSE* or AVX-128 double precision FP scalar uops executedsimd_fp_256.packed_singleumask=0x1,period=2000003,event=0x11number of GSSE-256 Computational FP single precision uops issued this cycleCounts 256-bit packed single-precision floating-point instructionssimd_fp_256.packed_doubleumask=0x2,period=2000003,event=0x11number of AVX-256 Computational FP double precision uops issued this cycleCounts 256-bit packed double-precision floating-point instructionsother_assists.avx_storeNumber of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operationsNumber of assists associated with 256-bit AVX store operationsNumber of transitions from AVX-256 to legacy SSE when penalty applicableumask=0x20,period=100003,event=0xc1Number of transitions from SSE to AVX-256 when penalty applicableCounts cycles the IDQ is emptyCounts cycles MITE is delivered at least one uops. Set Cmask = 1Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cyclesInstruction cache, streaming buffer and victim cache missesNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesCycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB missCount issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stalldsb2mite_switches.countumask=0x1,period=2000003,event=0xabDecode Stream Buffer (DSB)-to-MITE switchesNumber of DSB to MITE switchesCycles DSB to MITE switches caused delaydsb_fill.exceed_dsb_linesumask=0x8,period=2000003,event=0xacCycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) linesDSB Fill encountered > 3 DSB linesivb metricsmin( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 32 * ( icache.hit + icache.misses ) / 4 ) )(( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / cycles(( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))1000 * mem_load_uops_retired.llc_miss / inst_retired.any( (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / 1000000000 ) / duration_timeSpeculative cache-line split Store-address uops dispatched to L1Dpage_walks.llc_missumask=0x1,period=100003,event=0xbeNumber of any page walk that had a miss in LLCLoads with latency value being above 4 (Must be precise)Loads with latency value being above 8 (Must be precise)Loads with latency value being above 16 (Must be precise)Loads with latency value being above 32 (Must be precise)Loads with latency value being above 64 (Must be precise)Loads with latency value being above 128 (Must be precise)Loads with latency value being above 256 (Must be precise)Loads with latency value being above 512 (Must be precise)mem_trans_retired.precise_storeumask=0x2,period=2000003,event=0xcdSample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise)offcore_response.all_code_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400244Counts all demand & prefetch code reads that miss the LLC  and the data returned from dramoffcore_response.all_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400091Counts all demand & prefetch data reads that miss the LLC  and the data returned from dramoffcore_response.all_reads.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3004003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dramoffcore_response.demand_code_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400004Counts demand code reads that miss the LLC and the data returned from dramoffcore_response.demand_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400001Counts demand data reads that miss the LLC and the data returned from dramoffcore_response.data_in_socket.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004001b3Counts LLC replacementsLoads blocked by overlapping with store buffer that cannot be forwardedNumber of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)int_misc.recovery_stalls_countumask=0x3,edge=1,period=2000003,cmask=1,event=0xdNumber of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this coreNumber of flags-merge uops being allocatedNumber of flags-merge uops allocated. Such uops adds delayNumber of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notCycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of dividesarith.fpu_divumask=0x4,edge=1,period=100003,cmask=1,event=0x14Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)Count XClk pulses when this thread is unhalted and the other is haltedCycles the RS is empty for the threadCycles per thread when uops are dispatched to port 0Cycles which a Uop is dispatched on port 0uops_dispatched_port.port_0_coreCycles per core when uops are dispatched to port 0Cycles per thread when uops are dispatched to port 1Cycles which a Uop is dispatched on port 1uops_dispatched_port.port_1_coreCycles per core when uops are dispatched to port 1umask=0xc,period=2000003,event=0xa1Cycles per thread when load or STA uops are dispatched to port 2Cycles which a Uop is dispatched on port 2uops_dispatched_port.port_2_coreumask=0xc,any=1,period=2000003,event=0xa1Uops dispatched to port 2, loads and stores per core (speculative and retired)umask=0x30,period=2000003,event=0xa1Cycles per thread when load or STA uops are dispatched to port 3Cycles which a Uop is dispatched on port 3uops_dispatched_port.port_3_coreumask=0x30,any=1,period=2000003,event=0xa1Cycles per core when load or STA uops are dispatched to port 3Cycles per thread when uops are dispatched to port 4Cycles which a Uop is dispatched on port 4uops_dispatched_port.port_4_coreCycles per core when uops are dispatched to port 4Cycles per thread when uops are dispatched to port 5Cycles which a Uop is dispatched on port 5uops_dispatched_port.port_5_coreCycles per core when uops are dispatched to port 5Cycles Allocation is stalled due to Resource Related reasonCycles stalled due to no store buffers available (not including draining form sync)Cycles with pending L2 cache miss loadsCycles with pending L2 miss loads. Set AnyThread to count per coreCycles while L2 cache miss load* is outstandingCycles with pending memory loads. Set AnyThread to count per coreExecution stalls while L2 cache miss load* is outstandingCycles with pending L1 cache miss loads. Set AnyThread to count per coreCounts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cyclesCounts total number of uops to be executed per-core each cycleNumber of instructions retired. General Counter   - architectural eventNumber of instructions at retirementPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise)umask=0x80,period=100003,event=0xc1Retired uops (Precise event)Number of self-modifying-code machine clears detectedCounts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0unc_cbo_xsnp_response.missumask=0x01,event=0x22Unit: uncore_cbox A snoop misses in some processor coreA snoop misses in some processor coreunc_cbo_xsnp_response.invalumask=0x02,event=0x22Unit: uncore_cbox A snoop invalidates a non-modified line in some processor coreA snoop invalidates a non-modified line in some processor coreunc_cbo_xsnp_response.hitumask=0x04,event=0x22Unit: uncore_cbox A snoop hits a non-modified line in some processor coreA snoop hits a non-modified line in some processor coreunc_cbo_xsnp_response.hitmumask=0x08,event=0x22Unit: uncore_cbox A snoop hits a modified line in some processor coreA snoop hits a modified line in some processor coreunc_cbo_xsnp_response.inval_mumask=0x10,event=0x22Unit: uncore_cbox A snoop invalidates a modified line in some processor coreA snoop invalidates a modified line in some processor coreunc_cbo_xsnp_response.external_filterumask=0x20,event=0x22Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop requestFilter on cross-core snoops initiated by this Cbox due to external snoop requestunc_cbo_xsnp_response.xcore_filterumask=0x40,event=0x22Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to processor core memory requestFilter on cross-core snoops initiated by this Cbox due to processor core memory requestunc_cbo_xsnp_response.eviction_filterumask=0x80,event=0x22Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC evictionFilter on cross-core snoops initiated by this Cbox due to LLC evictionunc_cbo_cache_lookup.mumask=0x01,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in M-stateLLC lookup request that access cache and found line in M-stateunc_cbo_cache_lookup.eumask=0x02,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in E-stateLLC lookup request that access cache and found line in E-stateunc_cbo_cache_lookup.sumask=0x04,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in S-stateLLC lookup request that access cache and found line in S-stateunc_cbo_cache_lookup.iumask=0x08,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in I-stateLLC lookup request that access cache and found line in I-stateunc_cbo_cache_lookup.read_filterumask=0x10,event=0x34Unit: uncore_cbox Filter on processor core initiated cacheable read requestsFilter on processor core initiated cacheable read requestsunc_cbo_cache_lookup.write_filterumask=0x20,event=0x34Unit: uncore_cbox Filter on processor core initiated cacheable write requestsFilter on processor core initiated cacheable write requestsunc_cbo_cache_lookup.extsnp_filterumask=0x40,event=0x34Unit: uncore_cbox Filter on external snoop requestsFilter on external snoop requestsunc_cbo_cache_lookup.any_request_filterumask=0x80,event=0x34Unit: uncore_cbox Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsUnit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLCCounts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLCUnit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLCCounts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLCUnit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictionsCounts the number of allocated write entries, include full, partial, and LLC evictionsunc_arb_trk_requests.evictionsumask=0x80,event=0x81Unit: uncore_arb Counts the number of LLC evictions allocatedCounts the number of LLC evictions allocatedUnit: uncore_arb Cycles weighted by number of requests pending in Coherency TrackerCycles weighted by number of requests pending in Coherency TrackerUnit: uncore_arb Number of requests allocated in Coherency TrackerNumber of requests allocated in Coherency TrackerUnit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCunc_arb_trk_occupancy.cycles_over_half_fullumask=0x01,cmask=10,event=0x80Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCCycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCUnit: uncore_arb This 48-bit fixed counter counts the UCLK cyclesunc_cbo_cache_lookup.esumask=0x06,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-stateLLC lookup request that access cache and found line in E-state or S-stateumask=0x81,period=100003,event=0x8Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page sizeMisses in all TLB levels that cause a page walk of any page size from demand loadsumask=0x82,period=100003,event=0x8Misses in all TLB levels that caused page walk completed of any size by demand loadsumask=0x84,period=2000003,event=0x8Demand load cycles page miss handler (PMH) is busy with this walkCycle PMH is busy with a walk due to demand loadsdtlb_load_misses.large_page_walk_completedumask=0x88,period=100003,event=0x8Page walk for a large page completed for Demand loadMiss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkCycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesumask=0x4,period=100003,event=0x5fCounts load operations that missed 1st level DTLB but hit the 2nd levelMisses in all ITLB levels that cause page walksCycle PMH is busy with a walkitlb_misses.large_page_walk_completedumask=0x80,period=100003,event=0x85Completed page walks in ITLB due to STLB load misses for large pagesumask=0x3,period=100007,event=0xd3Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)mem_load_uops_llc_miss_retired.remote_dramumask=0xc,period=100007,event=0xd3Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)mem_load_uops_llc_miss_retired.remote_hitmRemote cache HITMmem_load_uops_llc_miss_retired.remote_fwdData forwarded from remote cacheoffcore_response.all_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0091Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.all_pf_data_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0090Counts all prefetch data reads that hit the LLCoffcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0090Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_data_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0090Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_data_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0090Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0090Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.all_reads.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_reads.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.demand_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0001Counts demand data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.other.lru_hintsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x803c8000Counts L2 hints sent to LLC to keep a line from being evicted out of the core cachesoffcore_response.other.portio_mmio_ucumask=0x1,period=100003,event=0xb7,offcore_rsp=0x23ffc08000Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accessesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0040Counts all prefetch (that bring data to L2) code reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0010Counts prefetch (that bring data to L2) data reads that hit in the LLCoffcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_data_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_data_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0200Counts all prefetch (that bring data to LLC only) code reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLCoffcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_data_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_data_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseivt metricsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc00244Counts all demand & prefetch code reads that miss the LLCoffcore_response.all_code_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800244Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dramoffcore_response.all_code_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f800244Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20091Counts all demand & prefetch data reads that hits the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc203f7Counts all data/code/rfo reads (demand & prefetch) that hit the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f8203f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20004Counts all demand code reads that miss the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400004Counts all demand code reads that miss the LLC  and the data returned from local dramoffcore_response.demand_code_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800004Counts all demand code reads that miss the LLC  and the data returned from remote dramoffcore_response.demand_code_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820004Counts all demand code reads that miss the LLC  and the data forwarded from remote cacheoffcore_response.demand_code_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00004Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereoffcore_response.demand_data_rd.llc_miss.any_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00001Counts demand data reads that miss the LLC  and the data returned from remote & local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20001Counts demand data reads that miss in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400001Counts demand data reads that miss the LLC  and the data returned from local dramoffcore_response.demand_data_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800001Counts demand data reads that miss the LLC  and the data returned from remote dramoffcore_response.demand_data_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820001Counts demand data reads that miss the LLC  and the data forwarded from remote cacheoffcore_response.demand_data_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00001Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc20002Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20040Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dramoffcore_response.pf_l2_data_rd.llc_miss.any_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20010Counts prefetch (that bring data to L2) data reads that miss in the LLCoffcore_response.pf_l2_data_rd.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dramoffcore_response.pf_l2_data_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800010Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dramoffcore_response.pf_l2_data_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cacheoffcore_response.pf_l2_data_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00010Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20200Counts all prefetch (that bring data to LLC only) code reads that miss in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20080Counts prefetch (that bring data to LLC only) data reads that miss in the LLCLLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x19cPCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox llc_misses.itom_writeLLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox llc_misses.pcie_non_snoop_readumask=0x3,event=0x35,filter_opc=0x1e4LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x1e6LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox llc_references.pcie_partial_readumask=0x1,event=0x35,filter_opc=0x195Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x19cPCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox llc_references.itom_writeumask=0x1,event=0x35,filter_opc=0x1c8ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox llc_references.pcie_ns_readumask=0x1,event=0x35,filter_opc=0x1e4PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1e5PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox llc_references.pcie_ns_writeumask=0x1,event=0x35,filter_opc=0x1e6PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox unc_c_tor_occupancy.miss_localumask=0x2A,event=0x36Occupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox unc_c_tor_occupancy.miss_remoteumask=0x8A,event=0x36Occupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha Write requests to home agent. Unit: uncore_ha QPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi unc_q_rxl0p_power_cyclesevent=0x10Cycles where receiving QPI link is in half-width mode. Unit: uncore_qpi (unc_q_rxl0p_power_cycles / unc_q_clockticks) * 100.rxl0p_power_cycles %unc_q_txl0p_power_cyclesevent=0xdCycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi (unc_q_txl0p_power_cycles / unc_q_clockticks) * 100.txl0p_power_cycles %unc_q_txl_flits_g0.dataNumber of data flits transmitted . Unit: uncore_qpi unc_q_txl_flits_g0.non_dataNumber of non data (control) flits transmitted . Unit: uncore_qpi unc_m_act_count.rdumask=0x1,umask=0x3,event=0x1Memory page activates for reads and writes. Unit: uncore_imc Read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc Memory page conflicts. Unit: uncore_imc unc_p_freq_band0_cyclesevent=0xbCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band0_cycles / unc_p_clockticks) * 100.freq_band0_cycles %unc_p_freq_band1_cyclesevent=0xcCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band1_cycles / unc_p_clockticks) * 100.freq_band1_cycles %unc_p_freq_band2_cyclesCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band2_cycles / unc_p_clockticks) * 100.freq_band2_cycles %unc_p_freq_band3_cyclesevent=0xeCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band3_cycles / unc_p_clockticks) * 100.freq_band3_cycles %unc_p_freq_band0_transitionsevent=0xb,edge=1Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_band1_transitionsevent=0xc,edge=1Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_band2_transitionsevent=0xd,edge=1Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_band3_transitionsevent=0xe,edge=1Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu unc_p_freq_max_current_cyclesevent=0x7(unc_p_freq_max_current_cycles / unc_p_clockticks) * 100.freq_max_current_cycles %event=0x60Cycles spent changing Frequency. Unit: uncore_pcu unc_p_freq_ge_1200mhz_cyclesevent=0xb,filter_band0=12Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu (unc_p_freq_ge_1200mhz_cycles / unc_p_clockticks) * 100.freq_ge_1200mhz_cycles %unc_p_freq_ge_2000mhz_cyclesevent=0xc,filter_band1=20Counts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu (unc_p_freq_ge_2000mhz_cycles / unc_p_clockticks) * 100.freq_ge_2000mhz_cycles %unc_p_freq_ge_3000mhz_cyclesevent=0xd,filter_band2=30Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu (unc_p_freq_ge_3000mhz_cycles / unc_p_clockticks) * 100.freq_ge_3000mhz_cycles %unc_p_freq_ge_4000mhz_cyclesevent=0xe,filter_band3=40Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu (unc_p_freq_ge_4000mhz_cycles / unc_p_clockticks) * 100.freq_ge_4000mhz_cycles %unc_p_freq_ge_1200mhz_transitionsevent=0xb,edge=1,filter_band0=12Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_ge_2000mhz_transitionsevent=0xc,edge=1,filter_band1=20Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_ge_3000mhz_transitionsevent=0xd,edge=1,filter_band2=30Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_ge_4000mhz_transitionsevent=0xe,edge=1,filter_band3=40Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu dtlb_load_misses.demand_ld_walk_completeddtlb_load_misses.demand_ld_walk_durationRetired load uops that miss the STLB (Precise event)Retired store uops that miss the STLB (Precise event)Retired load uops with locked access (Precise event)Retired load uops that split across a cacheline boundary (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)Retired store uops that split across a cacheline boundary (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)All retired load uops (Precise event)This event counts the number of load uops retired (Precise event)All retired store uops (Precise event)This event counts the number of store uops retired (Precise event)Retired load uops which data sources were data hits in LLC without snoops requiredThis event counts retired load uops that hit in the last-level (L3) cache without snoops requiredMiss in last-level (L3) cache. Excludes Unknown data-sourceRetired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cacheRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cacheThis event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified stateRetired load uops which data sources were HitM responses from shared LLCThis event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2Retired load uops which data sources were hits in LLC without snoops requiredData from local DRAM either Snoop not needed or Snoop Miss (RspI)Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlierl1d.allocated_in_mumask=0x2,period=2000003,event=0x51Allocated L1D data cache lines in M statel1d.evictionumask=0x4,period=2000003,event=0x51L1D data cache lines in M state evicted due to replacementl1d.all_m_replacementumask=0x8,period=2000003,event=0x51Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacementl2_store_lock_rqsts.hit_eumask=0x4,period=200003,event=0x27RFOs that hit cache lines in E statel2_l1d_wb_rqsts.hit_sumask=0x2,period=200003,event=0x28Not rejected writebacks from L1D to L2 cache lines in S statel1d_blocks.bank_conflict_cyclesumask=0x5,period=100003,cmask=1,event=0xbfCycles when dispatched loads are cancelled due to L1D bank conflicts with other load portsoffcore_requests_outstanding.demand_data_rd_c6umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010008Number of GSSE-256 Computational FP single precision uops issued this cycleNumber of AVX-256 Computational FP double precision uops issued this cycleThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accessesThis event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more informationUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterizationThis event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-enddsb_fill.other_cancelumask=0x2,period=2000003,event=0xacCases of cancelling valid DSB fill not because of exceeding way limitidq_uops_not_delivered.cycles_ge_1_uop_deliv.coreinv=1,umask=0x1,period=2000003,cmask=4,event=0x9cCycles when 1 or more uops were delivered to the by the front enddsb_fill.all_cancelumask=0xa,period=2000003,event=0xacCases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limitjkt metricsuops_dispatched.thread / (( cpu@uops_dispatched.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_dispatched.core\,cmask\=1@)This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequentlyLoads with latency value being above 4  (Must be precise)Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise)offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400077Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excludedoffcore_response.all_demand_mlc_pref_reads.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC20077This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excludedoffcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x187FC20077This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excludedinsts_written_to_iq.instsumask=0x1,period=2000003,event=0x17Valid instructions written to IQ per cyclehw_pre_req.dl1_missumask=0x2,period=2000003,event=0x4eHardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlersThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsbr_misp_exec.taken_direct_near_callumask=0x90,period=200003,event=0x89Taken speculative and retired mispredicted direct near callsbr_misp_exec.all_direct_near_callumask=0xd0,period=200003,event=0x89Speculative and retired mispredicted direct near callsumask=0x40,period=2000003,event=0xdpartial_rat_stalls.flags_merge_uopumask=0x20,period=2000003,event=0x59Increments the number of flags-merge uops in flight each cyclepartial_rat_stalls.slow_lea_windowumask=0x40,period=2000003,event=0x59Cycles with at least one slow LEA uop being allocatedThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionspartial_rat_stalls.mul_single_uopumask=0x80,period=2000003,event=0x59Multiply packed/scalar single precision uops allocatedresource_stalls.lbumask=0x2,period=2000003,event=0xa2Counts the cycles of stall due to lack of load buffersresource_stalls2.bob_fullumask=0x40,period=2000003,event=0x5bCycles when Allocator is stalled if BOB is full and new branch needs itThis event counts the number of Uops issued by the front-end of the pipeilne to the back-endActually retired uops (Precise event)This event counts the number of micro-ops retired (Precise event)This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event)All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise)br_misp_retired.near_callumask=0x2,period=100007,event=0xc5Direct and indirect mispredicted near call instructions retired (Precise event)br_misp_retired.not_takenumask=0x10,period=400009,event=0xc5Mispredicted not taken branch instructions retired (Precise event)br_misp_retired.takenMispredicted taken branch instructions retired (Precise event)other_assists.itlb_miss_retiredumask=0x2,period=100003,event=0xc1Retired instructions experiencing ITLB missesumask=0x1,edge=1,period=100003,cmask=1,event=0x14This event counts the number of the divide operations executeduops_dispatched.threadUops dispatched per threaduops_dispatched.coreUops dispatched from any threadcycle_activity.cycles_no_dispatchEach cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED eventEach cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGEach cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGEach cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2umask=0x1,period=100003,event=0x3Loads delayed due to SB blocks, preceding store operations with known addresses but unknown dataThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedumask=0x10,period=100003,event=0x3Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cyclesld_blocks_partial.all_sta_blockumask=0x8,period=100003,event=0x7This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeagu_bypass_cancel.countumask=0x1,period=100003,event=0xb6This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in anCycles per core when load or STA uops are dispatched to port 2Instructions retired. (Precise Event - PEBS) (Must be precise)resource_stalls2.all_prf_controlumask=0xf,period=2000003,event=0x5bResource stalls2 control structures full for physical registersresource_stalls2.all_fl_emptyumask=0xc,period=2000003,event=0x5bCycles with either free list is emptyresource_stalls.mem_rsumask=0xe,period=2000003,event=0xa2Resource stalls due to memory buffers or Reservation Station (RS) being fully utilizedresource_stalls.ooo_rsrcumask=0xf0,period=2000003,event=0xa2Resource stalls due to Rob being full, FCSW, MXCSR and OTHERresource_stalls2.ooo_rsrcumask=0x4f,period=2000003,event=0x5bResource stalls out of order resources fullresource_stalls.lb_sbumask=0xa,period=2000003,event=0xa2Resource stalls due to load or store buffers all being in useNumber of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)partial_rat_stalls.flags_merge_uop_cyclesumask=0x20,period=2000003,cmask=1,event=0x59Performance sensitive flags-merging uops added by Sandy Bridge u-archThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference ManualNumber of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)inv=1,umask=0x1,edge=1,period=2000003,cmask=1,event=0x5eunc_c_tor_occupancy.miss_allumask=0xa,event=0x36,filter_opc=0x182Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox (unc_c_tor_occupancy.miss_all / unc_c_clockticks) * 100.tor_occupancy.miss_all %umask=0x3,event=0x36umask=0xc,event=0x1QPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi unc_m_act_countevent=0x1Memory page activates. Unit: uncore_imc umask=0xc,event=0x4Memory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc unc_m_rpq_occupancyevent=0x80Occupancy counter for memory read queue. Unit: uncore_imc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of times that the uncore transistioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB missesumask=0x2,period=100003,event=0x8Load misses at all DTLB levels that cause completed page walksumask=0x10,period=100003,event=0x8This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cyclesl2_requests_reject.allCounts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple timesCounts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative pathl2_requests.referenceCounts the total number of L2 cache referencesl2_requests.missCounts the number of L2 cache missesumask=0x4,period=200003,event=0x86Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache missesThis event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache missesmem_uops_retired.l1_miss_loadsumask=0x1,period=200003,event=0x4Counts the number of load micro-ops retired that miss in L1 D cacheThis event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedmem_uops_retired.l2_hit_loadsumask=0x2,period=200003,event=0x4Counts the number of load micro-ops retired that hit in the L2  Supports address when precise (Precise event)mem_uops_retired.l2_miss_loadsumask=0x4,period=100007,event=0x4Counts the number of load micro-ops retired that miss in the L2  Supports address when precise (Precise event)mem_uops_retired.utlb_miss_loadsumask=0x10,period=200003,event=0x4Counts the number of load micro-ops retired that caused micro TLB missmem_uops_retired.hitmumask=0x20,period=200003,event=0x4Counts the loads retired that get the data from the other core in the same tile in M state  Supports address when precise (Precise event)umask=0x40,period=200003,event=0x4Counts all the load micro-ops retiredThis event counts the number of load micro-ops retiredumask=0x80,period=200003,event=0x4Counts all the store micro-ops retiredThis event counts the number of store micro-ops retiredCounts the matrix events specified by MSR_OFFCORE_RESPxoffcore_response.any_pf_l2.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000070Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_pf_l2.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_pf_l2.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_pf_l2.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_pf_l2.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_pf_l2.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010070Counts any Prefetch requests that accounts for any responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032f7Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_read.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10004032f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_read.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x08004032f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_read.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000832f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_read.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x08000832f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132f7Counts any Read request  that accounts for any responseoffcore_response.any_code_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000044Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_code_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_code_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_code_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_code_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_code_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010044Counts Demand code reads and prefetch code read requests  that accounts for any responseCounts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_rfo.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_rfo.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_rfo.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_rfo.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Demand cacheable data write requests  that accounts for any responseCounts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_data_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_data_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_data_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000083091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800083091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Demand cacheable data and L1 prefetch data read requests  that accounts for any responseCounts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_request.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000408000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_request.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800408000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_request.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000088000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_request.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800088000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts any request that accounts for any responseCounts all streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_streaming_stores.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014000Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any responseCounts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.pf_l1_data_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000402000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l1_data_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800402000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l1_data_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000082000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l1_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800082000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts L1 data HW prefetches that accounts for any responseoffcore_response.pf_software.outstandingCounts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.pf_software.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000401000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_software.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800401000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_software.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000081000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_software.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800081000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_software.any_responseCounts Software Prefetches that accounts for any responseCounts Full streaming stores (WC and should be programmed on PMC1) that accounts for any responseCounts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.bus_locks.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.bus_locks.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.bus_locks.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.bus_locks.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Bus locks and split lock requests that accounts for any responseoffcore_response.uc_code_reads.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000200Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.uc_code_reads.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.uc_code_reads.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.uc_code_reads.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.uc_code_reads.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.uc_code_reads.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010200Counts UC code reads (valid only for Outstanding response type)  that accounts for any responseoffcore_response.partial_writes.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.partial_writes.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.partial_writes.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.partial_writes.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_writes.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_reads.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.partial_reads.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.partial_reads.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.partial_reads.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.partial_reads.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_reads.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for any responseoffcore_response.pf_l2_code_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000040Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.pf_l2_code_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l2_code_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l2_code_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l2_code_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010040Counts L2 code HW prefetches that accounts for any responseoffcore_response.pf_l2_rfo.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l2_rfo.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l2_rfo.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l2_rfo.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_l2_rfo.supplier_noneumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000020020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier detailsCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any responseCounts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.demand_code_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_code_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_code_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_code_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts demand code reads and prefetch code reads that accounts for any responseCounts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.demand_rfo.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_rfo.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Demand cacheable data writes that accounts for any responseCounts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.demand_data_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_data_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_data_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts demand cacheable data and L1 prefetch data reads that accounts for any responseoffcore_response.demand_data_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_rfo.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_code_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.partial_reads.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.partial_writes.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.uc_code_reads.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.bus_locks.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_software.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_request.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002008000Counts any request that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_data_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_rfo.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_code_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_read.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00020032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_pf_l2.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_data_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_rfo.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_code_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l2_code_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000040Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_reads.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_writes.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.uc_code_reads.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.bus_locks.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_software.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_request.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004008000Counts any request that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_data_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_rfo.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_code_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_read.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00040032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_pf_l2.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_data_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.demand_rfo.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.demand_code_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.partial_reads.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.partial_writes.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.uc_code_reads.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.bus_locks.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_software.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_request.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008008000Counts any request that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_data_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_rfo.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_code_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_read.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00080032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.demand_data_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_rfo.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_code_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l2_code_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000040Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.partial_reads.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.partial_writes.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.uc_code_reads.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.bus_locks.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_software.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_request.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010008000Counts any request that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_data_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_rfo.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_code_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_read.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00100032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_pf_l2.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_rfo.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180002Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.demand_code_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180004Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l2_rfo.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l2_code_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180040Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.partial_reads.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.partial_writes.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.uc_code_reads.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180200Counts UC code reads (valid only for Outstanding response type)  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.bus_locks.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180400Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_software.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800181000Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l1_data_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800182000Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_request.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800188000Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_data_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800183091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_rfo.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180022Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_code_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180044Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_read.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x18001832f7Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_pf_l2.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180070Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.demand_rfo.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400002Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.demand_code_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400004Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_l2_code_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400040Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.partial_reads.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.partial_writes.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.bus_locks.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400400Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_software.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800401000Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_l1_data_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800402000Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_request.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800408000Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_data_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_rfo.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400022Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_code_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400044Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_read.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x18004032f7Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_pf_l2.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400070Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts all instruction fetches, including uncacheable fetchesCounts all instruction fetches that hit the instruction cacheCounts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstandingCounts the number of times the MSROM starts a flow of uopsCounts the number of times the machine clears due to memory ordering hazardsoffcore_response.any_pf_l2.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400070Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_pf_l2.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200070Counts any Prefetch requests that accounts for data responses from MCDRAM Localoffcore_response.any_pf_l2.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000070Counts any Prefetch requests that accounts for data responses from DRAM Faroffcore_response.any_pf_l2.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800070Counts any Prefetch requests that accounts for data responses from DRAM Localoffcore_response.any_read.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01004032f7Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_read.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00802032f7Counts any Read request  that accounts for data responses from MCDRAM Localoffcore_response.any_read.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01010032f7Counts any Read request  that accounts for data responses from DRAM Faroffcore_response.any_read.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00808032f7Counts any Read request  that accounts for data responses from DRAM Localoffcore_response.any_code_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400044Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_code_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200044Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Localoffcore_response.any_code_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000044Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Faroffcore_response.any_code_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800044Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Localoffcore_response.any_rfo.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400022Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_rfo.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200022Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Localoffcore_response.any_rfo.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000022Counts Demand cacheable data write requests  that accounts for data responses from DRAM Faroffcore_response.any_rfo.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800022Counts Demand cacheable data write requests  that accounts for data responses from DRAM Localoffcore_response.any_data_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_data_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080203091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Localoffcore_response.any_data_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Faroffcore_response.any_data_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080803091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Localoffcore_response.any_request.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100408000Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_request.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080208000Counts any request that accounts for data responses from MCDRAM Localoffcore_response.any_request.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101008000Counts any request that accounts for data responses from DRAM Faroffcore_response.any_request.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080808000Counts any request that accounts for data responses from DRAM Localoffcore_response.pf_l1_data_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100402000Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l1_data_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080202000Counts L1 data HW prefetches that accounts for data responses from MCDRAM Localoffcore_response.pf_l1_data_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101002000Counts L1 data HW prefetches that accounts for data responses from DRAM Faroffcore_response.pf_l1_data_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080802000Counts L1 data HW prefetches that accounts for data responses from DRAM Localoffcore_response.pf_software.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100401000Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_software.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080201000Counts Software Prefetches that accounts for data responses from MCDRAM Localoffcore_response.pf_software.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101001000Counts Software Prefetches that accounts for data responses from DRAM Faroffcore_response.pf_software.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080801000Counts Software Prefetches that accounts for data responses from DRAM Localoffcore_response.bus_locks.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400400Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.bus_locks.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200400Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Localoffcore_response.bus_locks.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000400Counts Bus locks and split lock requests that accounts for data responses from DRAM Faroffcore_response.bus_locks.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800400Counts Bus locks and split lock requests that accounts for data responses from DRAM Localoffcore_response.uc_code_reads.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.uc_code_reads.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Localoffcore_response.uc_code_reads.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Faroffcore_response.uc_code_reads.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Localoffcore_response.partial_writes.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.partial_writes.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Localoffcore_response.partial_writes.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Faroffcore_response.partial_writes.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Localoffcore_response.partial_reads.non_dramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsoffcore_response.partial_reads.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.partial_reads.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Localoffcore_response.partial_reads.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Faroffcore_response.partial_reads.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Localoffcore_response.pf_l2_code_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400040Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l2_code_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200040Counts L2 code HW prefetches that accounts for data responses from MCDRAM Localoffcore_response.pf_l2_code_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000040Counts L2 code HW prefetches that accounts for data responses from DRAM Faroffcore_response.pf_l2_code_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800040Counts L2 code HW prefetches that accounts for data responses from DRAM Localoffcore_response.pf_l2_rfo.non_dramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsoffcore_response.pf_l2_rfo.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l2_rfo.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Localoffcore_response.pf_l2_rfo.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Faroffcore_response.pf_l2_rfo.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Localoffcore_response.demand_code_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400004Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_code_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200004Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Localoffcore_response.demand_code_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000004Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Faroffcore_response.demand_code_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800004Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Localoffcore_response.demand_rfo.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400002Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_rfo.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200002Counts Demand cacheable data writes that accounts for data responses from MCDRAM Localoffcore_response.demand_rfo.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000002Counts Demand cacheable data writes that accounts for data responses from DRAM Faroffcore_response.demand_rfo.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800002Counts Demand cacheable data writes that accounts for data responses from DRAM Localoffcore_response.demand_data_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_data_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Localoffcore_response.demand_data_rd.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Faroffcore_response.demand_data_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Localoffcore_response.demand_data_rd.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)offcore_response.demand_rfo.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600002Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)offcore_response.demand_code_rd.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600004Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)offcore_response.pf_l2_rfo.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)offcore_response.partial_reads.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)offcore_response.partial_writes.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)offcore_response.uc_code_reads.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)offcore_response.bus_locks.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600400Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)offcore_response.pf_software.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180601000Counts Software Prefetches that accounts for responses from MCDRAM (local and far)offcore_response.any_request.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180608000Counts any request that accounts for responses from MCDRAM (local and far)offcore_response.any_data_rd.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180603091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_rfo.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600022Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_code_rd.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600044Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_read.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01806032f7Counts any Read request  that accounts for responses from MCDRAM (local and far)offcore_response.any_pf_l2.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600070Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)offcore_response.demand_data_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)offcore_response.demand_rfo.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800002Counts Demand cacheable data writes that accounts for responses from DDR (local and far)offcore_response.demand_code_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800004Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)offcore_response.pf_l2_rfo.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)offcore_response.pf_l2_code_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800040Counts L2 code HW prefetches that accounts for responses from DDR (local and far)offcore_response.partial_reads.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)offcore_response.uc_code_reads.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)offcore_response.bus_locks.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800400Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)offcore_response.pf_software.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181801000Counts Software Prefetches that accounts for responses from DDR (local and far)offcore_response.pf_l1_data_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181802000Counts L1 data HW prefetches that accounts for responses from DDR (local and far)offcore_response.any_request.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181808000Counts any request that accounts for responses from DDR (local and far)offcore_response.any_data_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181803091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)offcore_response.any_rfo.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800022Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)offcore_response.any_code_rd.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800044Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)offcore_response.any_read.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01818032f7Counts any Read request  that accounts for responses from DDR (local and far)Counts the number of branch instructions retired (Precise event)Counts the number of branch instructions retired that were conditional jumps (Precise event)Counts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of near CALL branch instructions retired (Precise event)Counts the number of near relative CALL branch instructions retired (Precise event)Counts the number of near indirect CALL branch instructions retired (Precise event)Counts the number of near RET branch instructions retired (Precise event)Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)Counts the number of mispredicted branch instructions retired (Precise event)Counts the number of mispredicted branch instructions retired that were conditional jumps (Precise event)Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event)Counts the number of mispredicted near RET branch instructions retired (Precise event)Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)This event counts the number of micro-ops retired that were supplied from MSROMCounts the number of micro-ops retiredThis event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assistsuops_retired.scalar_simdumask=0x20,period=200003,event=0xc2Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrtThis event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrtuops_retired.packed_simdumask=0x40,period=200003,event=0xc2Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesThis event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesCounts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code pageCounts the number of floating operations retired that required microcode assistsThis event counts the number of times that the pipeline stalled due to FP operations needing assistsCounts all nukesno_alloc_cycles.rob_fullCounts the number of core cycles when no micro-ops are allocated and the ROB is fullno_alloc_cycles.mispredictsumask=0x4,period=200003,event=0xcaCounts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireThis event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireno_alloc_cycles.rat_stallumask=0x20,period=200003,event=0xcaCounts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is assertedno_alloc_cycles.not_deliveredumask=0x90,period=200003,event=0xcaCounts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocationThis event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetchedno_alloc_cycles.allumask=0x7f,period=200003,event=0xcaCounts the total number of core cycles when no micro-ops are allocated for any reasonrs_full_stall.mecumask=0x1,period=200003,event=0xcbCounts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entryrs_full_stall.allumask=0x1f,period=200003,event=0xcbCounts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is fullCounts the total number of instructions retiredumask=0x1,period=2000003,event=0xcdCycles the number of core cycles when divider is busy.  Does not imply a stall waiting for the dividerThis event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector dividesFixed Counter: Counts the number of instructions retiredThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or trapsCounts the number of unhalted core clock cyclesCounts the number of unhalted reference clock cyclesFixed Counter: Counts the number of unhalted core clock cyclesThis event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counterFixed Counter: Counts the number of unhalted reference clock cyclesCounts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front endCounts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front endCounts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front endrecycleq.ld_block_st_forwardCounts the number of occurences a retired load gets blocked because its address partially overlaps with a store  Supports address when precise (Precise event)recycleq.ld_block_std_notreadyCounts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not readyrecycleq.st_splitsCounts the number of occurences a retired store that is a cache line split. Each split should be counted only onceThis event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only oncerecycleq.ld_splitsCounts the number of occurences a retired load that is a cache line split. Each split should be counted only once  Supports address when precise (Precise event)recycleq.lockCounts all the retired locked loads. It does not include stores because we would double count if we count storesrecycleq.sta_fullumask=0x20,period=200003,event=0x3Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is fullrecycleq.any_ldumask=0x40,period=200003,event=0x3Counts any retired load that was pushed into the recycle queue for any reasonrecycleq.any_stumask=0x80,period=200003,event=0x3Counts any retired store that was pushed into the recycle queue for any reasonbr_misp_retired.callumask=0xf9,period=200003,event=0xc5Counts the number of mispredicted near CALL branch instructions retired (Precise event)br_misp_retired.rel_callumask=0xfd,period=200003,event=0xc5Counts the number of mispredicted near relative CALL branch instructions retired (Precise event)br_misp_retired.far_branchumask=0xbf,period=200003,event=0xc5Counts the number of mispredicted far branch instructions retired (Precise event)unc_m_cas_count.rdumask=0x01,event=0x3ddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc 6.4e-05MiBunc_m_cas_count.wrumask=0x02,event=0x3ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc unc_e_rpq_insertsumask=0x01,event=0x1mcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk uncore_edc_eclkunc_e_wpq_insertsumask=0x01,event=0x2mcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk umask=0x8,period=200003,event=0x4Counts the number of load micro-ops retired that cause a DTLB miss  Supports address when precise (Precise event)umask=0x1,period=100003,edge=1,event=0x5Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be countedCounts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be includedumask=0x2,period=100003,edge=1,event=0x5Counts the total I-side page walks that are completedCounts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be includedThis event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progressumask=0x3,period=100003,edge=1,event=0x5Counts the total page walks that are completed (I-side and D-side)Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be includedThis event counts every cycle when a data (D) page walk or instruction (I) page walk is in progresscache_lock_cycles.l1dumask=0x2,period=2000000,event=0x63Cycles L1D lockedcache_lock_cycles.l1d_l2umask=0x1,period=2000000,event=0x63Cycles L1D and L2 lockedl1d.m_evictumask=0x4,period=2000000,event=0x51L1D cache lines replaced in M statel1d.m_replumask=0x2,period=2000000,event=0x51L1D cache lines allocated in the M statel1d.m_snoop_evictumask=0x8,period=2000000,event=0x51L1D snoop eviction of cache lines in M statel1d.replumask=0x1,period=2000000,event=0x51L1 data cache lines allocatedl1d_all_ref.anyumask=0x1,period=2000000,event=0x43All references to the L1 data cachel1d_all_ref.cacheableumask=0x2,period=2000000,event=0x43L1 data cacheable reads and writesl1d_cache_ld.e_stateumask=0x4,period=2000000,event=0x40L1 data cache read in E statel1d_cache_ld.i_stateumask=0x1,period=2000000,event=0x40L1 data cache read in I state (misses)l1d_cache_ld.m_stateumask=0x8,period=2000000,event=0x40L1 data cache read in M statel1d_cache_ld.mesiumask=0xf,period=2000000,event=0x40L1 data cache readsl1d_cache_ld.s_stateumask=0x2,period=2000000,event=0x40L1 data cache read in S statel1d_cache_lock.e_stateumask=0x4,period=2000000,event=0x42L1 data cache load locks in E statel1d_cache_lock.hitumask=0x1,period=2000000,event=0x42L1 data cache load lock hitsl1d_cache_lock.m_stateumask=0x8,period=2000000,event=0x42L1 data cache load locks in M statel1d_cache_lock.s_stateumask=0x2,period=2000000,event=0x42L1 data cache load locks in S statel1d_cache_lock_fb_hitumask=0x1,period=2000000,event=0x53L1D load lock accepted in fill bufferl1d_cache_prefetch_lock_fb_hitumask=0x1,period=2000000,event=0x52L1D prefetch load lock accepted in fill bufferl1d_cache_st.e_stateumask=0x4,period=2000000,event=0x41L1 data cache stores in E statel1d_cache_st.m_stateumask=0x8,period=2000000,event=0x41L1 data cache stores in M statel1d_cache_st.s_stateumask=0x2,period=2000000,event=0x41L1 data cache stores in S statel1d_prefetch.missumask=0x2,period=200000,event=0x4eL1D hardware prefetch missesl1d_prefetch.requestsumask=0x1,period=200000,event=0x4eL1D hardware prefetch requestsl1d_prefetch.triggersumask=0x4,period=200000,event=0x4eL1D hardware prefetch requests triggeredl1d_wb_l2.e_stateumask=0x4,period=100000,event=0x28L1 writebacks to L2 in E statel1d_wb_l2.i_stateumask=0x1,period=100000,event=0x28L1 writebacks to L2 in I state (misses)l1d_wb_l2.m_stateumask=0x8,period=100000,event=0x28L1 writebacks to L2 in M statel1d_wb_l2.mesiumask=0xf,period=100000,event=0x28All L1 writebacks to L2l1d_wb_l2.s_stateumask=0x2,period=100000,event=0x28L1 writebacks to L2 in S statel2_data_rqsts.anyumask=0xff,period=200000,event=0x26All L2 data requestsl2_data_rqsts.demand.e_stateumask=0x4,period=200000,event=0x26L2 data demand loads in E statel2_data_rqsts.demand.i_stateumask=0x1,period=200000,event=0x26L2 data demand loads in I state (misses)l2_data_rqsts.demand.m_stateumask=0x8,period=200000,event=0x26L2 data demand loads in M statel2_data_rqsts.demand.mesiumask=0xf,period=200000,event=0x26L2 data demand requestsl2_data_rqsts.demand.s_stateumask=0x2,period=200000,event=0x26L2 data demand loads in S statel2_data_rqsts.prefetch.e_stateL2 data prefetches in E statel2_data_rqsts.prefetch.i_stateumask=0x10,period=200000,event=0x26L2 data prefetches in the I state (misses)l2_data_rqsts.prefetch.m_stateumask=0x80,period=200000,event=0x26L2 data prefetches in M statel2_data_rqsts.prefetch.mesiumask=0xf0,period=200000,event=0x26All L2 data prefetchesl2_data_rqsts.prefetch.s_stateumask=0x20,period=200000,event=0x26L2 data prefetches in the S statel2_lines_in.anyumask=0x7,period=100000,event=0xf1L2 lines alloacatedl2_lines_in.e_stateumask=0x4,period=100000,event=0xf1L2 lines allocated in the E statel2_lines_in.s_stateumask=0x2,period=100000,event=0xf1L2 lines allocated in the S statel2_lines_out.anyumask=0xf,period=100000,event=0xf2L2 lines evictedumask=0x1,period=100000,event=0xf2L2 lines evicted by a demand requestumask=0x2,period=100000,event=0xf2L2 modified lines evicted by a demand requestl2_lines_out.prefetch_cleanumask=0x4,period=100000,event=0xf2L2 lines evicted by a prefetch requestl2_lines_out.prefetch_dirtyumask=0x8,period=100000,event=0xf2L2 modified lines evicted by a prefetch requestl2_rqsts.ifetch_hitumask=0x10,period=200000,event=0x24L2 instruction fetch hitsl2_rqsts.ifetch_missumask=0x20,period=200000,event=0x24L2 instruction fetch missesl2_rqsts.ifetchesumask=0x30,period=200000,event=0x24L2 instruction fetchesl2_rqsts.ld_hitumask=0x1,period=200000,event=0x24L2 load hitsl2_rqsts.ld_missumask=0x2,period=200000,event=0x24L2 load missesl2_rqsts.loadsumask=0x3,period=200000,event=0x24L2 requestsumask=0xaa,period=200000,event=0x24All L2 missesl2_rqsts.prefetch_hitL2 prefetch hitsl2_rqsts.prefetch_missumask=0x80,period=200000,event=0x24L2 prefetch missesl2_rqsts.prefetchesumask=0xc0,period=200000,event=0x24All L2 prefetchesumask=0xff,period=200000,event=0x24umask=0x4,period=200000,event=0x24L2 RFO hitsumask=0x8,period=200000,event=0x24L2 RFO missesl2_rqsts.rfosumask=0xc,period=200000,event=0x24L2 RFO requestsl2_transactions.anyumask=0x80,period=200000,event=0xf0All L2 transactionsl2_transactions.fillumask=0x20,period=200000,event=0xf0L2 fill transactionsl2_transactions.ifetchumask=0x4,period=200000,event=0xf0L2 instruction fetch transactionsl2_transactions.l1d_wbumask=0x10,period=200000,event=0xf0L1D writeback to L2 transactionsl2_transactions.loadumask=0x1,period=200000,event=0xf0L2 Load transactionsl2_transactions.prefetchumask=0x8,period=200000,event=0xf0L2 prefetch transactionsl2_transactions.rfoumask=0x2,period=200000,event=0xf0L2 RFO transactionsl2_transactions.wbumask=0x40,period=200000,event=0xf0L2 writeback to LLC transactionsl2_write.lock.e_stateumask=0x40,period=100000,event=0x27L2 demand lock RFOs in E statel2_write.lock.hitumask=0xe0,period=100000,event=0x27All demand L2 lock RFOs that hit the cachel2_write.lock.i_stateumask=0x10,period=100000,event=0x27L2 demand lock RFOs in I state (misses)l2_write.lock.m_stateumask=0x80,period=100000,event=0x27L2 demand lock RFOs in M statel2_write.lock.mesiumask=0xf0,period=100000,event=0x27All demand L2 lock RFOsl2_write.lock.s_stateumask=0x20,period=100000,event=0x27L2 demand lock RFOs in S statel2_write.rfo.hitumask=0xe,period=100000,event=0x27All L2 demand store RFOs that hit the cachel2_write.rfo.i_stateumask=0x1,period=100000,event=0x27L2 demand store RFOs in I state (misses)l2_write.rfo.m_stateumask=0x8,period=100000,event=0x27L2 demand store RFOs in M statel2_write.rfo.mesiumask=0xf,period=100000,event=0x27All L2 demand store RFOsl2_write.rfo.s_stateumask=0x2,period=100000,event=0x27L2 demand store RFOs in S stateumask=0x41,period=100000,event=0x2eLongest latency cache missLongest latency cache referencemem_inst_retired.loadsumask=0x1,period=2000000,event=0xbInstructions retired which contains a load (Precise Event)mem_inst_retired.storesumask=0x2,period=2000000,event=0xbInstructions retired which contains a store (Precise Event)mem_load_retired.hit_lfbumask=0x40,period=200000,event=0xcbRetired loads that miss L1D and hit an previously allocated LFB (Precise Event)mem_load_retired.l1d_hitumask=0x1,period=2000000,event=0xcbRetired loads that hit the L1 data cache (Precise Event)umask=0x2,period=200000,event=0xcbRetired loads that hit the L2 cache (Precise Event)mem_load_retired.llc_missumask=0x10,period=10000,event=0xcbRetired loads that miss the LLC cache (Precise Event)mem_load_retired.llc_unshared_hitumask=0x4,period=40000,event=0xcbRetired loads that hit valid versions in the LLC cache (Precise Event)mem_load_retired.other_core_l2_hit_hitmumask=0x8,period=40000,event=0xcbRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)mem_uncore_retired.local_dramumask=0x20,period=10000,event=0xfLoad instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)mem_uncore_retired.other_core_l2_hitmumask=0x2,period=40000,event=0xfLoad instructions retired that HIT modified data in sibling core (Precise Event)mem_uncore_retired.remote_cache_local_home_hitumask=0x8,period=20000,event=0xfLoad instructions retired remote cache HIT data source (Precise Event)mem_uncore_retired.remote_dramumask=0x10,period=10000,event=0xfLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)mem_uncore_retired.uncacheableumask=0x80,period=4000,event=0xfLoad instructions retired IO (Precise Event)offcore_requests.l1d_writebackumask=0x40,period=100000,event=0xb0Offcore L1 data cache writebacksoffcore_requests_sq_fullumask=0x1,period=100000,event=0xb2Offcore requests blocked due to Super Queue fullumask=0x10,period=2000000,event=0xf4Super Queue lock splits across a cache linestore_blocks.at_retumask=0x4,period=200000,event=0x6Loads delayed with at-Retirement block codestore_blocks.l1d_blockumask=0x8,period=200000,event=0x6Cacheable loads delayed with L1D block codemem_inst_retired.latency_above_threshold_0umask=0x10,period=2000000,event=0xb,ldlat=0x0Memory instructions retired above 0 clocks (Precise Event)mem_inst_retired.latency_above_threshold_1024umask=0x10,period=100,event=0xb,ldlat=0x400Memory instructions retired above 1024 clocks (Precise Event)mem_inst_retired.latency_above_threshold_128umask=0x10,period=1000,event=0xb,ldlat=0x80Memory instructions retired above 128 clocks (Precise Event)mem_inst_retired.latency_above_threshold_16umask=0x10,period=10000,event=0xb,ldlat=0x10Memory instructions retired above 16 clocks (Precise Event)mem_inst_retired.latency_above_threshold_16384umask=0x10,period=5,event=0xb,ldlat=0x4000Memory instructions retired above 16384 clocks (Precise Event)mem_inst_retired.latency_above_threshold_2048umask=0x10,period=50,event=0xb,ldlat=0x800Memory instructions retired above 2048 clocks (Precise Event)mem_inst_retired.latency_above_threshold_256umask=0x10,period=500,event=0xb,ldlat=0x100Memory instructions retired above 256 clocks (Precise Event)mem_inst_retired.latency_above_threshold_32umask=0x10,period=5000,event=0xb,ldlat=0x20Memory instructions retired above 32 clocks (Precise Event)mem_inst_retired.latency_above_threshold_32768umask=0x10,period=3,event=0xb,ldlat=0x8000Memory instructions retired above 32768 clocks (Precise Event)mem_inst_retired.latency_above_threshold_4umask=0x10,period=50000,event=0xb,ldlat=0x4Memory instructions retired above 4 clocks (Precise Event)mem_inst_retired.latency_above_threshold_4096umask=0x10,period=20,event=0xb,ldlat=0x1000Memory instructions retired above 4096 clocks (Precise Event)mem_inst_retired.latency_above_threshold_512umask=0x10,period=200,event=0xb,ldlat=0x200Memory instructions retired above 512 clocks (Precise Event)mem_inst_retired.latency_above_threshold_64umask=0x10,period=2000,event=0xb,ldlat=0x40Memory instructions retired above 64 clocks (Precise Event)mem_inst_retired.latency_above_threshold_8umask=0x10,period=20000,event=0xb,ldlat=0x8Memory instructions retired above 8 clocks (Precise Event)mem_inst_retired.latency_above_threshold_8192umask=0x10,period=10,event=0xb,ldlat=0x2000Memory instructions retired above 8192 clocks (Precise Event)offcore_response.any_data.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F11Offcore data reads satisfied by any cache or DRAMoffcore_response.any_data.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF11All offcore data readsoffcore_response.any_data.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8011Offcore data reads satisfied by the IO, CSR, MMIO unitoffcore_response.any_data.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x111Offcore data reads satisfied by the LLC and not found in a sibling coreoffcore_response.any_data.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x211Offcore data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.any_data.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x411Offcore data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_data.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x711Offcore data reads satisfied by the LLCoffcore_response.any_data.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4711Offcore data reads satisfied by the LLC or local DRAMoffcore_response.any_data.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1811Offcore data reads satisfied by a remote cacheoffcore_response.any_data.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3811Offcore data reads satisfied by a remote cache or remote DRAMoffcore_response.any_data.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1011Offcore data reads that HIT in a remote cacheoffcore_response.any_data.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x811Offcore data reads that HITM in a remote cacheoffcore_response.any_ifetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F44Offcore code reads satisfied by any cache or DRAMoffcore_response.any_ifetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF44All offcore code readsoffcore_response.any_ifetch.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8044Offcore code reads satisfied by the IO, CSR, MMIO unitoffcore_response.any_ifetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x144Offcore code reads satisfied by the LLC and not found in a sibling coreoffcore_response.any_ifetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x244Offcore code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.any_ifetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x444Offcore code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_ifetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x744Offcore code reads satisfied by the LLCoffcore_response.any_ifetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4744Offcore code reads satisfied by the LLC or local DRAMoffcore_response.any_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1844Offcore code reads satisfied by a remote cacheoffcore_response.any_ifetch.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3844Offcore code reads satisfied by a remote cache or remote DRAMoffcore_response.any_ifetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1044Offcore code reads that HIT in a remote cacheoffcore_response.any_ifetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x844Offcore code reads that HITM in a remote cacheoffcore_response.any_request.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFFOffcore requests satisfied by any cache or DRAMoffcore_response.any_request.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFFFFAll offcore requestsoffcore_response.any_request.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x80FFOffcore requests satisfied by the IO, CSR, MMIO unitoffcore_response.any_request.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1FFOffcore requests satisfied by the LLC and not found in a sibling coreoffcore_response.any_request.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2FFOffcore requests satisfied by the LLC and HIT in a sibling coreoffcore_response.any_request.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4FFOffcore requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_request.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFOffcore requests satisfied by the LLCoffcore_response.any_request.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x47FFOffcore requests satisfied by the LLC or local DRAMoffcore_response.any_request.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x18FFOffcore requests satisfied by a remote cacheoffcore_response.any_request.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x38FFOffcore requests satisfied by a remote cache or remote DRAMoffcore_response.any_request.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x10FFOffcore requests that HIT in a remote cacheoffcore_response.any_request.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8FFOffcore requests that HITM in a remote cacheoffcore_response.any_rfo.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F22Offcore RFO requests satisfied by any cache or DRAMoffcore_response.any_rfo.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF22All offcore RFO requestsoffcore_response.any_rfo.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8022Offcore RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.any_rfo.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x122Offcore RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.any_rfo.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x222Offcore RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.any_rfo.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x422Offcore RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_rfo.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x722Offcore RFO requests satisfied by the LLCoffcore_response.any_rfo.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4722Offcore RFO requests satisfied by the LLC or local DRAMoffcore_response.any_rfo.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1822Offcore RFO requests satisfied by a remote cacheoffcore_response.any_rfo.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3822Offcore RFO requests satisfied by a remote cache or remote DRAMoffcore_response.any_rfo.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1022Offcore RFO requests that HIT in a remote cacheoffcore_response.any_rfo.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x822Offcore RFO requests that HITM in a remote cacheoffcore_response.corewb.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F08Offcore writebacks to any cache or DRAMoffcore_response.corewb.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF08All offcore writebacksoffcore_response.corewb.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8008Offcore writebacks to the IO, CSR, MMIO unitoffcore_response.corewb.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x108Offcore writebacks to the LLC and not found in a sibling coreoffcore_response.corewb.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x408Offcore writebacks to the LLC  and HITM in a sibling coreoffcore_response.corewb.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x708Offcore writebacks to the LLCoffcore_response.corewb.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4708Offcore writebacks to the LLC or local DRAMoffcore_response.corewb.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1808Offcore writebacks to a remote cacheoffcore_response.corewb.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3808Offcore writebacks to a remote cache or remote DRAMoffcore_response.corewb.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1008Offcore writebacks that HIT in a remote cacheoffcore_response.corewb.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x808Offcore writebacks that HITM in a remote cacheoffcore_response.data_ifetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F77Offcore code or data read requests satisfied by any cache or DRAMoffcore_response.data_ifetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF77All offcore code or data read requestsoffcore_response.data_ifetch.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8077Offcore code or data read requests satisfied by the IO, CSR, MMIO unitoffcore_response.data_ifetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x177Offcore code or data read requests satisfied by the LLC and not found in a sibling coreoffcore_response.data_ifetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x277Offcore code or data read requests satisfied by the LLC and HIT in a sibling coreoffcore_response.data_ifetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x477Offcore code or data read requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.data_ifetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x777Offcore code or data read requests satisfied by the LLCoffcore_response.data_ifetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4777Offcore code or data read requests satisfied by the LLC or local DRAMoffcore_response.data_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1877Offcore code or data read requests satisfied by a remote cacheoffcore_response.data_ifetch.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3877Offcore code or data read requests satisfied by a remote cache or remote DRAMoffcore_response.data_ifetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1077Offcore code or data read requests that HIT in a remote cacheoffcore_response.data_ifetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x877Offcore code or data read requests that HITM in a remote cacheoffcore_response.data_in.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F33Offcore request = all data, response = any cache_dramoffcore_response.data_in.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF33Offcore request = all data, response = any locationoffcore_response.data_in.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8033Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unitoffcore_response.data_in.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x133Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling coreoffcore_response.data_in.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x233Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling coreoffcore_response.data_in.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x433Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling coreoffcore_response.data_in.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x733Offcore request = all data, response = local cacheoffcore_response.data_in.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4733Offcore request = all data, response = local cache or dramoffcore_response.data_in.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1833Offcore request = all data, response = remote cacheoffcore_response.data_in.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3833Offcore request = all data, response = remote cache or dramoffcore_response.data_in.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1033Offcore data reads, RFO's and prefetches that HIT in a remote cache offcore_response.data_in.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x833Offcore data reads, RFO's and prefetches that HITM in a remote cacheoffcore_response.demand_data.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F03Offcore demand data requests satisfied by any cache or DRAMoffcore_response.demand_data.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF03All offcore demand data requestsoffcore_response.demand_data.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8003Offcore demand data requests satisfied by the IO, CSR, MMIO unitoffcore_response.demand_data.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x103Offcore demand data requests satisfied by the LLC and not found in a sibling coreoffcore_response.demand_data.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x203Offcore demand data requests satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_data.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x403Offcore demand data requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_data.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x703Offcore demand data requests satisfied by the LLCoffcore_response.demand_data.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4703Offcore demand data requests satisfied by the LLC or local DRAMoffcore_response.demand_data.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1803Offcore demand data requests satisfied by a remote cacheoffcore_response.demand_data.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3803Offcore demand data requests satisfied by a remote cache or remote DRAMoffcore_response.demand_data.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1003Offcore demand data requests that HIT in a remote cacheoffcore_response.demand_data.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x803Offcore demand data requests that HITM in a remote cacheoffcore_response.demand_data_rd.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F01Offcore demand data reads satisfied by any cache or DRAMoffcore_response.demand_data_rd.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF01All offcore demand data readsoffcore_response.demand_data_rd.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8001Offcore demand data reads satisfied by the IO, CSR, MMIO unitoffcore_response.demand_data_rd.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x101Offcore demand data reads satisfied by the LLC and not found in a sibling coreoffcore_response.demand_data_rd.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x201Offcore demand data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_data_rd.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x401Offcore demand data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_data_rd.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x701Offcore demand data reads satisfied by the LLCoffcore_response.demand_data_rd.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4701Offcore demand data reads satisfied by the LLC or local DRAMoffcore_response.demand_data_rd.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1801Offcore demand data reads satisfied by a remote cacheoffcore_response.demand_data_rd.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3801Offcore demand data reads satisfied by a remote cache or remote DRAMoffcore_response.demand_data_rd.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1001Offcore demand data reads that HIT in a remote cacheoffcore_response.demand_data_rd.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x801Offcore demand data reads that HITM in a remote cacheoffcore_response.demand_ifetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F04Offcore demand code reads satisfied by any cache or DRAMoffcore_response.demand_ifetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF04All offcore demand code readsoffcore_response.demand_ifetch.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8004Offcore demand code reads satisfied by the IO, CSR, MMIO unitoffcore_response.demand_ifetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x104Offcore demand code reads satisfied by the LLC and not found in a sibling coreoffcore_response.demand_ifetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x204Offcore demand code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_ifetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x404Offcore demand code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_ifetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x704Offcore demand code reads satisfied by the LLCoffcore_response.demand_ifetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4704Offcore demand code reads satisfied by the LLC or local DRAMoffcore_response.demand_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1804Offcore demand code reads satisfied by a remote cacheoffcore_response.demand_ifetch.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3804Offcore demand code reads satisfied by a remote cache or remote DRAMoffcore_response.demand_ifetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1004Offcore demand code reads that HIT in a remote cacheoffcore_response.demand_ifetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x804Offcore demand code reads that HITM in a remote cacheoffcore_response.demand_rfo.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F02Offcore demand RFO requests satisfied by any cache or DRAMoffcore_response.demand_rfo.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF02All offcore demand RFO requestsoffcore_response.demand_rfo.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8002Offcore demand RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.demand_rfo.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x102Offcore demand RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.demand_rfo.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x202Offcore demand RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_rfo.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x402Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_rfo.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x702Offcore demand RFO requests satisfied by the LLCoffcore_response.demand_rfo.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4702Offcore demand RFO requests satisfied by the LLC or local DRAMoffcore_response.demand_rfo.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1802Offcore demand RFO requests satisfied by a remote cacheoffcore_response.demand_rfo.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3802Offcore demand RFO requests satisfied by a remote cache or remote DRAMoffcore_response.demand_rfo.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1002Offcore demand RFO requests that HIT in a remote cacheoffcore_response.demand_rfo.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x802Offcore demand RFO requests that HITM in a remote cacheoffcore_response.other.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F80Offcore other requests satisfied by any cache or DRAMoffcore_response.other.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF80All offcore other requestsoffcore_response.other.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8080Offcore other requests satisfied by the IO, CSR, MMIO unitoffcore_response.other.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x180Offcore other requests satisfied by the LLC and not found in a sibling coreoffcore_response.other.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x280Offcore other requests satisfied by the LLC and HIT in a sibling coreoffcore_response.other.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x480Offcore other requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.other.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x780Offcore other requests satisfied by the LLCoffcore_response.other.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4780Offcore other requests satisfied by the LLC or local DRAMoffcore_response.other.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1880Offcore other requests satisfied by a remote cacheoffcore_response.other.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3880Offcore other requests satisfied by a remote cache or remote DRAMoffcore_response.other.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1080Offcore other requests that HIT in a remote cacheoffcore_response.other.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x880Offcore other requests that HITM in a remote cacheoffcore_response.pf_data.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F30Offcore prefetch data requests satisfied by any cache or DRAMoffcore_response.pf_data.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF30All offcore prefetch data requestsoffcore_response.pf_data.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8030Offcore prefetch data requests satisfied by the IO, CSR, MMIO unitoffcore_response.pf_data.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x130Offcore prefetch data requests satisfied by the LLC and not found in a sibling coreoffcore_response.pf_data.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x230Offcore prefetch data requests satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_data.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x430Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_data.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x730Offcore prefetch data requests satisfied by the LLCoffcore_response.pf_data.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4730Offcore prefetch data requests satisfied by the LLC or local DRAMoffcore_response.pf_data.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1830Offcore prefetch data requests satisfied by a remote cacheoffcore_response.pf_data.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3830Offcore prefetch data requests satisfied by a remote cache or remote DRAMoffcore_response.pf_data.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1030Offcore prefetch data requests that HIT in a remote cacheoffcore_response.pf_data.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x830Offcore prefetch data requests that HITM in a remote cacheoffcore_response.pf_data_rd.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F10Offcore prefetch data reads satisfied by any cache or DRAMoffcore_response.pf_data_rd.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF10All offcore prefetch data readsoffcore_response.pf_data_rd.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8010Offcore prefetch data reads satisfied by the IO, CSR, MMIO unitoffcore_response.pf_data_rd.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x110Offcore prefetch data reads satisfied by the LLC and not found in a sibling coreoffcore_response.pf_data_rd.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x210Offcore prefetch data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_data_rd.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x410Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_data_rd.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x710Offcore prefetch data reads satisfied by the LLCoffcore_response.pf_data_rd.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4710Offcore prefetch data reads satisfied by the LLC or local DRAMoffcore_response.pf_data_rd.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1810Offcore prefetch data reads satisfied by a remote cacheoffcore_response.pf_data_rd.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3810Offcore prefetch data reads satisfied by a remote cache or remote DRAMoffcore_response.pf_data_rd.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1010Offcore prefetch data reads that HIT in a remote cacheoffcore_response.pf_data_rd.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x810Offcore prefetch data reads that HITM in a remote cacheoffcore_response.pf_ifetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F40Offcore prefetch code reads satisfied by any cache or DRAMoffcore_response.pf_ifetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF40All offcore prefetch code readsoffcore_response.pf_ifetch.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8040Offcore prefetch code reads satisfied by the IO, CSR, MMIO unitoffcore_response.pf_ifetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x140Offcore prefetch code reads satisfied by the LLC and not found in a sibling coreoffcore_response.pf_ifetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x240Offcore prefetch code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_ifetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x440Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_ifetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x740Offcore prefetch code reads satisfied by the LLCoffcore_response.pf_ifetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4740Offcore prefetch code reads satisfied by the LLC or local DRAMoffcore_response.pf_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1840Offcore prefetch code reads satisfied by a remote cacheoffcore_response.pf_ifetch.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3840Offcore prefetch code reads satisfied by a remote cache or remote DRAMoffcore_response.pf_ifetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1040Offcore prefetch code reads that HIT in a remote cacheoffcore_response.pf_ifetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x840Offcore prefetch code reads that HITM in a remote cacheoffcore_response.pf_rfo.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F20Offcore prefetch RFO requests satisfied by any cache or DRAMoffcore_response.pf_rfo.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF20All offcore prefetch RFO requestsoffcore_response.pf_rfo.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8020Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.pf_rfo.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x120Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.pf_rfo.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x220Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_rfo.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x420Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_rfo.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x720Offcore prefetch RFO requests satisfied by the LLCoffcore_response.pf_rfo.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4720Offcore prefetch RFO requests satisfied by the LLC or local DRAMoffcore_response.pf_rfo.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1820Offcore prefetch RFO requests satisfied by a remote cacheoffcore_response.pf_rfo.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3820Offcore prefetch RFO requests satisfied by a remote cache or remote DRAMoffcore_response.pf_rfo.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1020Offcore prefetch RFO requests that HIT in a remote cacheoffcore_response.pf_rfo.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x820Offcore prefetch RFO requests that HITM in a remote cacheoffcore_response.prefetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F70Offcore prefetch requests satisfied by any cache or DRAMoffcore_response.prefetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF70All offcore prefetch requestsoffcore_response.prefetch.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8070Offcore prefetch requests satisfied by the IO, CSR, MMIO unitoffcore_response.prefetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x170Offcore prefetch requests satisfied by the LLC and not found in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x270Offcore prefetch requests satisfied by the LLC and HIT in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x470Offcore prefetch requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.prefetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x770Offcore prefetch requests satisfied by the LLCoffcore_response.prefetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4770Offcore prefetch requests satisfied by the LLC or local DRAMoffcore_response.prefetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1870Offcore prefetch requests satisfied by a remote cacheoffcore_response.prefetch.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3870Offcore prefetch requests satisfied by a remote cache or remote DRAMoffcore_response.prefetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1070Offcore prefetch requests that HIT in a remote cacheoffcore_response.prefetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x870Offcore prefetch requests that HITM in a remote cachefp_assist.allumask=0x1,period=20000,event=0xf7X87 Floating point assists (Precise Event)fp_assist.inputumask=0x4,period=20000,event=0xf7X87 Floating poiint assists for invalid input value (Precise Event)fp_assist.outputumask=0x2,period=20000,event=0xf7X87 Floating point assists for invalid output value (Precise Event)fp_comp_ops_exe.mmxMMX Uopsfp_comp_ops_exe.sse_double_precisionumask=0x80,period=2000000,event=0x10SSE* FP double precision Uopsfp_comp_ops_exe.sse_fpumask=0x4,period=2000000,event=0x10SSE and SSE2 FP Uopsfp_comp_ops_exe.sse_fp_packedumask=0x10,period=2000000,event=0x10SSE FP packed Uopsfp_comp_ops_exe.sse_fp_scalarumask=0x20,period=2000000,event=0x10SSE FP scalar Uopsfp_comp_ops_exe.sse_single_precisionumask=0x40,period=2000000,event=0x10SSE* FP single precision Uopsfp_comp_ops_exe.sse2_integerumask=0x8,period=2000000,event=0x10SSE2 integer UopsComputational floating-point operations executedfp_mmx_trans.anyumask=0x3,period=2000000,event=0xccAll Floating Point to and from MMX transitionsfp_mmx_trans.to_fpumask=0x1,period=2000000,event=0xccTransitions from MMX to Floating Point instructionsfp_mmx_trans.to_mmxumask=0x2,period=2000000,event=0xccTransitions from Floating Point to MMX instructionssimd_int_128.packumask=0x4,period=200000,event=0x12128 bit SIMD integer pack operationssimd_int_128.packed_arithumask=0x20,period=200000,event=0x12128 bit SIMD integer arithmetic operationssimd_int_128.packed_logicalumask=0x10,period=200000,event=0x12128 bit SIMD integer logical operationssimd_int_128.packed_mpyumask=0x1,period=200000,event=0x12128 bit SIMD integer multiply operationssimd_int_128.packed_shiftumask=0x2,period=200000,event=0x12128 bit SIMD integer shift operationssimd_int_128.shuffle_moveumask=0x40,period=200000,event=0x12128 bit SIMD integer shuffle/move operationssimd_int_128.unpackumask=0x8,period=200000,event=0x12128 bit SIMD integer unpack operationssimd_int_64.packumask=0x4,period=200000,event=0xfdSIMD integer 64 bit pack operationssimd_int_64.packed_arithumask=0x20,period=200000,event=0xfdSIMD integer 64 bit arithmetic operationssimd_int_64.packed_logicalumask=0x10,period=200000,event=0xfdSIMD integer 64 bit logical operationssimd_int_64.packed_mpyumask=0x1,period=200000,event=0xfdSIMD integer 64 bit packed multiply operationssimd_int_64.packed_shiftumask=0x2,period=200000,event=0xfdSIMD integer 64 bit shift operationssimd_int_64.shuffle_moveumask=0x40,period=200000,event=0xfdSIMD integer 64 bit shuffle/move operationssimd_int_64.unpackumask=0x8,period=200000,event=0xfdSIMD integer 64 bit unpack operationsmacro_insts.decodedumask=0x1,period=2000000,event=0xd0Instructions decodedmacro_insts.fusions_decodedumask=0x1,period=2000000,event=0xa6Macro-fused instructions decodedtwo_uop_insts_decodedumask=0x1,period=2000000,event=0x19Two Uop instructions decodedoffcore_response.any_data.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6011Offcore data reads satisfied by any DRAMoffcore_response.any_data.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF811Offcore data reads that missed the LLCoffcore_response.any_data.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4011Offcore data reads satisfied by the local DRAMoffcore_response.any_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2011Offcore data reads satisfied by a remote DRAMoffcore_response.any_ifetch.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6044Offcore code reads satisfied by any DRAMoffcore_response.any_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF844Offcore code reads that missed the LLCoffcore_response.any_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4044Offcore code reads satisfied by the local DRAMoffcore_response.any_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2044Offcore code reads satisfied by a remote DRAMoffcore_response.any_request.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x60FFOffcore requests satisfied by any DRAMoffcore_response.any_request.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF8FFOffcore requests that missed the LLCoffcore_response.any_request.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x40FFOffcore requests satisfied by the local DRAMoffcore_response.any_request.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x20FFOffcore requests satisfied by a remote DRAMoffcore_response.any_rfo.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6022Offcore RFO requests satisfied by any DRAMoffcore_response.any_rfo.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF822Offcore RFO requests that missed the LLCoffcore_response.any_rfo.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4022Offcore RFO requests satisfied by the local DRAMoffcore_response.any_rfo.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2022Offcore RFO requests satisfied by a remote DRAMoffcore_response.corewb.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6008Offcore writebacks to any DRAMoffcore_response.corewb.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF808Offcore writebacks that missed the LLCoffcore_response.corewb.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4008Offcore writebacks to the local DRAMoffcore_response.corewb.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2008Offcore writebacks to a remote DRAMoffcore_response.data_ifetch.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6077Offcore code or data read requests satisfied by any DRAMoffcore_response.data_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF877Offcore code or data read requests that missed the LLCoffcore_response.data_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4077Offcore code or data read requests satisfied by the local DRAMoffcore_response.data_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2077Offcore code or data read requests satisfied by a remote DRAMoffcore_response.data_in.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6033Offcore request = all data, response = any DRAMoffcore_response.data_in.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF833Offcore request = all data, response = any LLC missoffcore_response.data_in.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4033Offcore data reads, RFO's and prefetches statisfied by the local DRAMoffcore_response.data_in.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2033Offcore data reads, RFO's and prefetches statisfied by the remote DRAMoffcore_response.demand_data.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6003Offcore demand data requests satisfied by any DRAMoffcore_response.demand_data.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF803Offcore demand data requests that missed the LLCoffcore_response.demand_data.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4003Offcore demand data requests satisfied by the local DRAMoffcore_response.demand_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2003Offcore demand data requests satisfied by a remote DRAMoffcore_response.demand_data_rd.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6001Offcore demand data reads satisfied by any DRAMoffcore_response.demand_data_rd.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF801Offcore demand data reads that missed the LLCoffcore_response.demand_data_rd.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4001Offcore demand data reads satisfied by the local DRAMoffcore_response.demand_data_rd.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2001Offcore demand data reads satisfied by a remote DRAMoffcore_response.demand_ifetch.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6004Offcore demand code reads satisfied by any DRAMoffcore_response.demand_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF804Offcore demand code reads that missed the LLCoffcore_response.demand_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4004Offcore demand code reads satisfied by the local DRAMoffcore_response.demand_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2004Offcore demand code reads satisfied by a remote DRAMoffcore_response.demand_rfo.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6002Offcore demand RFO requests satisfied by any DRAMoffcore_response.demand_rfo.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF802Offcore demand RFO requests that missed the LLCoffcore_response.demand_rfo.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4002Offcore demand RFO requests satisfied by the local DRAMoffcore_response.demand_rfo.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2002Offcore demand RFO requests satisfied by a remote DRAMoffcore_response.other.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6080Offcore other requests satisfied by any DRAMoffcore_response.other.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF880Offcore other requests that missed the LLCoffcore_response.other.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2080Offcore other requests satisfied by a remote DRAMoffcore_response.pf_data.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6030Offcore prefetch data requests satisfied by any DRAMoffcore_response.pf_data.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF830Offcore prefetch data requests that missed the LLCoffcore_response.pf_data.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4030Offcore prefetch data requests satisfied by the local DRAMoffcore_response.pf_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2030Offcore prefetch data requests satisfied by a remote DRAMoffcore_response.pf_data_rd.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6010Offcore prefetch data reads satisfied by any DRAMoffcore_response.pf_data_rd.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF810Offcore prefetch data reads that missed the LLCoffcore_response.pf_data_rd.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4010Offcore prefetch data reads satisfied by the local DRAMoffcore_response.pf_data_rd.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2010Offcore prefetch data reads satisfied by a remote DRAMoffcore_response.pf_ifetch.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6040Offcore prefetch code reads satisfied by any DRAMoffcore_response.pf_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF840Offcore prefetch code reads that missed the LLCoffcore_response.pf_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4040Offcore prefetch code reads satisfied by the local DRAMoffcore_response.pf_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2040Offcore prefetch code reads satisfied by a remote DRAMoffcore_response.pf_rfo.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6020Offcore prefetch RFO requests satisfied by any DRAMoffcore_response.pf_rfo.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF820Offcore prefetch RFO requests that missed the LLCoffcore_response.pf_rfo.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4020Offcore prefetch RFO requests satisfied by the local DRAMoffcore_response.pf_rfo.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2020Offcore prefetch RFO requests satisfied by a remote DRAMoffcore_response.prefetch.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6070Offcore prefetch requests satisfied by any DRAMoffcore_response.prefetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF870Offcore prefetch requests that missed the LLCoffcore_response.prefetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4070Offcore prefetch requests satisfied by the local DRAMoffcore_response.prefetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2070Offcore prefetch requests satisfied by a remote DRAMbpu_clears.earlyumask=0x1,period=2000000,event=0xe8Early Branch Prediciton Unit clearsbpu_clears.lateumask=0x2,period=2000000,event=0xe8Late Branch Prediction Unit clearsbpu_missed_call_retumask=0x1,period=2000000,event=0xe5Branch prediction unit missed call or returnes_reg_renamesumask=0x1,period=2000000,event=0xd5ES segment renamesio_transactionsumask=0x1,period=2000000,event=0x6cI/O transactionsl1i.cycles_stalledumask=0x4,period=2000000,event=0x80L1I instruction fetch stall cyclesl1i.hitsumask=0x1,period=2000000,event=0x80L1I instruction fetch hitsl1i.missesumask=0x2,period=2000000,event=0x80L1I instruction fetch missesl1i.readsumask=0x3,period=2000000,event=0x80L1I Instruction fetcheslarge_itlb.hitLarge ITLB hitload_dispatch.anyumask=0x7,period=2000000,event=0x13All loads dispatchedload_dispatch.mobumask=0x4,period=2000000,event=0x13Loads dispatched from the MOBload_dispatch.rsLoads dispatched that bypass the MOBload_dispatch.rs_delayedumask=0x2,period=2000000,event=0x13Loads dispatched from stage 305partial_address_aliasumask=0x1,period=200000,event=0x7False dependencies due to partial address aliasingrat_stalls.anyumask=0xf,period=2000000,event=0xd2All RAT stall cyclesrat_stalls.flagsumask=0x1,period=2000000,event=0xd2Flag stall cyclesrat_stalls.registersumask=0x2,period=2000000,event=0xd2Partial register stall cyclesrat_stalls.rob_read_portumask=0x4,period=2000000,event=0xd2ROB read port stalls cyclesrat_stalls.scoreboardumask=0x8,period=2000000,event=0xd2Scoreboard stall cyclessb_drain.anyumask=0x7,period=200000,event=0x4All Store buffer stall cyclesseg_rename_stallsumask=0x1,period=2000000,event=0xd4Segment rename stall cyclessnoop_response.hitumask=0x1,period=100000,event=0xb8Thread responded HIT to snoopsnoop_response.hiteumask=0x2,period=100000,event=0xb8Thread responded HITE to snoopsnoop_response.hitmumask=0x4,period=100000,event=0xb8Thread responded HITM to snoopsq_full_stall_cyclesumask=0x1,period=2000000,event=0xf6Super Queue full stall cyclesarith.cycles_div_busyarith.divinv=1,umask=0x1,period=2000000,cmask=1,edge=1,event=0x14Divide Operations executedarith.mulumask=0x2,period=2000000,event=0x14baclear.bad_targetumask=0x2,period=2000000,event=0xe6BACLEAR asserted with bad target addressbaclear.clearBACLEAR asserted, regardless of cause baclear_force_iqumask=0x1,period=2000000,event=0xa7Instruction queue forced BACLEARbr_inst_exec.anyumask=0x7f,period=200000,event=0x88Branch instructions executedbr_inst_exec.condumask=0x1,period=200000,event=0x88Conditional branch instructions executedbr_inst_exec.directumask=0x2,period=200000,event=0x88Unconditional branches executedbr_inst_exec.direct_near_callumask=0x10,period=20000,event=0x88Unconditional call branches executedbr_inst_exec.indirect_near_callumask=0x20,period=20000,event=0x88Indirect call branches executedbr_inst_exec.indirect_non_callumask=0x4,period=20000,event=0x88Indirect non call branches executedbr_inst_exec.near_callsumask=0x30,period=20000,event=0x88Call branches executedbr_inst_exec.non_callsumask=0x7,period=200000,event=0x88All non call branches executedbr_inst_exec.return_nearumask=0x8,period=20000,event=0x88Indirect return branches executedbr_inst_exec.takenumask=0x40,period=200000,event=0x88Taken branches executedumask=0x4,period=200000,event=0xc4Retired branch instructions (Precise Event)umask=0x1,period=200000,event=0xc4Retired conditional branch instructions (Precise Event)umask=0x2,period=20000,event=0xc4Retired near call instructions (Precise Event)br_misp_exec.anyumask=0x7f,period=20000,event=0x89Mispredicted branches executedbr_misp_exec.condumask=0x1,period=20000,event=0x89Mispredicted conditional branches executedbr_misp_exec.directumask=0x2,period=20000,event=0x89Mispredicted unconditional branches executedbr_misp_exec.direct_near_callumask=0x10,period=2000,event=0x89Mispredicted non call branches executedbr_misp_exec.indirect_near_callumask=0x20,period=2000,event=0x89Mispredicted indirect call branches executedbr_misp_exec.indirect_non_callumask=0x4,period=2000,event=0x89Mispredicted indirect non call branches executedbr_misp_exec.near_callsumask=0x30,period=2000,event=0x89Mispredicted call branches executedbr_misp_exec.non_callsumask=0x7,period=20000,event=0x89br_misp_exec.return_nearumask=0x8,period=2000,event=0x89Mispredicted return branches executedbr_misp_exec.takenumask=0x40,period=20000,event=0x89Mispredicted taken branches executedumask=0x2,period=2000,event=0xc5Mispredicted near retired calls (Precise Event)Reference cycles when thread is not halted (fixed counter)cpu_clk_unhalted.ref_pumask=0x1,period=100000,event=0x3cReference base clock (133 Mhz) cycles when thread is not halted (programmable counter)Cycles when thread is not halted (fixed counter)Cycles when thread is not halted (programmable counter)cpu_clk_unhalted.total_cyclesinv=1,umask=0x0,period=2000000,cmask=2,event=0x3cTotal CPU cyclesild_stall.anyumask=0xf,period=2000000,event=0x87Any Instruction Length Decoder stall cyclesumask=0x4,period=2000000,event=0x87Instruction Queue full stall cyclesLength Change Prefix stall cyclesild_stall.mruStall cycles due to BPU MRU bypassild_stall.regenumask=0x8,period=2000000,event=0x87Regen stall cyclesinst_decoded.dec0umask=0x1,period=2000000,event=0x18Instructions that must be decoded by decoder 0inst_queue_write_cyclesumask=0x1,period=2000000,event=0x1eCycles instructions are written to the instruction queueinst_queue_writesumask=0x1,period=2000000,event=0x17Instructions written to instruction queueInstructions retired (fixed counter)Instructions retired (Programmable counter and Precise Event) (Precise event)inst_retired.mmxumask=0x4,period=2000000,event=0xc0Retired MMX instructions (Precise Event)inst_retired.total_cyclesinv=1,umask=0x1,period=2000000,cmask=16,event=0xc0Total cycles (Precise Event)umask=0x2,period=2000000,event=0xc0Retired floating-point operations (Precise Event)load_hit_preumask=0x1,period=200000,event=0x4cLoad operations conflicting with software prefetcheslsd.activeumask=0x1,period=2000000,cmask=1,event=0xa8Cycles when uops were delivered by the LSDlsd.inactiveinv=1,umask=0x1,period=2000000,cmask=1,event=0xa8Cycles no uops were delivered by the LSDlsd_overflowumask=0x1,period=2000000,event=0x20Loops that can't stream from the instruction queueumask=0x1,period=20000,event=0xc3Cycles machine clear assertedmachine_clears.mem_orderumask=0x2,period=20000,event=0xc3Execution pipeline restart due to Memory ordering conflictsumask=0x4,period=20000,event=0xc3umask=0x1,period=2000000,event=0xa2Resource related stall cyclesresource_stalls.fpcwumask=0x20,period=2000000,event=0xa2FPU control word write stall cyclesresource_stalls.loadumask=0x2,period=2000000,event=0xa2Load buffer stall cyclesresource_stalls.mxcsrumask=0x40,period=2000000,event=0xa2MXCSR rename stall cyclesresource_stalls.otherumask=0x80,period=2000000,event=0xa2Other Resource related stall cyclesresource_stalls.rob_fullumask=0x10,period=2000000,event=0xa2ROB full stall cyclesresource_stalls.rs_fullumask=0x4,period=2000000,event=0xa2Reservation Station full stall cyclesresource_stalls.storeumask=0x8,period=2000000,event=0xa2Store buffer stall cyclesssex_uops_retired.packed_doubleumask=0x4,period=200000,event=0xc7SIMD Packed-Double Uops retired (Precise Event)ssex_uops_retired.packed_singleumask=0x1,period=200000,event=0xc7SIMD Packed-Single Uops retired (Precise Event)ssex_uops_retired.scalar_doubleumask=0x8,period=200000,event=0xc7SIMD Scalar-Double Uops retired (Precise Event)ssex_uops_retired.scalar_singleumask=0x2,period=200000,event=0xc7SIMD Scalar-Single Uops retired (Precise Event)ssex_uops_retired.vector_integerumask=0x10,period=200000,event=0xc7SIMD Vector Integer Uops retired (Precise Event)uop_unfusionumask=0x1,period=2000000,event=0xdbUop unfusions due to FP exceptionsuops_decoded.esp_foldingumask=0x4,period=2000000,event=0xd1Stack pointer instructions decodeduops_decoded.esp_syncumask=0x8,period=2000000,event=0xd1Stack pointer sync operationsuops_decoded.ms_cycles_activeumask=0x2,period=2000000,cmask=1,event=0xd1Uops decoded by Microcode Sequenceruops_decoded.stall_cyclesinv=1,umask=0x1,period=2000000,cmask=1,event=0xd1Cycles no Uops are decodeduops_executed.core_active_cyclesumask=0x3f,any=1,period=2000000,cmask=1,event=0xb1Cycles Uops executed on any port (core count)uops_executed.core_active_cycles_no_port5umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1Cycles Uops executed on ports 0-4 (core count)uops_executed.core_stall_countinv=1,umask=0x3f,any=1,period=2000000,cmask=1,edge=1,event=0xb1Uops executed on any port (core count)uops_executed.core_stall_count_no_port5inv=1,umask=0x1f,any=1,period=2000000,cmask=1,edge=1,event=0xb1Uops executed on ports 0-4 (core count)uops_executed.core_stall_cyclesinv=1,umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1Cycles no Uops issued on any port (core count)uops_executed.core_stall_cycles_no_port5inv=1,umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1Cycles no Uops issued on ports 0-4 (core count)uops_executed.port0umask=0x1,period=2000000,event=0xb1Uops executed on port 0uops_executed.port015umask=0x40,period=2000000,event=0xb1Uops issued on ports 0, 1 or 5uops_executed.port015_stall_cyclesinv=1,umask=0x40,period=2000000,cmask=1,event=0xb1Cycles no Uops issued on ports 0, 1 or 5uops_executed.port1umask=0x2,period=2000000,event=0xb1Uops executed on port 1uops_executed.port2_coreumask=0x4,any=1,period=2000000,event=0xb1Uops executed on port 2 (core count)uops_executed.port234_coreumask=0x80,any=1,period=2000000,event=0xb1Uops issued on ports 2, 3 or 4uops_executed.port3_coreumask=0x8,any=1,period=2000000,event=0xb1Uops executed on port 3 (core count)uops_executed.port4_coreumask=0x10,any=1,period=2000000,event=0xb1Uops executed on port 4 (core count)uops_executed.port5umask=0x20,period=2000000,event=0xb1Uops executed on port 5umask=0x1,period=2000000,event=0xeUops issuedinv=1,umask=0x1,any=1,period=2000000,cmask=1,event=0xeCycles no Uops were issued on any threaduops_issued.cycles_all_threadsumask=0x1,any=1,period=2000000,cmask=1,event=0xeCycles Uops were issued on either threaduops_issued.fusedumask=0x2,period=2000000,event=0xeFused Uops issuedinv=1,umask=0x1,period=2000000,cmask=1,event=0xeCycles no Uops were issueduops_retired.active_cyclesumask=0x1,period=2000000,cmask=1,event=0xc2Cycles Uops are being retired (Precise event)umask=0x1,period=2000000,event=0xc2Uops retired (Precise Event)uops_retired.macro_fusedumask=0x4,period=2000000,event=0xc2Macro-fused Uops retired (Precise Event)umask=0x2,period=2000000,event=0xc2Retirement slots used (Precise Event)inv=1,umask=0x1,period=2000000,cmask=1,event=0xc2Cycles Uops are not retiring (Precise Event)inv=1,umask=0x1,period=2000000,cmask=16,event=0xc2Total cycles using precise uop retired event (Precise Event)inst_retired.total_cycles_psdtlb_load_misses.anyumask=0x1,period=200000,event=0x8DTLB load missesdtlb_load_misses.pde_missumask=0x20,period=200000,event=0x8DTLB load miss caused by low part of addressumask=0x10,period=2000000,event=0x8DTLB second level hitumask=0x2,period=200000,event=0x8DTLB load miss page walks completedtlb_misses.anyumask=0x1,period=200000,event=0x49DTLB missesdtlb_misses.stlb_hitumask=0x10,period=200000,event=0x49DTLB first level misses but second level hitdtlb_misses.walk_completedumask=0x2,period=200000,event=0x49DTLB miss page walksitlb_flushumask=0x1,period=2000000,event=0xaeitlb_miss_retiredumask=0x20,period=200000,event=0xc8Retired instructions that missed the ITLB (Precise Event)itlb_misses.anyumask=0x1,period=200000,event=0x85ITLB missumask=0x2,period=200000,event=0x85ITLB miss page walksumask=0x80,period=200000,event=0xcbRetired loads that miss the DTLB (Precise Event)mem_store_retired.dtlb_missRetired stores that miss the DTLB (Precise Event)Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedCounts the RFO (Read-for-Ownership) requests that miss L2 cacheCounts L2 cache misses when fetching instructionsumask=0x38,period=200003,event=0x24Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheCounts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheCounts the RFO (Read-for-Ownership) requests that hit L2 cacheCounts L2 cache hits when fetching instructions, code readsumask=0xd8,period=200003,event=0x24Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheCounts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheCounts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedCounts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesCounts the total number of L2 code requestsRequests from the L1/L2/L3 hardware prefetchers or Load software prefetchesCounts the total number of requests from the L2 hardware prefetchersCore-originated cacheable demand requests missed L3  Spec update: SKL057Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3  Spec update: SKL057Core-originated cacheable demand requests that refer to L3  Spec update: SKL057Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3  Spec update: SKL057L1D miss outstandings duration in cyclesCounts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeCounts duration of L1D miss outstanding in cyclesNumber of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetchNumber of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructionsCounts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replaceCounts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion pointCounts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycleCounts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSCycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncoreCounts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSCycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncoreCounts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSCounts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSCounts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSCounts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoreCounts both cacheable and non-cacheable code read requestsCounts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMCounts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeoffcore_requests.all_requestsumask=0x80,period=100003,event=0xb0Any memory transaction that reached the SQCounts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entriesmem_inst_retired.stlb_miss_loadsRetired load instructions that miss the STLB. (Precise Event)  Supports address when preciseRetired load instructions that miss the STLB  Supports address when precisemem_inst_retired.stlb_miss_storesRetired store instructions that miss the STLB. (Precise Event)  Supports address when preciseRetired store instructions that miss the STLB  Supports address when precisemem_inst_retired.lock_loadsRetired load instructions with locked access. (Precise Event)  Supports address when precisemem_inst_retired.split_loadsRetired load instructions that split across a cacheline boundary. (Precise Event)  Supports address when precisemem_inst_retired.split_storesRetired store instructions that split across a cacheline boundary. (Precise Event)  Supports address when precisemem_inst_retired.all_loadsAll retired load instructions. (Precise Event)  Supports address when precisemem_inst_retired.all_storesAll retired store instructions. (Precise Event)  Supports address when preciseAll retired store instructions  Supports address when precisemem_load_retired.l1_hitRetired load instructions with L1 cache hits as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise (Precise event)Retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)mem_load_retired.l3_hitRetired load instructions with L3 cache hits as data sources  Supports address when precise (Precise event)mem_load_retired.l1_missRetired load instructions missed L1 cache as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that missed in the L1 cache  Supports address when precise (Precise event)Retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)mem_load_retired.l3_missRetired load instructions missed L3 cache as data sources  Supports address when precise (Precise event)mem_load_retired.fb_hitumask=0x40,period=100007,event=0xd1Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_missRetired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_hitRetired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_hitmRetired load instructions which data sources were HitM responses from shared L3  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_noneRetired load instructions which data sources were hits in L3 without snoops required  Supports address when precise (Precise event)mem_load_misc_retired.ucumask=0x4,period=100007,event=0xd4Retired instructions with at least 1 uncacheable load or lock  Supports address when precise (Precise event)Counts L2 writebacks that access L2 cacheumask=0x1f,period=100003,event=0xf1Counts the number of L2 cache lines filling the L2. Counting does not cover rejectsl2_lines_out.silentumask=0x1,period=200003,event=0xf2Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded eventl2_lines_out.non_silentumask=0x2,period=200003,event=0xf2Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3l2_lines_out.useless_prefumask=0x4,period=200003,event=0xf2This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPFl2_lines_out.useless_hwpfCounts the number of lines that have been hardware prefetched but not used and now evicted by L2 cacheNumber of cache line split locks sent to uncoreCounts the number of cache line split locks sent to the uncoreoffcore_response.other.l4_hit_local_l4.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0408000offcore_response.other.l4_hit_local_l4.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000408000offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400408000offcore_response.other.l4_hit_local_l4.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200408000offcore_response.other.l4_hit_local_l4.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100408000offcore_response.other.l4_hit_local_l4.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080408000offcore_response.other.l4_hit_local_l4.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C8000offcore_response.other.l3_hit.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C8000offcore_response.other.l3_hit_s.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0108000offcore_response.other.l3_hit_s.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000108000offcore_response.other.l3_hit_s.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400108000offcore_response.other.l3_hit_s.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200108000offcore_response.other.l3_hit_s.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100108000offcore_response.other.l3_hit_s.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080108000offcore_response.other.l3_hit_s.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040108000offcore_response.other.l3_hit_e.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0088000offcore_response.other.l3_hit_e.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000088000offcore_response.other.l3_hit_e.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400088000offcore_response.other.l3_hit_e.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200088000offcore_response.other.l3_hit_e.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100088000offcore_response.other.l3_hit_e.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080088000offcore_response.other.l3_hit_e.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040088000offcore_response.other.l3_hit_m.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0048000offcore_response.other.l3_hit_m.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000048000offcore_response.other.l3_hit_m.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400048000offcore_response.other.l3_hit_m.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200048000offcore_response.other.l3_hit_m.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100048000offcore_response.other.l3_hit_m.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080048000offcore_response.other.l3_hit_m.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040048000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0028000offcore_response.other.supplier_none.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040028000offcore_response.demand_code_rd.l4_hit_local_l4.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400004Counts demand instruction fetches and L1 instruction cache prefetches thatoffcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_neededoffcore_response.demand_code_rd.l4_hit_local_l4.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400004offcore_response.demand_code_rd.l4_hit_local_l4.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0004offcore_response.demand_code_rd.l3_hit.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0004offcore_response.demand_code_rd.l3_hit_s.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100004offcore_response.demand_code_rd.l3_hit_s.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100004offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100004offcore_response.demand_code_rd.l3_hit_s.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100004offcore_response.demand_code_rd.l3_hit_s.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100004offcore_response.demand_code_rd.l3_hit_s.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100004offcore_response.demand_code_rd.l3_hit_s.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100004offcore_response.demand_code_rd.l3_hit_e.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080004offcore_response.demand_code_rd.l3_hit_e.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080004offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080004offcore_response.demand_code_rd.l3_hit_e.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080004offcore_response.demand_code_rd.l3_hit_e.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080004offcore_response.demand_code_rd.l3_hit_e.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080004offcore_response.demand_code_rd.l3_hit_e.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080004offcore_response.demand_code_rd.l3_hit_m.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040004offcore_response.demand_code_rd.l3_hit_m.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040004offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040004offcore_response.demand_code_rd.l3_hit_m.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040004offcore_response.demand_code_rd.l3_hit_m.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040004offcore_response.demand_code_rd.l3_hit_m.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040004offcore_response.demand_code_rd.l3_hit_m.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020004offcore_response.demand_code_rd.supplier_none.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020004Counts demand instruction fetches and L1 instruction cache prefetches that have any response typeoffcore_response.demand_rfo.l4_hit_local_l4.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_neededoffcore_response.demand_rfo.l4_hit_local_l4.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400002offcore_response.demand_rfo.l4_hit_local_l4.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0002offcore_response.demand_rfo.l3_hit.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0002offcore_response.demand_rfo.l3_hit_s.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100002offcore_response.demand_rfo.l3_hit_s.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100002offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100002offcore_response.demand_rfo.l3_hit_s.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100002offcore_response.demand_rfo.l3_hit_s.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100002offcore_response.demand_rfo.l3_hit_s.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100002offcore_response.demand_rfo.l3_hit_s.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100002offcore_response.demand_rfo.l3_hit_e.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080002offcore_response.demand_rfo.l3_hit_e.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080002offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080002offcore_response.demand_rfo.l3_hit_e.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080002offcore_response.demand_rfo.l3_hit_e.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080002offcore_response.demand_rfo.l3_hit_e.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080002offcore_response.demand_rfo.l3_hit_e.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080002offcore_response.demand_rfo.l3_hit_m.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040002offcore_response.demand_rfo.l3_hit_m.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040002offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040002offcore_response.demand_rfo.l3_hit_m.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040002offcore_response.demand_rfo.l3_hit_m.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040002offcore_response.demand_rfo.l3_hit_m.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040002offcore_response.demand_rfo.l3_hit_m.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040002offcore_response.demand_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020002offcore_response.demand_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020002offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020002offcore_response.demand_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020002offcore_response.demand_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020002offcore_response.demand_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020002offcore_response.demand_rfo.supplier_none.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020002offcore_response.demand_data_rd.l4_hit_local_l4.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_neededoffcore_response.demand_data_rd.l4_hit_local_l4.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400001offcore_response.demand_data_rd.l4_hit_local_l4.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0001offcore_response.demand_data_rd.l3_hit.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0001offcore_response.demand_data_rd.l3_hit_s.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100001offcore_response.demand_data_rd.l3_hit_s.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100001offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100001offcore_response.demand_data_rd.l3_hit_s.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100001offcore_response.demand_data_rd.l3_hit_s.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100001offcore_response.demand_data_rd.l3_hit_s.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100001offcore_response.demand_data_rd.l3_hit_s.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100001offcore_response.demand_data_rd.l3_hit_e.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080001offcore_response.demand_data_rd.l3_hit_e.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080001offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080001offcore_response.demand_data_rd.l3_hit_e.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080001offcore_response.demand_data_rd.l3_hit_e.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080001offcore_response.demand_data_rd.l3_hit_e.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080001offcore_response.demand_data_rd.l3_hit_e.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080001offcore_response.demand_data_rd.l3_hit_m.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040001offcore_response.demand_data_rd.l3_hit_m.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040001offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040001offcore_response.demand_data_rd.l3_hit_m.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040001offcore_response.demand_data_rd.l3_hit_m.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040001offcore_response.demand_data_rd.l3_hit_m.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040001offcore_response.demand_data_rd.l3_hit_m.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020001offcore_response.demand_data_rd.supplier_none.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020001Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQCounts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQCounts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQCounts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQCounts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQCounts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQCounts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITECounts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MSicache_16b.ifdata_stallCycles where a code fetch is stalled due to L1 instruction cache missCycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularityicache_64b.iftag_hitumask=0x1,period=200003,event=0x83Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityicache_64b.iftag_missumask=0x2,period=200003,event=0x83Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityicache_64b.iftag_stallumask=0x4,period=200003,event=0x83Cycles where a code fetch is stalled due to L1 instruction cache tag missCounts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uopsCounts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3Cycles with less than 2 uops delivered by the front-endCycles with less than 3 uops delivered by the front-endCounts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cyclesfrontend_retired.dsb_missumask=0x1,period=100007,event=0xc6,frontend=0x11Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event (Precise event)Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event)frontend_retired.l1i_missumask=0x1,period=100007,event=0xc6,frontend=0x12Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event (Precise event)frontend_retired.l2_missumask=0x1,period=100007,event=0xc6,frontend=0x13Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event (Precise event)frontend_retired.itlb_missumask=0x1,period=100007,event=0xc6,frontend=0x14Retired Instructions who experienced iTLB true miss. Precise Event (Precise event)Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event)frontend_retired.stlb_missumask=0x1,period=100007,event=0xc6,frontend=0x15Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event (Precise event)Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event)frontend_retired.latency_ge_2umask=0x1,period=100007,event=0xc6,frontend=0x400206Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_2_bubbles_ge_2umask=0x1,period=100007,event=0xc6,frontend=0x200206Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_4umask=0x1,period=100007,event=0xc6,frontend=0x400406Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_8umask=0x1,period=100007,event=0xc6,frontend=0x400806Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.latency_ge_16umask=0x1,period=100007,event=0xc6,frontend=0x401006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.latency_ge_32umask=0x1,period=100007,event=0xc6,frontend=0x402006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)Counts retired instructions that are delivered to the back-end  after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.latency_ge_64umask=0x1,period=100007,event=0xc6,frontend=0x404006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_128umask=0x1,period=100007,event=0xc6,frontend=0x408006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_256umask=0x1,period=100007,event=0xc6,frontend=0x410006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_512umask=0x1,period=100007,event=0xc6,frontend=0x420006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)frontend_retired.latency_ge_2_bubbles_ge_1umask=0x1,period=100007,event=0xc6,frontend=0x100206Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event)frontend_retired.latency_ge_2_bubbles_ge_3umask=0x1,period=100007,event=0xc6,frontend=0x300206Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event)tx_mem.abort_capacityNumber of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writesUnfriendly TSX abort triggered by a vzeroupper instructionoffcore_requests_outstanding.l3_miss_demand_data_rdumask=0x10,period=2000003,event=0x60Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycleoffcore_requests_outstanding.cycles_with_l3_miss_demand_data_rdumask=0x10,period=2000003,cmask=1,event=0x60Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQoffcore_requests_outstanding.l3_miss_demand_data_rd_ge_6umask=0x10,period=2000003,cmask=6,event=0x60Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQcycle_activity.cycles_l3_missCycles while L3 cache miss demand load is outstandingcycle_activity.stalls_l3_missExecution stalls while L3 cache miss demand load is outstandingoffcore_requests.l3_miss_demand_data_rdumask=0x10,period=100003,event=0xb0Demand Data Read requests who miss L3 cacheCounts the number of machine clears due to memory order conflicts  Spec update: SKL089Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer  Spec update: SKL089Number of times we entered an HLE region. Does not count nested transactionsNumber of times HLE abort was triggered. (PEBS) (Precise event)hle_retired.aborted_memhle_retired.aborted_timerNumber of times an HLE execution aborted due to hardware timer expirationhle_retired.aborted_unfriendlyNumber of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)hle_retired.aborted_memtypehle_retired.aborted_eventsNumber of times an HLE execution aborted due to unfriendly events (such as interrupts)Number of times we entered an RTM region. Does not count nested transactionsNumber of times RTM abort was triggered. (PEBS) (Precise event)rtm_retired.aborted_memrtm_retired.aborted_timerNumber of times an RTM execution aborted due to uncommon conditionsrtm_retired.aborted_unfriendlyrtm_retired.aborted_memtypertm_retired.aborted_eventsCounts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency (Must be precise)offcore_response.other.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC408000offcore_response.other.l3_miss.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C408000offcore_response.other.l3_miss.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC408000offcore_response.other.l3_miss.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4008000offcore_response.other.l3_miss_local_dram.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044008000offcore_response.other.l4_hit_local_l4.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000408000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C8000offcore_response.other.l3_hit_s.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000108000offcore_response.other.l3_hit_e.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000088000offcore_response.other.l3_hit_m.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000048000offcore_response.demand_code_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400004offcore_response.demand_code_rd.l3_miss.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400004offcore_response.demand_code_rd.l3_miss.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400004offcore_response.demand_code_rd.l3_miss.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000004offcore_response.demand_code_rd.l3_miss_local_dram.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0004offcore_response.demand_code_rd.l3_hit_s.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100004offcore_response.demand_code_rd.l3_hit_e.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080004offcore_response.demand_code_rd.l3_hit_m.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040004offcore_response.demand_rfo.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400002offcore_response.demand_rfo.l3_miss.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400002offcore_response.demand_rfo.l3_miss.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400002offcore_response.demand_rfo.l3_miss.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000002offcore_response.demand_rfo.l3_miss_local_dram.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000002offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0002offcore_response.demand_rfo.l3_hit_s.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100002offcore_response.demand_rfo.l3_hit_e.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080002offcore_response.demand_rfo.l3_hit_m.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040002offcore_response.demand_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020002offcore_response.demand_data_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400001offcore_response.demand_data_rd.l3_miss.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400001offcore_response.demand_data_rd.l3_miss.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400001offcore_response.demand_data_rd.l3_miss.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000001offcore_response.demand_data_rd.l3_miss_local_dram.spl_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0001offcore_response.demand_data_rd.l3_hit_s.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100001offcore_response.demand_data_rd.l3_hit_e.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080001offcore_response.demand_data_rd.l3_hit_m.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040001sw_prefetch_access.ntaumask=0x1,period=2000003,event=0x32Number of PREFETCHNTA instructions executedsw_prefetch_access.t0umask=0x2,period=2000003,event=0x32Number of PREFETCHT0 instructions executedsw_prefetch_access.t1_t2umask=0x4,period=2000003,event=0x32Number of PREFETCHT1 or PREFETCHT2 instructions executedsw_prefetch_access.prefetchwumask=0x8,period=2000003,event=0x32Number of PREFETCHW instructions executedNumber of hardware interrupts received by the processorCounts the number of hardware interruptions received by the processorCounts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructionsCounts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseLoads blocked by overlapping with store buffer that cannot be forwarded Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization GuideCounts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedumask=0x1,period=2000003,event=0xdCore cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventumask=0x1,any=1,period=2000003,event=0xdint_misc.clear_resteer_cyclesumask=0x80,period=2000003,event=0xdCycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear eventsCounts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS)Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threaduops_issued.vector_width_mismatchumask=0x2,period=2000003,event=0xeUops inserted at issue-stage in order to preserve upper bits of vector registersCounts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guidearith.divider_activeumask=0x1,period=2000003,cmask=1,event=0x14Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationscpu_clk_unhalted.ring0_transumask=0x0,edge=1,period=100007,cmask=1,event=0x3cCounts when there is a transition from ring 1, 2 or 3 to ring 0Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel)umask=0x1,period=2503,event=0x3cCore crystal clock cycles when the thread is unhaltedumask=0x1,any=1,period=2503,event=0x3cCore crystal clock cycles when at least one thread on the physical core is unhaltedCore crystal clock cycles when this thread is unhalted and the other thread is haltedumask=0x2,period=2503,event=0x3cDemand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCounts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructionspartial_rat_stalls.scoreboardumask=0x1,period=2000003,event=0x59Cycles where the pipeline is stalled due to serializing operationsThis event counts cycles during which the microcode scoreboard stalls happenCounts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesCounts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issuesCounts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunkCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7Counts resource-related stall cyclesCounts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-endumask=0x10,period=2000003,cmask=16,event=0xa3umask=0x14,period=2000003,cmask=20,event=0xa3exe_activity.exe_bound_0_portsumask=0x1,period=2000003,event=0xa6Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding loadCounts cycles during which no uops were executed on all ports and Reservation Station (RS) was not emptyexe_activity.1_ports_utilumask=0x2,period=2000003,event=0xa6Cycles total of 1 uop is executed on all ports and Reservation Station was not emptyCounts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not emptyexe_activity.2_ports_utilumask=0x4,period=2000003,event=0xa6Cycles total of 2 uops are executed on all ports and Reservation Station was not emptyCounts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not emptyexe_activity.3_ports_utilumask=0x8,period=2000003,event=0xa6Cycles total of 3 uops are executed on all ports and Reservation Station was not emptyCycles total of 3 uops are executed on all ports and Reservation Station (RS) was not emptyexe_activity.4_ports_utilumask=0x10,period=2000003,event=0xa6Cycles total of 4 uops are executed on all ports and Reservation Station was not emptyCycles total of 4 uops are executed on all ports and Reservation Station (RS) was not emptyexe_activity.bound_on_storesumask=0x40,period=2000003,event=0xa6Cycles where the Store Buffer was full and no outstanding loadNumber of uops delivered to the back-end by the LSD(Loop Stream Detector)Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector)Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector)Counts cycles during which no uops were dispatched from the Reservation Station (RS) per threadinv=1,umask=0x2,period=2000003,cmask=1,event=0xb1uops_executed.x87umask=0x10,period=2000003,event=0xb1Counts the number of x87 uops dispatchedCounts the number of x87 uops executedNumber of instructions retired. General Counter - architectural event  Spec update: SKL091, SKL044Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: SKL091, SKL044Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: SKL091, SKL044 (Must be precise)A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled  Spec update: SKL091, SKL044 (Must be precise)inv=1,umask=0x1,period=2000003,cmask=10,event=0xc0Number of cycles using always true condition applied to  PEBS instructions retired event  Spec update: SKL091, SKL044 (Must be precise)Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)  Spec update: SKL091, SKL044 (Must be precise)other_assists.anyumask=0x3f,period=100003,event=0xc1Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assistsRetirement slots usedCounts the retirement slots usedinv=1,umask=0x2,period=2000003,cmask=1,event=0xc2inv=1,umask=0x2,period=2000003,cmask=10,event=0xc2Counts self-modifying code (SMC) detected, which causes a machine clearAll (macro) branch instructions retired  Spec update: SKL091Counts all (macro) branch instructions retired  Spec update: SKL091Conditional branch instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired  Spec update: SKL091 (Precise event)Direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)All (macro) branch instructions retired  Spec update: SKL091 (Must be precise)This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: SKL091 (Must be precise)Return instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts return instructions retired  Spec update: SKL091 (Precise event)Counts all not taken macro branch instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired  Spec update: SKL091 (Precise event)Taken branch instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired  Spec update: SKL091 (Precise event)Counts the number of far branch instructions retired  Spec update: SKL091 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired  Spec update: SKL091 (Precise event)Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct pathumask=0x2,period=400009,event=0xc5Mispredicted direct and indirect near call instructions retired (Precise event)This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event)Increments whenever there is an update to the LBR arrayIncrements when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECTrob_misc_events.pause_instumask=0x40,period=2000003,event=0xccNumber of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL productsumask=0x1,period=100003,event=0xe6Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymoreskl metricsmin( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 64 * ( icache_64b.iftag_hit + icache_64b.iftag_miss ) / 4.1 ) )idq.dsb_uops / (idq.dsb_uops + idq.mite_uops + idq.ms_uops)inst_retired.any / mem_inst_retired.all_loadsinst_retired.any / mem_inst_retired.all_storesuops_executed.thread / (( uops_executed.core_cycles_ge_1 / 2 ) if #smt_on else uops_executed.core_cycles_ge_1)( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branches( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branchesl1d_pend_miss.pending / ( mem_load_retired.l1_miss + mem_load_retired.fb_hit )( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * cycles )( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) )64 * offcore_requests.all_requests / 1000000000 / duration_timeL3_Cache_Access_BW1000 * mem_load_retired.l1_miss / inst_retired.any1000 * mem_load_retired.l2_miss / inst_retired.any1000 * mem_load_retired.l3_miss / inst_retired.anyarb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,thresh\=1@Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions. )inst_retired.any / ( br_inst_retired.far_branch / 2 )IpFarBranchUnit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficEach cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficCounts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedPage walk completed due to a demand data load to a 4K pageCounts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultPage walk completed due to a demand data load to a 2M/4M pageCounts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page faultPage walk completed due to a demand data load to a 1G pageLoad miss in all TLB levels causes a page walk that completes. (All page sizes)Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a faultCounts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecturedtlb_load_misses.walk_activeumask=0x10,period=100003,cmask=1,event=0x8Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in SkylakeCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a loadLoads that miss the DTLB and hit the STLBCounts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB)Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedPage walk completed due to a demand data store to a 2M/4M pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page faultPage walk completed due to a demand data store to a 1G pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page faultStore misses in all TLB levels causes a page walk that completes. (All page sizes)Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a faultumask=0x10,period=2000003,event=0x49Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecturedtlb_store_misses.walk_activeumask=0x10,period=100003,cmask=1,event=0x49Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a storeStores that miss the DTLB and hit the STLBStores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request typeCounts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request typeCounts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completedCounts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a faultCounts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a faultCode miss in all TLB levels causes a page walk that completes. (1G)Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a faultCode miss in all TLB levels causes a page walk that completes. (All page sizes)Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a faultCounts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitectureitlb_misses.walk_activeumask=0x10,period=100003,cmask=1,event=0x85Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in SkylakeCycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitectureInstruction fetch requests that miss the ITLB and hit the STLBCounts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)Counts the number of DTLB flush attempts of the thread-specific entriesCounts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.)Counts the number of request from the L2 that were not accepted into the XQThis event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)Counts the number of request that were not accepted into the L2Q because the L2Q is FULLCounts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)L2 cache requests from this coreThis event counts requests originating from the core that references a cache line in the L2 cacheThis event counts the total number of L2 cache references and the number of L2 cache misses respectivelyCounts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsrehabq.ld_block_st_forwardLoads blocked due to store forward restriction (Precise event)This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event)rehabq.ld_block_std_notreadyLoads blocked due to store data not readyThis event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right timerehabq.st_splitsStore uops that split cache line boundaryThis event counts the number of retire stores that experienced cache line boundary splitsrehabq.ld_splitsLoad uops that split cache line boundary (Precise event)This event counts the number of retire loads that experienced cache line boundary splits (Precise event)rehabq.lockUops with lock semanticsThis event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0)rehabq.sta_fullStore address buffer fullThis event counts the number of retired stores that are delayed because there is not a store address buffer availablerehabq.any_ldAny reissued load uopsThis event counts the number of load uops reissued from Rehabqrehabq.any_stAny reissued store uopsThis event counts the number of store uops reissued from RehabqLoads missed L1This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedLoads hit L2 (Precise event)This event counts the number of load ops retired that hit in the L2 (Precise event)Loads missed L2 (Precise event)This event counts the number of load ops retired that miss in the L2 (Precise event)mem_uops_retired.utlb_missLoads missed UTLBThis event counts the number of load ops retired that had UTLB missCross core or cross module hitm (Precise event)This event counts the number of load ops retired that got data from the other core or from the other module (Precise event)All LoadsThis event counts the number of load ops retiredAll StoresThis event counts the number of store ops retiredoffcore_response.any_code_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000044Counts any code reads (demand & prefetch) that miss L2offcore_response.any_code_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000044Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheoffcore_response.any_code_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000044Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_code_rd.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000044Counts any code reads (demand & prefetch) that miss L2 with a snoop miss responseCounts any code reads (demand & prefetch) that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000022Counts any rfo reads (demand & prefetch) that miss L2Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_rfo.l2_miss.snoop_missCounts any rfo reads (demand & prefetch) that miss L2 with a snoop miss responseCounts any rfo reads (demand & prefetch) that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680003091Counts any data read (demand & prefetch) that miss L2Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_data_rd.l2_miss.snoop_missCounts any data read (demand & prefetch) that miss L2 with a snoop miss responseCounts any data read (demand & prefetch) that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680004800Counts streaming store that miss L2umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008008Counts any request that hit in the other module where modified copies were found in other core's L1 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008008Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_request.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008008Counts any request that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018008Counts any request that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680002000Counts DCU hardware prefetcher data read that miss L2Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cacheCounts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l1_data_rd.l2_miss.snoop_missCounts DCU hardware prefetcher data read that miss L2 with a snoop miss responseCounts DCU hardware prefetcher data read that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000100Countsof demand RFO requests to write to partial cache lines that miss L2umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000080Counts demand reads of partial cache lines (including UC and WC) that miss L2offcore_response.pf_l2_code_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000040Counts code reads generated by L2 prefetchers that miss L2offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000040Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_code_rd.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000040Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000020Counts RFO requests generated by L2 prefetchers that miss L2Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheCounts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_rfo.l2_miss.snoop_missCounts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000010Counts data cacheline reads generated by L2 prefetchers that miss L2Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheCounts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_data_rd.l2_miss.snoop_missCounts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000008Counts writeback (modified to exclusive) that miss L2offcore_response.corewb.l2_miss.no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080000008Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related informationCounts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000004Counts demand and DCU prefetch instruction cacheline that miss L2Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_code_rd.l2_miss.snoop_missCounts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss responseCounts demand and DCU prefetch instruction cacheline that have any response typeCounts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000002Counts demand and DCU prefetch RFOs that miss L2Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.l2_miss.snoop_missCounts demand and DCU prefetch RFOs that miss L2 with a snoop miss responseCounts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000001Counts demand and DCU prefetch data read that miss L2Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_data_rd.l2_miss.snoop_missCounts demand and DCU prefetch data read that miss L2 with a snoop miss responseCounts demand and DCU prefetch data read that have any response typeThis event counts all instruction fetches, not including most uncacheable
fetchesInstruction fetches from IcacheThis event counts all instruction fetches from the instruction cacheThis event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstandingCounts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative countCounts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructionsCounts the number of times a decode restriction reduced the decode throughput due to wrong instruction length predictionStalls due to Memory orderingThis event counts the number of times that pipeline was cleared due to memory ordering issuesumask=0x3f,period=200003,event=0x86Counts the number of branch instructions retired.. (Precise event)ALL_BRANCHES counts the number of any branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of JCC branch instructions retired (Precise event)JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of taken JCC branch instructions retired (Precise event)TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)CALL counts the number of near CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)REL_CALL counts the number of near relative CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)IND_CALL counts the number of near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)RETURN counts the number of near RET branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event)NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted JCC branch instructions retired (Precise event)JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted taken JCC branch instructions retired (Precise event)TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)RETURN counts the number of mispredicted near RET branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event)NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)MSROM micro-ops retiredThis event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-opsThis event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processorsStalls due to FP assistsThis event counts the number of times that pipeline stalled due to FP operations needing assistsCounts all machine clearsMachine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions "older" than this one will be allowed to finish.  This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANYCounts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredictedCounts the number of cycles when no uops are allocated and a RATstall is assertedumask=0x50,period=200003,event=0xcaCounts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocationThe NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidthumask=0x3f,period=200003,event=0xcaCounts the number of cycles when no uops are allocated for any reasonThe NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycleCounts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to MCounts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event countsThis event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlersCycles the divider is busy.  Does not imply a stall waiting for the dividerCycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructionsThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_PCounts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFCounts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFThis event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to timeThis event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the timeCounts the number of baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branchCounts the number of RETURN baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclearsCounts the number of JCC baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclearsALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise)Loads missed DTLB (Precise event)This event counts the number of load ops retired that had DTLB miss (Precise event)D-side page-walksThis event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksDuration of D-side page-walks in core cyclesThis event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksI-side page-walksThis event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksDuration of I-side page-walks in core cyclesThis event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksTotal page walks that are completed (I-side and D-side)This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksTotal cycles for all the page walks. (I-side and D-side)This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this eventRetired load uops that miss the STLB. (Precise Event - PEBS) (Precise event)Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event)Retired load uops with locked access. (Precise Event - PEBS) (Precise event)Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)All retired load uops. (Precise Event - PEBS) (Precise event)This event counts the number of load uops retired (Precise Event) (Precise event)All retired store uops. (Precise Event - PEBS) (Precise event)This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event)Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event)Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)mem_load_uops_misc_retired.llc_missumask=0x2,period=100007,event=0xd4Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event)This event counts retired demand loads that missed the  last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event)offcore_response.all_code_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0244Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0244Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.all_pf_code_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0240Counts all prefetch code reads that hit in the LLCoffcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0240Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_code_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0240Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0240Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0240Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch data reads that hit in the LLCCounts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.all_pf_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0120Counts all prefetch RFOs that hit in the LLCoffcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0120Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_rfo.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0120Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0120Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0120Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCOREWB & ANY_RESPONSEumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0004Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0004Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0004Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2380408000offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_code_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch (that bring data to L2) data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0020Counts all prefetch (that bring data to L2) RFOs that hit in the LLCoffcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_rfo.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_code_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch (that bring data to LLC only) data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0100Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLCoffcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_rfo.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all demand data reads Counts all demand rfo's Counts all demand & prefetch prefetch RFOs Counts all data/code/rfo references (demand & prefetch) offcore_response.data_in.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10433REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSEoffcore_response.demand_rfo.llc_hit_m.hitmREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITMoffcore_response.pf_ifetch.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10040REQUEST = PF_RFO and RESPONSE = ANY_RESPONSEoffcore_response.pf_l_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10080REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSEoffcore_response.pf_l_ifetch.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10200REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSEThis event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more informationNumber of any page walk that had a miss in LLC. Does not necessary cause a SUSPENDoffcore_response.all_pf_code_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400240Counts all prefetch code reads that miss the LLC  and the data returned from dramoffcore_response.all_pf_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400090Counts all prefetch data reads that miss the LLC  and the data returned from dramoffcore_response.all_pf_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400120Counts all prefetch RFOs that miss the LLC  and the data returned from dramoffcore_response.all_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400122Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dramoffcore_response.demand_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400002Counts demand data writes (RFOs) that miss the LLC and the data returned from dramoffcore_response.pf_l2_code_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400040Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dramoffcore_response.pf_l2_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400010Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dramoffcore_response.pf_l2_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400020Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dramoffcore_response.pf_llc_code_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400200Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dramoffcore_response.pf_llc_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400080Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dramoffcore_response.pf_llc_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400100Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dramThis event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAMoffcore_response.any_request.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80408fffREQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMThis event counts any requests that miss the LLC where the data was returned from local DRAMoffcore_response.data_in_socket.llc_miss_local.any_llc_hitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x17004001b3REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIToffcore_response.demand_ifetch.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400004REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_data_rd.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400010REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_ifetch.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400040REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_l_data_rd.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400080REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_l_ifetch.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400200REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel® 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel® 64 and IA-32 Architectures Optimization Reference ManualThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionsActually retired uops. (Precise Event - PEBS) (Precise event)This event counts the number of micro-ops retired. (Precise Event) (Precise event)This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event)Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event)Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event)Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event)snb metricsoffcore_requests.anyumask=0x80,period=100000,event=0xb0offcore_requests.any.readumask=0x8,period=100000,event=0xb0Offcore read requestsoffcore_requests.any.rfoumask=0x10,period=100000,event=0xb0Offcore RFO requestsoffcore_requests.demand.read_codeumask=0x2,period=100000,event=0xb0Offcore demand code read requestsoffcore_requests.demand.read_dataumask=0x1,period=100000,event=0xb0Offcore demand data read requestsoffcore_requests.demand.rfoumask=0x4,period=100000,event=0xb0Offcore demand RFO requestsoffcore_requests_outstanding.any.readumask=0x8,period=2000000,event=0x60Outstanding offcore readsoffcore_requests_outstanding.any.read_not_emptyumask=0x8,period=2000000,cmask=1,event=0x60Cycles offcore reads busyoffcore_requests_outstanding.demand.read_codeumask=0x2,period=2000000,event=0x60Outstanding offcore demand code readsoffcore_requests_outstanding.demand.read_code_not_emptyumask=0x2,period=2000000,cmask=1,event=0x60Cycles offcore demand code read busyoffcore_requests_outstanding.demand.read_dataumask=0x1,period=2000000,event=0x60Outstanding offcore demand data readsoffcore_requests_outstanding.demand.read_data_not_emptyumask=0x1,period=2000000,cmask=1,event=0x60Cycles offcore demand data read busyoffcore_requests_outstanding.demand.rfoumask=0x4,period=2000000,event=0x60Outstanding offcore demand RFOsoffcore_requests_outstanding.demand.rfo_not_emptyumask=0x4,period=2000000,cmask=1,event=0x60Cycles offcore demand RFOs busysq_misc.lru_hintsumask=0x4,period=2000000,event=0xf4Super Queue LRU hints sent to LLCoffcore_response.any_data.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5011REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f11REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff11REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATIONREQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIOREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHEoffcore_response.any_data.local_dram_and_remote_cache_hitREQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_ifetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5044REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f44REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff44REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATIONREQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.any_ifetch.local_dram_and_remote_cache_hitREQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_request.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x50ffREQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7fffREQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xffffREQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATIONumask=0x1,period=100000,event=0xb7,offcore_rsp=0x80ffREQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIOumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7ffREQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHEoffcore_response.any_request.local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x10ffREQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8ffREQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_rfo.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5022REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f22REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff22REQUEST = ANY RFO and RESPONSE = ANY_LOCATIONREQUEST = ANY RFO and RESPONSE = IO_CSR_MMIOREQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY RFO and RESPONSE = LOCAL_CACHEoffcore_response.any_rfo.local_dram_and_remote_cache_hitREQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.corewb.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5008REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f08REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff08REQUEST = CORE_WB and RESPONSE = ANY_LOCATIONREQUEST = CORE_WB and RESPONSE = IO_CSR_MMIOREQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_COREoffcore_response.corewb.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x208REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = CORE_WB and RESPONSE = LOCAL_CACHEoffcore_response.corewb.local_dram_and_remote_cache_hitREQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITMoffcore_response.data_ifetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5077REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f77REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff77REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.data_ifetch.local_dram_and_remote_cache_hitREQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.data_in.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5033REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f33REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff33REQUEST = DATA_IN and RESPONSE = ANY_LOCATIONREQUEST = DATA_IN and RESPONSE = IO_CSR_MMIOREQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IN and RESPONSE = LOCAL_CACHEoffcore_response.data_in.local_dram_and_remote_cache_hitREQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_data.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5003REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f03REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff03REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHEoffcore_response.demand_data.local_dram_and_remote_cache_hitREQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_data_rd.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5001REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f01REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff01REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHEoffcore_response.demand_data_rd.local_dram_and_remote_cache_hitREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_ifetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5004REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f04REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff04REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.demand_ifetch.local_dram_and_remote_cache_hitREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_rfo.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5002REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f02REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff02REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHEoffcore_response.demand_rfo.local_dram_and_remote_cache_hitREQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.other.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5080REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f80REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff80REQUEST = OTHER and RESPONSE = ANY_LOCATIONREQUEST = OTHER and RESPONSE = IO_CSR_MMIOREQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = OTHER and RESPONSE = LOCAL_CACHEoffcore_response.other.local_dram_and_remote_cache_hitREQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_data.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5050REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f50REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff50REQUEST = PF_DATA and RESPONSE = ANY_LOCATIONumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8050REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIOumask=0x1,period=100000,event=0xb7,offcore_rsp=0x150REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x250REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x450REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x750REQUEST = PF_DATA and RESPONSE = LOCAL_CACHEoffcore_response.pf_data.local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1050REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x850REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_data_rd.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5010REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f10REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff10REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHEoffcore_response.pf_data_rd.local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_ifetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5040REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f40REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff40REQUEST = PF_RFO and RESPONSE = ANY_LOCATIONREQUEST = PF_RFO and RESPONSE = IO_CSR_MMIOREQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_RFO and RESPONSE = LOCAL_CACHEoffcore_response.pf_ifetch.local_dram_and_remote_cache_hitREQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_rfo.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5020REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f20REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff20REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.pf_rfo.local_dram_and_remote_cache_hitREQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.prefetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5070REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f70REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff70REQUEST = PREFETCH and RESPONSE = ANY_LOCATIONREQUEST = PREFETCH and RESPONSE = IO_CSR_MMIOREQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PREFETCH and RESPONSE = LOCAL_CACHEoffcore_response.prefetch.local_dram_and_remote_cache_hitREQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITMmisalign_mem_ref.storeumask=0x2,period=200000,event=0x5Misaligned store referencesoffcore_response.any_data.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3011REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf811REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISSoffcore_response.any_data.other_local_dramREQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAMoffcore_response.any_ifetch.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3044REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf844REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.any_ifetch.other_local_dramREQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.any_request.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x30ffREQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf8ffREQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISSoffcore_response.any_request.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x40ffREQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x20ffREQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAMoffcore_response.any_rfo.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3022REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf822REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISSoffcore_response.any_rfo.other_local_dramREQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY RFO and RESPONSE = REMOTE_DRAMoffcore_response.corewb.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3008REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf808REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISSoffcore_response.corewb.other_local_dramREQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAMREQUEST = CORE_WB and RESPONSE = REMOTE_DRAMoffcore_response.data_ifetch.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3077REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf877REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.data_ifetch.other_local_dramREQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.data_in.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3033REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf833REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISSoffcore_response.data_in.other_local_dramREQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IN and RESPONSE = REMOTE_DRAMoffcore_response.demand_data.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3003REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf803REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISSoffcore_response.demand_data.other_local_dramREQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAMoffcore_response.demand_data_rd.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3001REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf801REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISSoffcore_response.demand_data_rd.other_local_dramREQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAMoffcore_response.demand_ifetch.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3004REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf804REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.demand_ifetch.other_local_dramREQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.demand_rfo.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3002REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf802REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISSoffcore_response.demand_rfo.other_local_dramREQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAMoffcore_response.other.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3080REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf880REQUEST = OTHER and RESPONSE = ANY_LLC_MISSoffcore_response.other.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4080REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAMREQUEST = OTHER and RESPONSE = REMOTE_DRAMoffcore_response.pf_data.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3050REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf850REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISSoffcore_response.pf_data.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4050REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2050REQUEST = PF_DATA and RESPONSE = REMOTE_DRAMoffcore_response.pf_data_rd.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3010REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf810REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISSoffcore_response.pf_data_rd.other_local_dramREQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAMoffcore_response.pf_ifetch.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3040REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf840REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISSoffcore_response.pf_ifetch.other_local_dramREQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_RFO and RESPONSE = REMOTE_DRAMoffcore_response.pf_rfo.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3020REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf820REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.pf_rfo.other_local_dramREQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.prefetch.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3070REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf870REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.prefetch.other_local_dramREQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PREFETCH and RESPONSE = REMOTE_DRAMload_block.overlap_storeumask=0x2,period=200000,event=0x3Loads that partially overlap an earlier storesnoopq_requests.codeumask=0x4,period=100000,event=0xb4Snoop code requestssnoopq_requests.dataumask=0x1,period=100000,event=0xb4Snoop data requestssnoopq_requests.invalidateumask=0x2,period=100000,event=0xb4Snoop invalidate requestssnoopq_requests_outstanding.codeOutstanding snoop code requestssnoopq_requests_outstanding.code_not_emptyumask=0x4,period=2000000,cmask=1,event=0xb3Cycles snoop code requests queuedsnoopq_requests_outstanding.dataOutstanding snoop data requestssnoopq_requests_outstanding.data_not_emptyumask=0x1,period=2000000,cmask=1,event=0xb3Cycles snoop data requests queuedsnoopq_requests_outstanding.invalidateOutstanding snoop invalidate requestssnoopq_requests_outstanding.invalidate_not_emptyumask=0x2,period=2000000,cmask=1,event=0xb3Cycles snoop invalidate requests queuedumask=0x4,period=20000,event=0xc5Mispredicted retired branch instructions (Precise Event)umask=0x1,period=20000,event=0xc5Mispredicted conditional retired branches (Precise Event)dtlb_load_misses.large_walk_completedumask=0x80,period=200000,event=0x8DTLB load miss large page walksdtlb_load_misses.walk_cyclesumask=0x4,period=200000,event=0x8DTLB load miss page walk cyclesdtlb_misses.large_walk_completedumask=0x80,period=200000,event=0x49DTLB miss large page walksdtlb_misses.pde_missumask=0x20,period=200000,event=0x49DTLB misses casued by low part of addressdtlb_misses.walk_cyclesumask=0x4,period=2000000,event=0x49DTLB miss page walk cyclesumask=0x10,period=2000000,event=0x4fExtended Page Table walk cyclesitlb_misses.large_walk_completedumask=0x80,period=200000,event=0x85ITLB miss large page walksitlb_misses.walk_cyclesumask=0x4,period=2000000,event=0x85ITLB miss page walk cyclesoffcore_requests.uncached_memumask=0x20,period=100000,event=0xb0Offcore uncached memory accessesumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2711umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5811umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2744umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5844umask=0x1,period=100000,event=0xb7,offcore_rsp=0x27FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x58FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2722umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5822umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2708umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5808umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2777umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5877umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2733umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5833umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2703umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5803umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2701umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5801umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2704umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5804umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2702umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5802umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2780umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5880umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F50umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF50umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2750umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1850umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5850umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2710umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5810umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2740umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5840umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2720umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5820umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2770umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5870umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6050umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF850mem_uncore_retired.local_hitmmem_uncore_retired.local_dram_and_remote_cache_hitLoad instructions retired local dram and remote cache HIT data sources (Precise Event)mem_uncore_retired.remote_hitmumask=0x4,period=40000,event=0xfRetired loads that hit remote socket in modified state (Precise Event)Cycles thread is activeinv=1,umask=0x3f,period=2000000,cmask=1,edge=1,event=0xb1inv=1,umask=0x1f,period=2000000,cmask=1,edge=1,event=0xb1DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDEumask=0x2,cmask=1,period=2000003,event=0x60mem_load_l3_miss_retired.local_dramRetired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_dramumask=0x2,period=100007,event=0xd3Retired load instructions which data sources missed L3 but serviced from remote dram  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_hitmRetired load instructions whose data sources was remote HITM  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_fwdumask=0x8,period=100007,event=0xd3Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise (Precise event)Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded eventCounts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or droppedoffcore_response.demand_data_rd.l3_hit.no_snoop_neededCounts demand data reads TBD TBDoffcore_response.demand_rfo.l3_hit.no_snoop_neededCounts all demand data writes (RFOs) TBD TBDoffcore_response.demand_code_rd.l3_hit.no_snoop_neededCounts demand instruction fetches and L1 instruction cache prefetches that TBD TBDoffcore_response.pf_l2_data_rd.l3_hit.no_snoop_neededCounts prefetch (that bring data to L2) data reads TBD TBDoffcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_hit.hitm_other_coreoffcore_response.pf_l2_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs TBD TBDoffcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l2_rfo.l3_hit.hitm_other_coreoffcore_response.pf_l3_data_rd.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads TBD TBDoffcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l3_data_rd.l3_hit.hitm_other_coreoffcore_response.pf_l3_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs TBD TBDoffcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l3_rfo.l3_hit.hitm_other_coreoffcore_response.pf_l1d_and_sw.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010400Counts L1 data cache hardware prefetch requests and software prefetch requests have any response typeoffcore_response.pf_l1d_and_sw.l3_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0400Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBDoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0400offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0400offcore_response.pf_l1d_and_sw.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0400umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010490TBD have any response typeoffcore_response.all_pf_data_rd.l3_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0490TBD TBD TBDoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0490offcore_response.all_pf_data_rd.l3_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0490umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0490offcore_response.all_pf_rfo.l3_hit.no_snoop_neededoffcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwdoffcore_response.all_pf_rfo.l3_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010491offcore_response.all_data_rd.l3_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0491umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0491umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0491umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0491offcore_response.all_rfo.l3_hit.no_snoop_neededoffcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.demand_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdCounts L1 data cache hardware prefetch requests and software prefetch requestsoffcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwdTBDoffcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.all_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.all_rfo.l3_hit.snoop_hit_with_fwdfp_arith_inst_retired.512b_packed_doubleumask=0x40,period=2000003,event=0xc7Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)fp_arith_inst_retired.512b_packed_singleumask=0x80,period=2000003,event=0xc7Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)umask=0x10,cmask=6,period=2000003,event=0x60umask=0x10,cmask=1,period=2000003,event=0x60umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000001offcore_response.demand_data_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00001Counts demand data reads TBDoffcore_response.demand_data_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00001offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00001offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000002offcore_response.demand_rfo.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00002Counts all demand data writes (RFOs) TBDoffcore_response.demand_rfo.l3_miss.remote_hitmoffcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00002offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800002offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000004offcore_response.demand_code_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00004Counts demand instruction fetches and L1 instruction cache prefetches that TBDoffcore_response.demand_code_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00004offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00004offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000004offcore_response.pf_l2_data_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000010offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00010Counts prefetch (that bring data to L2) data reads TBDoffcore_response.pf_l2_data_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00010offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00010offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000010offcore_response.pf_l2_rfo.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000020offcore_response.pf_l2_rfo.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00020Counts all prefetch (that bring data to L2) RFOs TBDoffcore_response.pf_l2_rfo.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00020offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00020offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000020offcore_response.pf_l3_data_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000080offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00080Counts all prefetch (that bring data to LLC only) data reads TBDoffcore_response.pf_l3_data_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00080offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00080offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000080offcore_response.pf_l3_rfo.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000100offcore_response.pf_l3_rfo.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00100Counts all prefetch (that bring data to LLC only) RFOs TBDoffcore_response.pf_l3_rfo.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00100offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00100offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000100offcore_response.pf_l1d_and_sw.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000400offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests TBDoffcore_response.pf_l1d_and_sw.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00400offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00400offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800400offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000400offcore_response.all_pf_data_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000490offcore_response.all_pf_data_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00490TBD TBDoffcore_response.all_pf_data_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00490offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00490offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800490offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000490offcore_response.all_pf_rfo.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000120offcore_response.all_pf_rfo.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00120offcore_response.all_pf_rfo.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00120offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00120offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000120offcore_response.all_data_rd.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000491offcore_response.all_data_rd.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00491offcore_response.all_data_rd.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00491offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00491offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800491offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000491offcore_response.all_rfo.l3_miss.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000122offcore_response.all_rfo.l3_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00122offcore_response.all_rfo.l3_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00122offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00122offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800122offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdcore_power.lvl0_turbo_licenseumask=0x7,period=200003,event=0x28Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo scheduleCore cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codescore_power.lvl1_turbo_licenseumask=0x18,period=200003,event=0x28Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo scheduleCore cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionscore_power.lvl2_turbo_licenseumask=0x20,period=200003,event=0x28Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo scheduleCore cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructionscore_power.throttleumask=0x40,period=200003,event=0x28Core cycles the core was throttled due to a pending power level requestCore cycles the out-of-order engine was throttled due to a pending power level requestcore_snoop_response.rsp_ihitiumask=0x1,period=2000003,event=0xefcore_snoop_response.rsp_ihitfseumask=0x2,period=2000003,event=0xefcore_snoop_response.rsp_shitfseumask=0x4,period=2000003,event=0xefcore_snoop_response.rsp_sfwdmumask=0x8,period=2000003,event=0xefcore_snoop_response.rsp_ifwdmumask=0x10,period=2000003,event=0xefcore_snoop_response.rsp_ifwdfeumask=0x20,period=2000003,event=0xefcore_snoop_response.rsp_sfwdfeumask=0x40,period=2000003,event=0xefidi_misc.wb_upgradeumask=0x2,period=100003,event=0xfeCounts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortlyidi_misc.wb_downgradeumask=0x4,period=100003,event=0xfeCounts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortlyumask=0x1,cmask=1,period=2000003,event=0x14edge=1,umask=0x0,cmask=1,period=100007,event=0x3cedge=1,inv=1,umask=0x1,cmask=1,period=2000003,event=0x5eumask=0x10,cmask=16,period=2000003,event=0xa3umask=0x14,cmask=20,period=2000003,event=0xa3inv=1,umask=0x2,cmask=1,period=2000003,event=0xb1inv=1,umask=0x1,cmask=10,period=2000003,event=0xc0inv=1,umask=0x2,cmask=10,period=2000003,event=0xc2inv=1,umask=0x2,cmask=1,period=2000003,event=0xc2skx metrics(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / cycles(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)1000 * l2_lines_out.silent / inst_retired.anyL2_Evictions_Silent_PKIRate of non silent evictions from the L2 cache per Kilo instruction1000 * l2_lines_out.non_silent / inst_retired.anyL2_Evictions_NonSilent_PKI( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / 1000000000 ) / duration_time1000000000 * ( cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x35\\\,umask\=0x21@ ) / ( cha_0@event\=0x0@ / duration_time )cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x36\\\,umask\=0x21\\\,thresh\=1@cha_0@event\=0x0@unc_m_act_count.wrDRAM Page Activate commands sent due to a write request. Unit: uncore_imc Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) commandunc_m_cas_count.allumask=0xF,event=0x4All DRAM CAS Commands issued. Unit: uncore_imc Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or notunc_m_cas_count.rd_regumask=0x1,event=0x4All DRAM Read CAS Commands issued (does not include underfills) . Unit: uncore_imc Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or notunc_m_cas_count.rd_underfillumask=0x2,event=0x4DRAM Underfill Read CAS Commands issued. Unit: uncore_imc Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request)unc_m_rpq_insertsRead Pending Queue Allocations. Unit: uncore_imc Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQRead Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memoryunc_m_wpq_insertsevent=0x20Write Pending Queue Allocations. Unit: uncore_imc Counts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMCunc_m_wpq_occupancyevent=0x81Write Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requestsunc_cha_clockticksUncore cache clock ticks. Unit: uncore_cha uncore otheruncore_chaumask=0x21,event=0x35,config1=0x40e33LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x40040e33MMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x40041e33MMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41833Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41a33Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha unc_cha_requests.readsumask=0x03,event=0x50read requests from home agent. Unit: uncore_cha unc_cha_requests.reads_localumask=0x01,event=0x50read requests from local home agent. Unit: uncore_cha unc_cha_requests.reads_remoteumask=0x02,event=0x50read requests from remote home agent. Unit: uncore_cha unc_cha_requests.writesumask=0x0C,event=0x50write requests from home agent. Unit: uncore_cha unc_cha_requests.writes_localumask=0x04,event=0x50write requests from local home agent. Unit: uncore_cha unc_cha_requests.writes_remoteumask=0x08,event=0x50write requests from remote home agent. Unit: uncore_cha upi_data_bandwidth_txumask=0x0F,event=0x2UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi ll uncore_upi ll7.11E-06Bytesfc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83,ch_mask=0x1fPCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio uncore_iio4Bytesunc_iio_data_req_of_cpu.mem_read.part0 + unc_iio_data_req_of_cpu.mem_read.part1 + unc_iio_data_req_of_cpu.mem_read.part2 + unc_iio_data_req_of_cpu.mem_read.part3LLC_MISSES.PCIE_READfc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83,ch_mask=0x1fPCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part0 +unc_iio_data_req_of_cpu.mem_write.part1 +unc_iio_data_req_of_cpu.mem_write.part2 +unc_iio_data_req_of_cpu.mem_write.part3LLC_MISSES.PCIE_WRITEunc_iio_data_req_of_cpu.mem_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x83PCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x83PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x83PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x83PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x83PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x83PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio unc_cha_core_snp.core_gtoneumask=0x42,event=0x33Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s)unc_cha_core_snp.evict_gtoneumask=0x82,event=0x33Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_lookup.no_snpumask=0x02,event=0x53Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not neededunc_cha_dir_lookup.snpumask=0x01,event=0x53Multi-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was neededunc_cha_dir_update.haumask=0x01,event=0x54Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesunc_cha_dir_update.torumask=0x02,event=0x54Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesunc_cha_hitme_hit.ex_rdsumask=0x01,event=0x5fRead request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)unc_cha_imc_reads_count.normalumask=0x01,event=0x59Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHAunc_cha_imc_writes_count.fullumask=0x01,event=0x5bCHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channelsunc_cha_misc.rfo_hit_sumask=0x08,event=0x39Number of times that an RFO hit in S state. Unit: uncore_cha Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) stateunc_cha_requests.invitoe_localumask=0x10,event=0x50Local requests for exclusive ownership of a cache line  without receiving data. Unit: uncore_cha Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHAunc_cha_requests.invitoe_remoteumask=0x20,event=0x50Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHAunc_cha_snoop_resp.rspcnflctsumask=0x40,event=0x5cRspCnflct* Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbIunc_cha_snoop_resp.rspiumask=0x01,event=0x5cRspI Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data)unc_cha_snoop_resp.rspifwdumask=0x04,event=0x5cRspIFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  statesunc_cha_snoop_resp.rspsfwdumask=0x08,event=0x5cRspSFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) stateunc_cha_snoop_resp.rsp_fwd_wbumask=0x20,event=0x5cRsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to it's home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to it's home socket to be written back to memoryunc_cha_snoop_resp.rsp_wbwbumask=0x10,event=0x5cRsp*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownershipunc_iio_clockticksClockticks of the IIO Traffic Controller. Unit: uncore_iio Counts clockticks of the 1GHz trafiic controller clock in the IIO unitunc_iio_data_req_by_cpu.mem_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc0Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc0Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc0Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc0Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc0Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc0Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc0Write request of 4 bytes made to IIO Part2 by the CPU . Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc0Write request of 4 bytes made to IIO Part3 by the CPU . Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc1Read request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc1Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc1Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc1Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc1Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc1Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc1Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU . Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc1Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU . Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x84Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x84Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x84Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x84Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x84Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x84Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x84Write request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x84Write request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_m2m_bypass_m2m_egress.not_takenumask=0x2,event=0x22Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not takenuncore_m2munc_m2m_direct2core_not_taken_dirstateevent=0x24Cycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Counts cycles when direct to core mode (which bypasses the CHA) was disabledunc_m2m_direct2core_takenevent=0x23Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m Counts when messages were sent direct to core (bypassing the CHA)unc_m2m_direct2core_txn_overrideevent=0x25Number of reads in which direct to core transaction were overridden. Unit: uncore_m2m Counts reads in which direct to core transactions (which would have bypassed the CHA) were overriddenunc_m2m_direct2upi_not_taken_creditsevent=0x28Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overriddenunc_m2m_direct2upi_not_taken_dirstateevent=0x27Cycles when direct to Intel UPI was disabled. Unit: uncore_m2m Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabledunc_m2m_direct2upi_takenevent=0x26Messages sent direct to the Intel UPI. Unit: uncore_m2m Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)unc_m2m_direct2upi_txn_overrideevent=0x29Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overriddenunc_m2m_directory_lookup.anyumask=0x1,event=0x2dMulti-socket cacheline Directory lookups (any state found). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)unc_m2m_directory_lookup.state_aumask=0x8,event=0x2dMulti-socket cacheline Directory lookups (cacheline found in A state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_lookup.state_iumask=0x2,event=0x2dMulti-socket cacheline Directory lookup (cacheline found in I state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_lookup.state_sumask=0x4,event=0x2dMulti-socket cacheline Directory lookup (cacheline found in S state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_update.a2iumask=0x20,event=0x2eMulti-socket cacheline Directory update from A to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)unc_m2m_directory_update.a2sumask=0x40,event=0x2eMulti-socket cacheline Directory update from A to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)unc_m2m_directory_update.anyumask=0x1,event=0x2eMulti-socket cacheline Directory update from/to Any state . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new stateunc_m2m_directory_update.i2aumask=0x4,event=0x2eMulti-socket cacheline Directory update from I to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)unc_m2m_directory_update.i2sumask=0x2,event=0x2eMulti-socket cacheline Directory update from I to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)unc_m2m_directory_update.s2aumask=0x10,event=0x2eMulti-socket cacheline Directory update from S to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)unc_m2m_directory_update.s2iumask=0x8,event=0x2eMulti-socket cacheline Directory update from S to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)unc_m2m_imc_reads.allumask=0x4,event=0x37Reads to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller)unc_m2m_imc_reads.normalReads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous readsunc_m2m_imc_writes.allumask=0x10,event=0x38Writes to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller)unc_m2m_imc_writes.partialumask=0x2,event=0x38Partial Non-Isochronous writes to the iMC. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writesunc_m2m_prefcam_demand_promotionsevent=0x56Prefecth requests that got turn into a demand request. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)unc_m2m_prefcam_insertsevent=0x57Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memoryunc_m2m_rxc_ad_insertsAD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, and unc_m3upi_upi_prefetch_spawnPrefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)uncore_m3upiunc_upi_clockticksClocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi ll Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghzunc_upi_direct_attempts.d2cumask=0x1,event=0x12Data Response packets that go direct to core. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHAunc_upi_direct_attempts.d2uumask=0x2,event=0x12Data Response packets that go direct to Intel UPI. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA unc_upi_l1_power_cyclesevent=0x21Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi ll Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdownunc_upi_rxl0p_power_cyclesCycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi ll Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerunc_upi_rxl_bypassed.slot0umask=0x1,event=0x31FLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_bypassed.slot1umask=0x2,event=0x31Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_bypassed.slot2umask=0x4,event=0x31Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_flits.all_dataumask=0x0F,event=0x3Valid data FLITs received from any slot. Unit: uncore_upi ll Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitunc_upi_rxl_flits.all_nullumask=0x27,event=0x3Null FLITs received from any slot. Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitunc_upi_rxl_flits.non_dataumask=0x97,event=0x3Protocol header and credit FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unitunc_upi_txl0p_power_cyclesCycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi ll Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerunc_upi_txl_bypassedevent=0x41FLITs that bypassed the TxL Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the linkunc_upi_txl_flits.all_nullumask=0x27,event=0x2Null FLITs transmitted from any slot. Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unitunc_upi_txl_flits.idleumask=0x47,event=0x2Idle FLITs transmitted. Unit: uncore_upi ll Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITsunc_upi_txl_flits.non_dataumask=0x97,event=0x2Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unitumask=0x10,cmask=1,period=100003,event=0x8umask=0x10,cmask=1,period=100003,event=0x49umask=0x10,cmask=1,period=100003,event=0x85offcore_response.other.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400002This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOPperiod=200003,umask=0x27,event=0x24offcore_response.all_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISSperiod=50021,umask=0x4,event=0xd1Counts retired load instructions with at least one uop that hit in the L3 cache  Supports address when precise (Precise event)offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_data_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDperiod=200003,umask=0x40,event=0xf0period=100003,umask=0x1f,event=0xf1offcore_response.demand_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.all_reads.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=200003,umask=0x1,event=0xf2offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_reads.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F804007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l1d_and_sw.supplier_none.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=200003,umask=0x3f,event=0x24period=100007,umask=0x8,event=0xd3Retired load instructions whose data sources was forwarded from a remote cache  Supports address when preciseoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOPoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=20011,umask=0x2,event=0xd2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x8,event=0xd1offcore_response.other.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400002This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.all_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDany=1,cmask=1,period=2000003,umask=0x1,event=0x48offcore_response.other.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x80,event=0xb0offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.other.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.other.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100007,umask=0x4,event=0xd4mem_load_l3_miss_retired.remote_pmmperiod=100007,umask=0x10,event=0xd3Retired load instructions with remote Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)Counts retired load instructions with remote Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOPoffcore_response.all_reads.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.demand_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSEperiod=100003,umask=0x8,event=0xd2offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=200003,umask=0xe1,event=0x24offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISScmask=1,period=2000003,umask=0x4,event=0x60offcore_response.demand_data_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x10,event=0xf4offcore_response.pf_l3_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.demand_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=200003,umask=0xc4,event=0x24offcore_response.all_pf_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_reads.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISSoffcore_response.all_pf_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08001007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=20011,umask=0x4,event=0xd2offcore_response.pf_l2_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x42,event=0xd0Retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)Counts retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010122This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSEoffcore_response.all_pf_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010002This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSEoffcore_response.all_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSEoffcore_response.pf_l1d_and_sw.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSEoffcore_response.all_pf_data_rd.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.demand_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400002This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=2000003,umask=0x2,event=0x48period=100003,umask=0x1,event=0xb7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=2000003,umask=0x1,event=0xb2offcore_response.pf_l2_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOPoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_reads.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=50021,umask=0x10,event=0xd1period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONEoffcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_rfo.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONEoffcore_response.demand_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=200003,umask=0x38,event=0x24offcore_response.all_reads.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISSoffcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.all_reads.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_reads.supplier_none.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.all_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010020This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSEoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.demand_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_reads.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100007,umask=0x20,event=0xd1Counts retired load instructions with at least one uop that missed in the L3 cache  Supports address when precise (Precise event)offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_rfo.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x41,event=0x2eoffcore_response.all_pf_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l2_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.supplier_none.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOPoffcore_response.other.l3_hit.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.all_pf_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.demand_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.all_reads.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01004007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDEDperiod=2000003,umask=0x4,event=0x60period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l3_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l3_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=200003,umask=0x2,event=0xf2offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_reads.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00804007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=200003,umask=0xc2,event=0x24offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=2000003,umask=0x8,event=0x60offcore_response.other.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00000107F7This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSEoffcore_response.all_reads.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISSoffcore_response.all_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.other.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080408000This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.all_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.all_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F801007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONEperiod=2000003,umask=0x1,event=0x51offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COREperiod=200003,umask=0xc1,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDperiod=2000003,umask=0x81,event=0xd0All retired load instructions  Supports address when precise (Precise event)offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONEoffcore_response.other.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.all_reads.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_COREcmask=1,period=2000003,umask=0x1,event=0x60offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONEoffcore_response.demand_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSEoffcore_response.other.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWDcmask=1,period=2000003,umask=0x8,event=0x60offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x41,event=0xd0Retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)Counts retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDcmask=6,period=2000003,umask=0x1,event=0x60offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOPperiod=100003,umask=0x12,event=0xd0Retired store instructions that miss the STLB  Supports address when precise (Precise event)offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=200003,umask=0xe2,event=0x24offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_reads.l3_hit.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.all_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.all_reads.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.other.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.demand_code_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.demand_code_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONEoffcore_response.other.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISSperiod=200003,umask=0xf8,event=0x24offcore_response.all_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISSoffcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISSperiod=200003,umask=0xe4,event=0x24offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=200003,umask=0xe7,event=0x24period=100007,umask=0x2,event=0xd3offcore_response.all_reads.supplier_none.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_reads.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISSperiod=200003,umask=0x24,event=0x24offcore_response.pf_l3_data_rd.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=2000003,umask=0x1,event=0x60offcore_response.all_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDcmask=1,period=2000003,umask=0x2,event=0x60offcore_response.all_reads.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x4f,event=0x2eperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x11,event=0xd0Retired load instructions that miss the STLB  Supports address when precise (Precise event)offcore_response.pf_l3_rfo.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOPmem_load_retired.local_pmmperiod=100003,umask=0x80,event=0xd1Retired load instructions with local Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)Counts retired load instructions with local Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)offcore_response.demand_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSEoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDperiod=200003,umask=0x4,event=0xf2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISSperiod=200003,umask=0x21,event=0x24offcore_response.demand_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_COREperiod=20011,umask=0x1,event=0xd2offcore_response.other.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISSperiod=200003,umask=0xff,event=0x24offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l1d_and_sw.supplier_none.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONEcmask=1,period=2000003,umask=0x1,event=0x48offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.demand_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOPoffcore_response.other.l3_hit.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISSoffcore_response.all_reads.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISSoffcore_response.demand_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISSoffcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.other.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.demand_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_COREperiod=100007,umask=0x21,event=0xd0Retired load instructions with locked access  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=2000003,umask=0x82,event=0xd0All retired store instructions  Supports address when precise (Precise event)offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100007,umask=0x1,event=0xd3Retired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when precise (Precise event)offcore_response.all_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_reads.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100108000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.other.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x4,event=0xb0offcore_response.all_data_rd.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_reads.supplier_none.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb0offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.demand_code_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISSoffcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISSperiod=100007,umask=0x4,event=0xd3offcore_response.pf_l2_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000018000This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSEoffcore_response.pf_l2_rfo.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONEperiod=200003,umask=0x22,event=0x24offcore_response.pf_l2_data_rd.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISSperiod=200003,umask=0xd8,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.demand_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREperiod=100003,umask=0x2,event=0xb0offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.all_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.all_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.other.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100408000This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.demand_code_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.other.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80408000This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISSoffcore_response.all_reads.l3_hit.snoop_hit_with_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.all_pf_data_rd.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSEoffcore_response.all_reads.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONEoffcore_response.demand_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOPoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100007,umask=0x40,event=0xd1offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.demand_code_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_reads.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800407F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.other.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISSoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOPperiod=100003,umask=0x2,event=0xd1period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_reads.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00802007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONEperiod=2000003,umask=0x1,event=0x48offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.demand_code_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOPoffcore_response.all_reads.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOPoffcore_response.other.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_reads.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_COREoffcore_response.other.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_COREperiod=2000003,umask=0x1,event=0xd1period=100003,umask=0x8,event=0xb0offcore_response.other.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISSperiod=2000003,umask=0x2,event=0x60offcore_response.all_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit.snoop_hit_with_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.all_reads.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F802007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.all_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.all_reads.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010100This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONEclx metricsidq.dsb_uops / (idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops)Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches( 1000000000 * ( imc@event\=0xe0\\\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ ) if 1 if 0 == 1 else 0 else 0MEM_PMM_Read_LatencyAverage 3DXP Memory Bandwidth Use for reads [GB / sec]( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0PMM_Read_BWAverage 3DXP Memory Bandwidth Use for Writes [GB / sec]( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0PMM_Write_BWperiod=2000003,umask=0x2,event=0xc7Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x8,event=0xc7Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x40,event=0xc7Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x20,event=0xc7Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x1,event=0xc7Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x80,event=0xc7Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementcmask=1,period=100003,umask=0x1e,event=0xcaperiod=2000003,umask=0x4,event=0xc7Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=2000003,umask=0x10,event=0xc7Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementcmask=4,period=2000003,umask=0x1,event=0x9cperiod=100007,umask=0x1,event=0xc6,frontend=0x13Retired Instructions who experienced Instruction L2 Cache true miss (Precise event)period=2000003,umask=0x20,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x200206Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x300206Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x100206Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)cmask=1,inv=1,period=2000003,umask=0x1,event=0x9cperiod=2000003,umask=0x30,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x12Retired Instructions who experienced Instruction L1 Cache true miss (Precise event)cmask=1,period=2000003,umask=0x1,event=0x9ccmask=1,period=2000003,umask=0x8,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x11Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss (Precise event)period=2000003,umask=0x4,event=0x79cmask=1,period=2000003,umask=0x30,event=0x79cmask=1,period=2000003,umask=0x4,event=0x79period=2000003,umask=0x1,event=0x9cCounts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uopsperiod=2000003,umask=0x2,event=0xabCounts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclesperiod=100007,umask=0x1,event=0xc6,frontend=0x400806period=100007,umask=0x1,event=0xc6,frontend=0x400206Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x400406Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)cmask=1,period=2000003,umask=0x10,event=0x79period=200003,umask=0x2,event=0x83period=100007,umask=0x1,event=0xc6,frontend=0x408006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)cmask=3,period=2000003,umask=0x1,event=0x9cperiod=200003,umask=0x1,event=0x83period=100007,umask=0x1,event=0xc6,frontend=0x404006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x15Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event)period=2000003,umask=0x8,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x410006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)period=2000003,umask=0x4,event=0x80cmask=1,period=2000003,umask=0x24,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x401006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event)cmask=2,period=2000003,umask=0x1,event=0x9cperiod=100007,umask=0x1,event=0xc6,frontend=0x402006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event)cmask=1,edge=1,period=2000003,umask=0x30,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x14Retired Instructions who experienced iTLB true miss (Precise event)cmask=1,period=2000003,umask=0x18,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x420006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)cmask=4,period=2000003,umask=0x24,event=0x79cmask=4,period=2000003,umask=0x18,event=0x79period=200003,umask=0x4,event=0x83ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x06040007F7ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800491ALL_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITMoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.pf_l3_rfo.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000100offcore_response.pf_l3_rfo.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_COREocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.other.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000491ALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000080Counts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01040007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000010Counts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=2000003,umask=0x8,event=0xc9ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000010Counts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPoffcore_response.all_reads.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10040007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.pf_l1d_and_sw.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONEocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08100007F7ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOPocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000020Counts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000400ocr.all_pf_rfo.l3_miss.any_snoopALL_PF_RFO & L3_MISS & ANY_SNOOPoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F840007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000004Counts all demand code reads  DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISSocr.pf_l3_rfo.l3_miss_local_dram.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOPperiod=2000003,umask=0x4,event=0x54period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISSperiod=2000003,umask=0x1,event=0x54ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000120ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000122ALL_RFO & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.other.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104008000Counts any other requests  OTHER & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDperiod=2000003,umask=0x10,event=0x5dperiod=2000003,umask=0x8,event=0x5dperiod=2000003,umask=0x4,event=0x5dperiod=2000003,umask=0x2,event=0x5dperiod=2000003,umask=0x1,event=0x5doffcore_response.all_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.pf_l2_data_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000010ocr.all_pf_data_rd.l3_miss.remote_hit_forwardALL_PF_DATA_RD & L3_MISS & REMOTE_HIT_FORWARDocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800122ALL_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_MISSoffcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B8007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000001offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_reads.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00840007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10100007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDEDperiod=2000003,umask=0x10,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_code_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00004Counts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HIT_FORWARDoffcore_response.demand_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F900007F7ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04040007F7ALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.pf_l2_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000002Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_MISSocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000080Counts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss.remote_hitmALL_PF_DATA_RD & L3_MISS & REMOTE_HITMocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000004Counts all demand code reads  DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss.snoop_missCounts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000010ocr.pf_l1d_and_sw.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONEocr.pf_l1d_and_sw.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSperiod=2000003,umask=0x2,event=0xc8offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000491ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000010Counts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000491ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISSoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.pf_l2_data_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITMocr.all_pf_data_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000490ALL_PF_DATA_RD & L3_MISS & HITM_OTHER_COREocr.all_rfo.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000122ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISSocr.demand_rfo.l3_miss.no_snoop_neededCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000080Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONEocr.all_reads.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C0007F7ALL_READS & L3_MISS & SNOOP_MISSoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITMocr.all_reads.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C0007F7ALL_READS & L3_MISS & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.pf_l2_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000004Counts all demand code reads  DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000120ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000490ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.other.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110008000Counts any other requests  OTHER & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.other.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC008000Counts any other requests OTHER & L3_MISS & SNOOP_NONEocr.all_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000122ALL_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.demand_rfo.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00002Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HITMperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_reads.l3_miss_local_dram.any_snoopALL_READS & L3_MISS_LOCAL_DRAM & ANY_SNOOPoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_reads.l3_miss.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISSoffcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000490ALL_PF_DATA_RD & L3_MISS & ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.all_reads.l3_miss_local_dram.hitm_other_coreALL_READS & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREoffcore_response.all_reads.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C0007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.other.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004008000Counts any other requests  OTHER & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREperiod=1009,umask=0x1,event=0xcd,ldlat=0x80offcore_response.all_reads.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C0007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWDperiod=2000003,umask=0x40,event=0x54period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.pf_l2_data_rd.l3_miss.snoop_missCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_MISSoffcore_response.all_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000120ALL_PF_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.all_pf_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000490ALL_PF_DATA_RD & L3_MISS & NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000490ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss.hit_other_core_fwdCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000491ALL_DATA_RD & L3_MISS & ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISSocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_pf_rfo.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000120ALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOPocr.pf_l3_rfo.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000100Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_MISSocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.other.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090008000ocr.all_rfo.l3_miss_local_dram.no_snoop_neededALL_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss.snoop_missALL_PF_DATA_RD & L3_MISS & SNOOP_MISSocr.all_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000122ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000120ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_pf_rfo.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000120ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISSocr.demand_data_rd.l3_miss.any_snoopCounts demand data reads DEMAND_DATA_RD & L3_MISS & ANY_SNOOPperiod=2000003,umask=0x40,event=0xc9ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000120ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.all_pf_data_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000490ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.pf_l2_data_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HIT_FORWARDocr.all_rfo.l3_miss_local_dram.snoop_noneALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONEocr.all_reads.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00900007F7ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.all_reads.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02040007F7ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISSocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000122ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00122ALL_RFO & L3_MISS & REMOTE_HIT_FORWARDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdALL_READS & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000020Counts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000490ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.other.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOPocr.pf_l3_rfo.l3_miss.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HITM_OTHER_COREocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B808000Counts any other requests OTHER & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDperiod=2000003,umask=0x8,event=0x54ocr.other.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084008000offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000491ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_pf_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000490ALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000010Counts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.all_reads.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_reads.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITMocr.demand_data_rd.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000001Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISSocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000080ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000100Counts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONEoffcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_rfo.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000002Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREocr.other.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC08000Counts any other requests OTHER & L3_MISS & REMOTE_HIT_FORWARDocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000020Counts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000400offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITMoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08040007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.other.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITMocr.demand_code_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000004Counts all demand code reads  DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts any other requests  OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_local_dram.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01100007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_local_dram.any_snoopCounts demand data reads  DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.other.l3_miss_local_dram.hit_other_core_fwdCounts any other requests  OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missocr.pf_l2_rfo.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000080Counts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOPperiod=2000003,umask=0x20,event=0xc9ocr.all_pf_rfo.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000120ALL_PF_RFO & L3_MISS & SNOOP_MISSoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l3_data_rd.l3_miss.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000080offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.pf_l3_data_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000080Counts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_pf_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000120ALL_PF_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000004Counts all demand code reads DEMAND_CODE_RD & L3_MISS & ANY_SNOOPocr.all_reads.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC0007F7ALL_READS & L3_MISS & ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l2_rfo.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_NONEoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPperiod=2000003,umask=0x4,event=0xc9ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.other.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010008000Counts any other requests  OTHER & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.snoop_noneALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONEocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdALL_PF_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000080Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000001Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDcmask=1,period=2000003,umask=0x10,event=0x60offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x2,event=0xc3period=2000003,umask=0x10,event=0x54offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000010ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000122ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREoffcore_response.all_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000080Counts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000001Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWDocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810008000Counts any other requests  OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.pf_l2_rfo.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HITM_OTHER_COREocr.demand_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.all_reads.l3_miss.no_snoop_neededALL_READS & L3_MISS & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDperiod=2000003,umask=0x80,event=0xc9ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04100007F7ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss.snoop_noneALL_PF_RFO & L3_MISS & SNOOP_NONEocr.demand_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000001Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss.snoop_missALL_RFO & L3_MISS & SNOOP_MISSoffcore_response.other.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDcmask=6,period=2000003,umask=0x6,event=0xa3This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.pf_l1d_and_sw.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_NONEocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneocr.demand_data_rd.l3_miss.hitm_other_coreCounts demand data reads DEMAND_DATA_RD & L3_MISS & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HITMoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.other.l3_miss_local_dram.snoop_missoffcore_response.other.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.demand_code_rd.l3_miss.snoop_noneCounts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss.remote_hit_forwardALL_READS & L3_MISS & REMOTE_HIT_FORWARDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000122ALL_RFO & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000100Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopCounts all demand code reads  DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.all_pf_rfo.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000120ALL_PF_RFO & L3_MISS & NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02100007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_reads.l3_miss.remote_hitmALL_READS & L3_MISS & REMOTE_HITMoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss.any_snoopCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & ANY_SNOOPoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000491ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITMperiod=2000003,umask=0x10,event=0xc8ocr.all_rfo.l3_miss.remote_hitmALL_RFO & L3_MISS & REMOTE_HITMocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000491ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONEocr.pf_l3_data_rd.l3_miss.remote_hitmCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HITMocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800004Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDocr.other.l3_miss_remote_hop1_dram.any_snoopCounts any other requests  OTHER & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.other.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C008000Counts any other requests OTHER & L3_MISS & SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.other.l3_miss_local_dram.snoop_miss_or_no_fwdCounts any other requests OTHER & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDperiod=100007,umask=0x1,event=0xcd,ldlat=0x20offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000020Counts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HIT_FORWARDocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000004offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000122ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISSocr.pf_l3_rfo.l3_miss.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_NONEocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000001Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_MISSperiod=2000003,umask=0x8,event=0xc8offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000122ALL_RFO & L3_MISS & SNOOP_NONEocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800120ALL_PF_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.other.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC08000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITMoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISSocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.other.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C008000Counts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.other.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210008000ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000080ocr.demand_data_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00001Counts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HIT_FORWARDocr.all_reads.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC0007F7ALL_READS & L3_MISS & SNOOP_NONEoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITMocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000020Counts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREoffcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_local_dram.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000120ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONEocr.pf_l3_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00100Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HIT_FORWARDocr.all_data_rd.l3_miss.snoop_missALL_DATA_RD & L3_MISS & SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwdALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_local_dram.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.all_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONEoffcore_response.all_pf_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000120ALL_PF_RFO & L3_MISS & HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONEocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000020Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & ANY_SNOOPoffcore_response.all_reads.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONEocr.pf_l2_rfo.l3_miss.snoop_missCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_MISSoffcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoopALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.all_rfo.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREocr.demand_rfo.l3_miss.snoop_noneCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_NONEocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000120ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.other.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C008000Counts any other requests OTHER & L3_MISS & HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=503,umask=0x1,event=0xcd,ldlat=0x100ocr.demand_code_rd.l3_miss_local_dram.snoop_missoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDperiod=20011,umask=0x1,event=0xcd,ldlat=0x10offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss_local_dram.snoop_noneperiod=2000003,umask=0x20,event=0x54ocr.pf_l3_data_rd.l3_miss.snoop_missCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_MISSoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneocr.pf_l2_data_rd.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_NONEocr.demand_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000002Counts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=2000003,umask=0x2,event=0x54period=2000003,umask=0x40,event=0xc8period=2000003,umask=0x1,event=0xc9ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000122ALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISSocr.other.l3_miss_local_dram.hit_other_core_no_fwdCounts any other requests  OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONEocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000490ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEperiod=101,umask=0x1,event=0xcd,ldlat=0x200period=2000003,umask=0x20,event=0xc8ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000010Counts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss_remote_hop1_dram.snoop_missALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISSoffcore_response.all_reads.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C0007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss.no_snoop_neededCounts all demand code reads DEMAND_CODE_RD & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000400Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.demand_data_rd.l3_miss.remote_hitmCounts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HITMocr.demand_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000001Counts demand data reads DEMAND_DATA_RD & L3_MISS & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000080Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_rfo.l3_miss.any_snoopALL_RFO & L3_MISS & ANY_SNOOPocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.demand_code_rd.l3_miss.hit_other_core_fwdCounts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00010Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HITMcmask=6,period=2000003,umask=0x10,event=0x60period=2003,umask=0x1,event=0xcd,ldlat=0x40ocr.all_rfo.l3_miss.hitm_other_coreALL_RFO & L3_MISS & HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_miss.snoop_noneALL_PF_DATA_RD & L3_MISS & SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITMoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.other.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C008000Counts any other requests OTHER & L3_MISS & NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDocr.other.l3_miss.any_snoopCounts any other requests OTHER & L3_MISS & ANY_SNOOPocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000004Counts all demand code reads  DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.all_rfo.l3_miss.hit_other_core_no_fwdALL_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.pf_l3_data_rd.l3_miss.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITMocr.all_pf_rfo.l3_miss.remote_hit_forwardALL_PF_RFO & L3_MISS & REMOTE_HIT_FORWARDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_local_dram.hitm_other_coreALL_PF_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREocr.other.l3_miss_local_dram.any_snoopCounts any other requests  OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_COREocr.demand_rfo.l3_miss_local_dram.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.demand_rfo.l3_miss.hitm_other_coreCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITMoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_missALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISScmask=2,period=2000003,umask=0x2,event=0xa3ocr.other.l3_miss.remote_hitmCounts any other requests OTHER & L3_MISS & REMOTE_HITMoffcore_response.all_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800001Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.other.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISSoffcore_response.all_reads.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.all_data_rd.l3_miss.snoop_noneALL_DATA_RD & L3_MISS & SNOOP_NONEocr.all_data_rd.l3_miss.no_snoop_neededALL_DATA_RD & L3_MISS & NO_SNOOP_NEEDEDocr.all_rfo.l3_miss_local_dram.any_snoopALL_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.snoop_noneALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONEocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss.remote_hit_forwardThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000491ALL_DATA_RD & L3_MISS & HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOPocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREoffcore_response.demand_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss_local_dram.no_snoop_neededALL_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDoffcore_response.other.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000001Counts demand data reads  DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDperiod=2000003,umask=0x2,event=0xc9ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWDocr.all_data_rd.l3_miss_local_dram.hitm_other_coreALL_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREperiod=2000003,umask=0x80,event=0xc8period=2000003,umask=0x10,event=0x60ocr.demand_rfo.l3_miss.any_snoopCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.snoop_missALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISSoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONEoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONEoffcore_response.other.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITMocr.all_reads.l3_miss_local_dram.no_snoop_neededALL_READS & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss.hit_other_core_no_fwdCounts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_COREocr.all_pf_rfo.l3_miss_local_dram.snoop_noneALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONEoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_data_rd.l3_miss.remote_hitmALL_DATA_RD & L3_MISS & REMOTE_HITMocr.all_rfo.l3_miss_remote_hop1_dram.snoop_noneALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONEoffcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss.remote_hitmCounts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HITMocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwdALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss.remote_hit_forwardCounts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.demand_rfo.l3_miss_local_dram.snoop_noneocr.pf_l3_rfo.l3_miss.remote_hitmCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HITMThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000080offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.other.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C008000This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000400Counts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.pf_l3_rfo.l3_miss_local_dram.snoop_missocr.all_data_rd.l3_miss.remote_hit_forwardALL_DATA_RD & L3_MISS & REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x10,event=0xb0ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededALL_READS & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss.hitm_other_coreCounts all demand code reads DEMAND_CODE_RD & L3_MISS & HITM_OTHER_COREocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000491ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISSocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss_local_dram.snoop_missocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDEDocr.all_reads.l3_miss_local_dram.hit_other_core_fwdALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_COREocr.demand_code_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000004offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITMoffcore_response.demand_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=2000003,umask=0x4,event=0xc8This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneocr.pf_l2_data_rd.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000010ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneocr.all_data_rd.l3_miss.hit_other_core_fwdALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss_local_dram.any_snoopALL_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss.any_snoopCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & ANY_SNOOPoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_data_rd.l3_miss_local_dram.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.all_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOPoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONEocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss.remote_hitmCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HITMperiod=2000003,umask=0x1,event=0xc8offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARDocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss.hit_other_core_fwdALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss.hitm_other_coreALL_READS & L3_MISS & HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_COREocr.other.l3_miss.hit_other_core_fwdCounts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss.remote_hitmALL_PF_RFO & L3_MISS & REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_reads.l3_miss_local_dram.snoop_noneALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_NONEperiod=100003,umask=0x1,event=0xcd,ldlat=0x4This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISSperiod=50021,umask=0x1,event=0xcd,ldlat=0x8ocr.all_reads.l3_miss.hit_other_core_fwdALL_READS & L3_MISS & HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_s.hitm_other_coreALL_PF_RFO & L3_HIT_S & HITM_OTHER_COREocr.all_reads.l3_hit_f.no_snoop_neededALL_READS & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit.snoop_hit_with_fwdALL_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWDocr.all_rfo.supplier_none.snoop_missALL_RFO & SUPPLIER_NONE & SNOOP_MISSocr.all_reads.l3_hit_m.hit_other_core_fwdALL_READS & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_s.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_S & HITM_OTHER_COREocr.other.l3_hit_e.snoop_noneocr.demand_data_rd.l3_hit_s.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_s.no_snoop_neededALL_RFO & L3_HIT_S & NO_SNOOP_NEEDEDocr.other.supplier_none.hitm_other_coreCounts any other requests  OTHER & SUPPLIER_NONE & HITM_OTHER_COREocr.demand_rfo.l3_hit_m.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_M & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_s.hit_other_core_fwdALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_e.any_snoopCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_E & ANY_SNOOPocr.all_pf_rfo.l3_hit.any_snoopALL_PF_RFO & L3_HIT & ANY_SNOOPocr.all_data_rd.l3_hit_s.hitm_other_coreALL_DATA_RD & L3_HIT_S & HITM_OTHER_COREocr.all_pf_rfo.l3_hit_s.any_snoopALL_PF_RFO & L3_HIT_S & ANY_SNOOPocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit.snoop_missCounts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_MISSocr.other.l3_hit_m.hitm_other_coreCounts any other requests  OTHER & L3_HIT_M & HITM_OTHER_COREocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_s.snoop_noneocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_m.no_snoop_neededALL_READS & L3_HIT_M & NO_SNOOP_NEEDEDocr.other.l3_hit_e.any_snoopCounts any other requests  OTHER & L3_HIT_E & ANY_SNOOPocr.pf_l2_rfo.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_e.hitm_other_coreALL_PF_RFO & L3_HIT_E & HITM_OTHER_COREocr.all_pf_data_rd.l3_hit.hitm_other_coreALL_PF_DATA_RD & L3_HIT & HITM_OTHER_COREocr.all_rfo.supplier_none.no_snoop_neededALL_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_f.hitm_other_coreALL_DATA_RD & L3_HIT_F & HITM_OTHER_COREocr.other.pmm_hit_local_pmm.any_snoopCounts any other requests OTHER & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_pf_data_rd.supplier_none.hitm_other_coreALL_PF_DATA_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.all_reads.pmm_hit_local_pmm.any_snoopALL_READS & PMM_HIT_LOCAL_PMM & ANY_SNOOPperiod=100003,umask=0x4,event=0xfeocr.demand_rfo.l3_hit_e.snoop_noneocr.demand_code_rd.l3_hit.hitm_other_coreCounts all demand code reads DEMAND_CODE_RD & L3_HIT & HITM_OTHER_COREocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_f.snoop_missocr.demand_code_rd.l3_hit_m.any_snoopCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_M & ANY_SNOOPocr.other.l3_hit_s.any_snoopCounts any other requests  OTHER & L3_HIT_S & ANY_SNOOPocr.other.l3_hit.hit_other_core_no_fwdCounts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_data_rd.pmm_hit_local_pmm.any_snoopALL_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdocr.other.l3_hit_s.no_snoop_neededCounts any other requests  OTHER & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_reads.l3_hit_f.snoop_missALL_READS & L3_HIT_F & SNOOP_MISSocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_e.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_E & HITM_OTHER_COREocr.demand_code_rd.supplier_none.snoop_noneocr.all_pf_rfo.l3_hit_e.hit_other_core_fwdALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_s.hit_other_core_no_fwdALL_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwdocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwdALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.other.l3_hit.snoop_missCounts any other requests OTHER & L3_HIT & SNOOP_MISSocr.pf_l1d_and_sw.l3_hit_e.snoop_missocr.demand_data_rd.l3_hit_s.hit_other_core_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit.snoop_missALL_RFO & L3_HIT & SNOOP_MISSocr.demand_rfo.l3_hit_m.hitm_other_coreCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_M & HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_s.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_S & ANY_SNOOPocr.all_rfo.l3_hit_f.hitm_other_coreALL_RFO & L3_HIT_F & HITM_OTHER_COREocr.other.l3_hit_e.hit_other_core_fwdCounts any other requests  OTHER & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_data_rd.supplier_none.snoop_missALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISSocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_NONEocr.demand_rfo.l3_hit_e.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_E & ANY_SNOOPocr.all_rfo.l3_hit_m.snoop_missALL_RFO & L3_HIT_M & SNOOP_MISSocr.all_rfo.l3_hit.hitm_other_coreALL_RFO & L3_HIT & HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit.snoop_noneCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_NONEocr.demand_data_rd.l3_hit_e.snoop_noneocr.pf_l1d_and_sw.l3_hit_m.snoop_missocr.pf_l2_rfo.any_responseocr.demand_rfo.supplier_none.hit_other_core_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_f.snoop_missocr.other.supplier_none.snoop_missocr.pf_l3_rfo.l3_hit_e.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.all_reads.l3_hit_e.hit_other_core_fwdALL_READS & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_f.hit_other_core_no_fwdALL_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_m.snoop_noneocr.demand_data_rd.l3_hit_f.any_snoopCounts demand data reads  DEMAND_DATA_RD & L3_HIT_F & ANY_SNOOPocr.demand_data_rd.l3_hit_m.hit_other_core_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.pf_l3_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_m.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.other.l3_hit_m.hit_other_core_fwdCounts any other requests  OTHER & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_e.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & L3_HIT_E & HITM_OTHER_COREocr.all_data_rd.l3_hit_e.no_snoop_neededALL_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_s.snoop_noneocr.pf_l2_rfo.l3_hit_e.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_E & NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit.any_snoopCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & ANY_SNOOPocr.all_data_rd.supplier_none.hit_other_core_no_fwdALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.supplier_none.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_pf_data_rd.supplier_none.hit_other_core_fwdALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit.no_snoop_neededALL_RFO & L3_HIT & NO_SNOOP_NEEDEDocr.demand_data_rd.supplier_none.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit.snoop_noneCounts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_NONEocr.pf_l3_rfo.supplier_none.snoop_missocr.pf_l2_data_rd.l3_hit_f.snoop_missocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.any_responseALL_PF_DATA_RD & ANY_RESPONSE have any response typeocr.other.l3_hit_s.hit_other_core_fwdCounts any other requests  OTHER & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit.snoop_missALL_PF_RFO & L3_HIT & SNOOP_MISSocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_m.snoop_missocr.all_data_rd.l3_hit_s.snoop_missALL_DATA_RD & L3_HIT_S & SNOOP_MISSocr.all_rfo.l3_hit_m.any_snoopALL_RFO & L3_HIT_M & ANY_SNOOPocr.demand_rfo.l3_hit_f.hit_other_core_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.supplier_none.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & SUPPLIER_NONE & HITM_OTHER_COREocr.all_reads.l3_hit_e.any_snoopALL_READS & L3_HIT_E & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_e.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l3_rfo.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOPocr.all_pf_data_rd.l3_hit_f.hitm_other_coreALL_PF_DATA_RD & L3_HIT_F & HITM_OTHER_COREocr.all_reads.supplier_none.hit_other_core_fwdALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_reads.supplier_none.hit_other_core_no_fwdALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_e.snoop_missALL_PF_DATA_RD & L3_HIT_E & SNOOP_MISSocr.all_data_rd.l3_hit_f.hit_other_core_no_fwdALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_e.no_snoop_neededALL_PF_RFO & L3_HIT_E & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_e.hit_other_core_fwdALL_RFO & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_f.any_snoopALL_DATA_RD & L3_HIT_F & ANY_SNOOPocr.pf_l3_rfo.l3_hit.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_NONEocr.demand_data_rd.l3_hit_e.hit_other_core_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_e.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.other.l3_hit_e.hit_other_core_no_fwdCounts any other requests  OTHER & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_m.hitm_other_coreALL_RFO & L3_HIT_M & HITM_OTHER_COREocr.demand_data_rd.l3_hit_m.snoop_missocr.all_rfo.any_responseALL_RFO & ANY_RESPONSE have any response typeocr.demand_code_rd.any_responseocr.demand_code_rd.l3_hit_e.snoop_missocr.pf_l3_rfo.l3_hit_m.snoop_missocr.demand_rfo.l3_hit.snoop_hit_with_fwdocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.demand_data_rd.l3_hit.hit_other_core_fwdCounts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit.any_snoopCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & ANY_SNOOPocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l2_rfo.l3_hit_f.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_F & ANY_SNOOPocr.pf_l3_data_rd.supplier_none.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.all_reads.l3_hit.snoop_missALL_READS & L3_HIT & SNOOP_MISSocr.all_pf_data_rd.supplier_none.snoop_missALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISSocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.pf_l3_rfo.l3_hit_e.snoop_missocr.demand_rfo.l3_hit_f.snoop_noneocr.pf_l2_rfo.supplier_none.snoop_noneocr.other.l3_hit_e.no_snoop_neededCounts any other requests  OTHER & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_f.any_snoopALL_PF_DATA_RD & L3_HIT_F & ANY_SNOOPocr.all_pf_rfo.l3_hit_m.hit_other_core_fwdALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_FWDocr.all_reads.supplier_none.any_snoopALL_READS & SUPPLIER_NONE & ANY_SNOOPocr.pf_l3_data_rd.l3_hit_f.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_F & ANY_SNOOPocr.pf_l2_data_rd.l3_hit.snoop_noneCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_NONEocr.all_data_rd.l3_hit_s.no_snoop_neededALL_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_pf_rfo.supplier_none.snoop_missALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISSocr.all_rfo.l3_hit_m.hit_other_core_no_fwdALL_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.all_reads.supplier_none.snoop_noneALL_READS & SUPPLIER_NONE & SNOOP_NONEocr.all_data_rd.l3_hit_s.hit_other_core_fwdALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.supplier_none.snoop_missocr.all_rfo.pmm_hit_local_pmm.snoop_noneALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.all_pf_data_rd.supplier_none.snoop_noneALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONEocr.all_reads.l3_hit_e.snoop_missALL_READS & L3_HIT_E & SNOOP_MISSocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.all_data_rd.l3_hit_m.snoop_noneALL_DATA_RD & L3_HIT_M & SNOOP_NONEocr.all_rfo.pmm_hit_local_pmm.any_snoopALL_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_rfo.l3_hit_m.hit_other_core_fwdALL_RFO & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_f.snoop_noneocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit.hit_other_core_no_fwdCounts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit.hit_other_core_fwdALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_e.any_snoopCounts demand data reads  DEMAND_DATA_RD & L3_HIT_E & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_f.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_F & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_s.any_snoopCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_S & ANY_SNOOPocr.demand_data_rd.l3_hit_f.snoop_noneocr.demand_code_rd.l3_hit_e.snoop_noneocr.pf_l2_data_rd.supplier_none.snoop_missocr.all_pf_data_rd.l3_hit_f.snoop_missALL_PF_DATA_RD & L3_HIT_F & SNOOP_MISSocr.all_pf_data_rd.l3_hit_m.any_snoopALL_PF_DATA_RD & L3_HIT_M & ANY_SNOOPocr.demand_code_rd.supplier_none.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.demand_code_rd.l3_hit.hit_other_core_fwdCounts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.demand_code_rd.supplier_none.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_s.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_S & HITM_OTHER_COREocr.demand_rfo.l3_hit_m.snoop_missocr.all_rfo.l3_hit_f.hit_other_core_fwdALL_RFO & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_e.hit_other_core_no_fwdALL_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_rfo.supplier_none.hitm_other_coreCounts all demand data writes (RFOs)  DEMAND_RFO & SUPPLIER_NONE & HITM_OTHER_COREperiod=200003,umask=0x7,event=0x28ocr.other.supplier_none.snoop_noneocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.demand_rfo.l3_hit_m.hit_other_core_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_f.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_rfo.supplier_none.snoop_noneALL_RFO & SUPPLIER_NONE & SNOOP_NONEocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.demand_code_rd.l3_hit_e.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_E & HITM_OTHER_COREocr.all_data_rd.l3_hit_s.any_snoopALL_DATA_RD & L3_HIT_S & ANY_SNOOPocr.all_reads.l3_hit_f.hit_other_core_fwdALL_READS & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_f.snoop_missALL_DATA_RD & L3_HIT_F & SNOOP_MISSocr.all_pf_rfo.supplier_none.snoop_noneALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONEocr.all_pf_rfo.any_responseALL_PF_RFO & ANY_RESPONSE have any response typeocr.all_rfo.l3_hit.hit_other_core_no_fwdALL_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_m.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_M & HITM_OTHER_COREocr.demand_code_rd.l3_hit_f.any_snoopCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_F & ANY_SNOOPocr.pf_l2_data_rd.l3_hit_e.any_snoopCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_E & ANY_SNOOPocr.all_reads.l3_hit_m.snoop_missALL_READS & L3_HIT_M & SNOOP_MISSocr.pf_l2_rfo.l3_hit.snoop_missCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_MISSocr.pf_l3_data_rd.l3_hit_m.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit.snoop_missCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_MISSperiod=200003,umask=0x40,event=0x28ocr.demand_rfo.l3_hit.hitm_other_coreCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_f.snoop_missocr.demand_code_rd.l3_hit_e.hit_other_core_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.demand_code_rd.supplier_none.snoop_missocr.pf_l1d_and_sw.l3_hit_m.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_M & ANY_SNOOPocr.all_pf_rfo.l3_hit_m.snoop_noneALL_PF_RFO & L3_HIT_M & SNOOP_NONEocr.demand_data_rd.l3_hit_s.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & L3_HIT_S & HITM_OTHER_COREocr.demand_rfo.l3_hit_m.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_M & ANY_SNOOPocr.demand_data_rd.l3_hit.no_snoop_neededCounts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l1d_and_sw.l3_hit_m.snoop_noneocr.pf_l2_data_rd.l3_hit_s.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_S & HITM_OTHER_COREocr.all_rfo.supplier_none.hit_other_core_fwdALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.other.any_responseocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.supplier_none.hit_other_core_fwdCounts all demand code reads  DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_e.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_E & ANY_SNOOPocr.pf_l2_data_rd.supplier_none.any_snoopCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOPocr.demand_rfo.supplier_none.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_e.snoop_noneocr.all_pf_rfo.l3_hit.no_snoop_neededALL_PF_RFO & L3_HIT & NO_SNOOP_NEEDEDocr.demand_data_rd.any_responseocr.demand_code_rd.l3_hit.snoop_missCounts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_MISSocr.other.l3_hit_f.snoop_noneocr.pf_l2_rfo.supplier_none.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOPocr.pf_l3_data_rd.l3_hit_s.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_S & HITM_OTHER_COREocr.demand_rfo.pmm_hit_local_pmm.snoop_noneCounts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.demand_rfo.l3_hit_s.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_m.no_snoop_neededALL_PF_RFO & L3_HIT_M & NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_e.snoop_missALL_PF_RFO & L3_HIT_E & SNOOP_MISSocr.demand_data_rd.supplier_none.any_snoopCounts demand data reads  DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOPocr.all_data_rd.any_responseALL_DATA_RD & ANY_RESPONSE have any response typeocr.pf_l3_rfo.l3_hit_e.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_E & HITM_OTHER_COREocr.all_rfo.l3_hit_s.snoop_noneALL_RFO & L3_HIT_S & SNOOP_NONEocr.pf_l2_rfo.l3_hit_e.snoop_noneocr.demand_code_rd.l3_hit_f.hit_other_core_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_pf_rfo.pmm_hit_local_pmm.snoop_noneALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_m.snoop_noneocr.all_pf_rfo.l3_hit_f.snoop_noneALL_PF_RFO & L3_HIT_F & SNOOP_NONEocr.pf_l3_rfo.l3_hit_f.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_e.any_snoopALL_PF_RFO & L3_HIT_E & ANY_SNOOPocr.other.l3_hit.hit_other_core_fwdCounts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_m.snoop_noneocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwdALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_e.hitm_other_coreALL_PF_DATA_RD & L3_HIT_E & HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_f.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_F & HITM_OTHER_COREocr.pf_l1d_and_sw.supplier_none.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_f.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_F & HITM_OTHER_COREocr.pf_l3_rfo.supplier_none.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_s.snoop_noneocr.all_data_rd.l3_hit.no_snoop_neededALL_DATA_RD & L3_HIT & NO_SNOOP_NEEDEDocr.all_reads.l3_hit.hit_other_core_fwdALL_READS & L3_HIT & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit.snoop_noneCounts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_NONEocr.all_data_rd.pmm_hit_local_pmm.snoop_noneALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.all_data_rd.supplier_none.snoop_noneALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONEocr.demand_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.all_pf_data_rd.l3_hit.hit_other_core_fwdALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit.hitm_other_coreALL_DATA_RD & L3_HIT & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_m.any_snoopCounts demand data reads  DEMAND_DATA_RD & L3_HIT_M & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit.hit_other_core_no_fwdALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit.snoop_missCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_MISSocr.pf_l2_data_rd.l3_hit_s.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_s.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_S & HITM_OTHER_COREocr.all_data_rd.l3_hit_e.any_snoopALL_DATA_RD & L3_HIT_E & ANY_SNOOPocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_reads.l3_hit_f.hitm_other_coreALL_READS & L3_HIT_F & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit.hitm_other_coreALL_PF_RFO & L3_HIT & HITM_OTHER_COREocr.other.l3_hit_s.snoop_missocr.pf_l3_rfo.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.supplier_none.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & SUPPLIER_NONE & ANY_SNOOPocr.pf_l2_data_rd.any_responseocr.demand_rfo.l3_hit_s.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit_m.hitm_other_coreALL_DATA_RD & L3_HIT_M & HITM_OTHER_COREperiod=100003,umask=0x2,event=0xfeocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit.snoop_hit_with_fwdocr.other.l3_hit_m.no_snoop_neededCounts any other requests  OTHER & L3_HIT_M & NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwdALL_PF_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWDocr.all_pf_data_rd.l3_hit_m.no_snoop_neededALL_PF_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_f.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_F & ANY_SNOOPocr.all_data_rd.l3_hit_f.snoop_noneALL_DATA_RD & L3_HIT_F & SNOOP_NONEocr.pf_l2_data_rd.l3_hit_s.snoop_missocr.all_pf_rfo.l3_hit_f.no_snoop_neededALL_PF_RFO & L3_HIT_F & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_s.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_m.snoop_noneocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit.snoop_missCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_MISSocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_reads.l3_hit.hitm_other_coreALL_READS & L3_HIT & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_s.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_S & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_m.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.all_reads.l3_hit.hit_other_core_no_fwdALL_READS & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_f.no_snoop_neededALL_PF_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.other.supplier_none.no_snoop_neededCounts any other requests  OTHER & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_e.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_E & ANY_SNOOPocr.other.pmm_hit_local_pmm.snoop_noneCounts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.all_reads.l3_hit_s.hit_other_core_fwdALL_READS & L3_HIT_S & HIT_OTHER_CORE_FWDperiod=2000003,umask=0x4,event=0x32ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.demand_data_rd.supplier_none.snoop_noneocr.pf_l2_rfo.l3_hit_m.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_M & ANY_SNOOPocr.pf_l2_rfo.supplier_none.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & SUPPLIER_NONE & HITM_OTHER_COREocr.all_data_rd.l3_hit_m.hit_other_core_fwdALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_f.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_f.snoop_missALL_RFO & L3_HIT_F & SNOOP_MISSocr.pf_l2_rfo.l3_hit_f.snoop_noneocr.pf_l1d_and_sw.supplier_none.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & SUPPLIER_NONE & HITM_OTHER_COREocr.all_pf_rfo.l3_hit.hit_other_core_no_fwdALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.any_responseocr.all_pf_data_rd.supplier_none.any_snoopALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOPocr.pf_l3_rfo.l3_hit_m.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_M & ANY_SNOOPocr.all_rfo.supplier_none.hitm_other_coreALL_RFO & SUPPLIER_NONE & HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_f.any_snoopALL_RFO & L3_HIT_F & ANY_SNOOPocr.all_pf_data_rd.l3_hit_s.hitm_other_coreALL_PF_DATA_RD & L3_HIT_S & HITM_OTHER_COREocr.all_rfo.l3_hit_s.any_snoopALL_RFO & L3_HIT_S & ANY_SNOOPocr.other.pmm_hit_local_pmm.snoop_not_neededCounts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l2_rfo.l3_hit.snoop_noneCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_NONEocr.demand_rfo.l3_hit.no_snoop_neededCounts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.all_reads.l3_hit_s.hit_other_core_no_fwdALL_READS & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_m.any_snoopCounts any other requests  OTHER & L3_HIT_M & ANY_SNOOPocr.all_pf_data_rd.l3_hit_s.any_snoopALL_PF_DATA_RD & L3_HIT_S & ANY_SNOOPocr.demand_rfo.l3_hit_f.hitm_other_coreCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_F & HITM_OTHER_COREocr.all_data_rd.l3_hit_e.hitm_other_coreALL_DATA_RD & L3_HIT_E & HITM_OTHER_COREocr.all_reads.l3_hit_e.no_snoop_neededALL_READS & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_f.snoop_missocr.demand_code_rd.l3_hit_s.any_snoopCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_S & ANY_SNOOPocr.pf_l1d_and_sw.any_responseocr.demand_data_rd.l3_hit_f.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.other.l3_hit.snoop_hit_with_fwdocr.all_pf_rfo.l3_hit_s.no_snoop_neededALL_PF_RFO & L3_HIT_S & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_s.snoop_noneocr.all_rfo.supplier_none.hit_other_core_no_fwdALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_e.hitm_other_coreCounts any other requests  OTHER & L3_HIT_E & HITM_OTHER_COREocr.all_reads.l3_hit.any_snoopALL_READS & L3_HIT & ANY_SNOOPocr.all_reads.pmm_hit_local_pmm.snoop_noneALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.other.supplier_none.hit_other_core_no_fwdCounts any other requests  OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit.any_snoopALL_PF_DATA_RD & L3_HIT & ANY_SNOOPocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededCounts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.demand_data_rd.l3_hit.hitm_other_coreCounts demand data reads DEMAND_DATA_RD & L3_HIT & HITM_OTHER_COREocr.demand_rfo.supplier_none.snoop_missocr.all_reads.l3_hit.snoop_hit_with_fwdALL_READS & L3_HIT & SNOOP_HIT_WITH_FWDocr.demand_code_rd.pmm_hit_local_pmm.snoop_noneCounts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.demand_data_rd.l3_hit_s.snoop_missocr.all_reads.l3_hit.snoop_noneALL_READS & L3_HIT & SNOOP_NONEocr.pf_l3_data_rd.l3_hit_e.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_E & HITM_OTHER_COREocr.all_pf_data_rd.supplier_none.no_snoop_neededALL_PF_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.other.supplier_none.any_snoopCounts any other requests  OTHER & SUPPLIER_NONE & ANY_SNOOPocr.all_pf_data_rd.l3_hit.no_snoop_neededALL_PF_DATA_RD & L3_HIT & NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_s.no_snoop_neededALL_READS & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_s.hitm_other_coreALL_RFO & L3_HIT_S & HITM_OTHER_COREocr.all_rfo.l3_hit.snoop_hit_with_fwdALL_RFO & L3_HIT & SNOOP_HIT_WITH_FWDocr.all_reads.l3_hit_m.any_snoopALL_READS & L3_HIT_M & ANY_SNOOPocr.all_reads.l3_hit.no_snoop_neededALL_READS & L3_HIT & NO_SNOOP_NEEDEDocr.all_reads.any_responseALL_READS & ANY_RESPONSE have any response typeocr.all_data_rd.l3_hit.hit_other_core_fwdALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_m.no_snoop_neededALL_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.pf_l3_data_rd.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOPocr.other.l3_hit_f.hitm_other_coreCounts any other requests  OTHER & L3_HIT_F & HITM_OTHER_COREocr.all_data_rd.l3_hit.any_snoopALL_DATA_RD & L3_HIT & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_m.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_M & HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_e.snoop_noneocr.pf_l2_data_rd.l3_hit_e.snoop_missocr.all_pf_rfo.pmm_hit_local_pmm.any_snoopALL_PF_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_e.snoop_noneocr.all_pf_data_rd.l3_hit.snoop_missALL_PF_DATA_RD & L3_HIT & SNOOP_MISSocr.other.l3_hit.snoop_noneCounts any other requests OTHER & L3_HIT & SNOOP_NONEocr.other.supplier_none.hit_other_core_fwdCounts any other requests  OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_e.snoop_noneALL_DATA_RD & L3_HIT_E & SNOOP_NONEocr.demand_rfo.l3_hit_s.hitm_other_coreCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_S & HITM_OTHER_COREocr.all_reads.l3_hit_s.hitm_other_coreALL_READS & L3_HIT_S & HITM_OTHER_COREocr.all_reads.l3_hit_f.any_snoopALL_READS & L3_HIT_F & ANY_SNOOPocr.all_reads.l3_hit_m.hit_other_core_no_fwdALL_READS & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_s.snoop_noneALL_READS & L3_HIT_S & SNOOP_NONEocr.pf_l3_data_rd.l3_hit.snoop_missCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_MISSocr.all_pf_data_rd.l3_hit_e.snoop_noneALL_PF_DATA_RD & L3_HIT_E & SNOOP_NONEocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_e.hit_other_core_no_fwdALL_READS & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_s.snoop_missocr.all_data_rd.l3_hit_s.snoop_noneALL_DATA_RD & L3_HIT_S & SNOOP_NONEocr.demand_rfo.supplier_none.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & SUPPLIER_NONE & ANY_SNOOPocr.pf_l3_data_rd.l3_hit.any_snoopCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & ANY_SNOOPocr.all_rfo.l3_hit.snoop_noneALL_RFO & L3_HIT & SNOOP_NONEocr.all_pf_data_rd.l3_hit_m.snoop_noneALL_PF_DATA_RD & L3_HIT_M & SNOOP_NONEocr.demand_rfo.l3_hit.hit_other_core_no_fwdCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_e.snoop_noneALL_READS & L3_HIT_E & SNOOP_NONEocr.demand_data_rd.supplier_none.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.all_reads.supplier_none.snoop_missALL_READS & SUPPLIER_NONE & SNOOP_MISSocr.pf_l3_data_rd.l3_hit_f.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_F & HITM_OTHER_COREperiod=2000003,umask=0x2,event=0x32ocr.all_rfo.l3_hit.hit_other_core_fwdALL_RFO & L3_HIT & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_f.hit_other_core_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_s.hit_other_core_no_fwdALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_m.snoop_noneALL_READS & L3_HIT_M & SNOOP_NONEocr.pf_l2_rfo.l3_hit_s.snoop_missperiod=200003,umask=0x20,event=0x28ocr.pf_l1d_and_sw.l3_hit.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HITM_OTHER_COREocr.pf_l2_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l1d_and_sw.l3_hit_e.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_E & HITM_OTHER_COREocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.demand_code_rd.supplier_none.any_snoopCounts all demand code reads  DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_s.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_S & ANY_SNOOPocr.demand_rfo.l3_hit_e.hit_other_core_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_f.snoop_missALL_PF_RFO & L3_HIT_F & SNOOP_MISSocr.demand_code_rd.l3_hit.hit_other_core_no_fwdCounts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_f.any_snoopCounts any other requests  OTHER & L3_HIT_F & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_s.snoop_noneocr.all_reads.supplier_none.no_snoop_neededALL_READS & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_f.snoop_noneALL_PF_DATA_RD & L3_HIT_F & SNOOP_NONEocr.demand_rfo.l3_hit_s.hit_other_core_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_f.snoop_noneALL_READS & L3_HIT_F & SNOOP_NONEocr.pf_l1d_and_sw.l3_hit.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & ANY_SNOOPocr.pf_l3_data_rd.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_f.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_m.hitm_other_coreALL_PF_RFO & L3_HIT_M & HITM_OTHER_COREocr.demand_code_rd.l3_hit_f.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_F & HITM_OTHER_COREocr.demand_rfo.l3_hit.hit_other_core_fwdCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoopALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit.snoop_noneALL_DATA_RD & L3_HIT & SNOOP_NONEocr.demand_rfo.l3_hit_s.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_S & ANY_SNOOPocr.all_rfo.l3_hit_s.snoop_missALL_RFO & L3_HIT_S & SNOOP_MISSocr.all_pf_data_rd.l3_hit_e.any_snoopALL_PF_DATA_RD & L3_HIT_E & ANY_SNOOPocr.pf_l3_data_rd.l3_hit_e.snoop_missocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit.any_snoopCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & ANY_SNOOPocr.all_data_rd.l3_hit_m.snoop_missALL_DATA_RD & L3_HIT_M & SNOOP_MISSocr.pf_l3_data_rd.l3_hit_m.snoop_noneocr.pf_l3_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.all_pf_rfo.l3_hit_f.hit_other_core_fwdALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_e.snoop_noneALL_PF_RFO & L3_HIT_E & SNOOP_NONEocr.demand_rfo.l3_hit_e.hitm_other_coreCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_E & HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_m.snoop_missALL_PF_DATA_RD & L3_HIT_M & SNOOP_MISSocr.demand_rfo.l3_hit_e.no_snoop_neededCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l2_rfo.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.other.l3_hit_m.snoop_noneocr.demand_rfo.l3_hit_e.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_e.snoop_missocr.all_rfo.l3_hit_f.no_snoop_neededALL_RFO & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_e.no_snoop_neededALL_PF_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_m.snoop_missocr.demand_rfo.l3_hit_m.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_m.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & L3_HIT_M & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_f.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_F & HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_s.snoop_missocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.all_rfo.l3_hit_m.no_snoop_neededALL_RFO & L3_HIT_M & NO_SNOOP_NEEDEDocr.demand_data_rd.pmm_hit_local_pmm.any_snoopCounts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_data_rd.l3_hit_f.no_snoop_neededALL_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.demand_rfo.pmm_hit_local_pmm.any_snoopCounts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.other.l3_hit.any_snoopCounts any other requests OTHER & L3_HIT & ANY_SNOOPocr.pf_l3_data_rd.l3_hit_f.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_s.snoop_missALL_PF_RFO & L3_HIT_S & SNOOP_MISSocr.pf_l2_data_rd.l3_hit.hitm_other_coreCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HITM_OTHER_COREocr.all_reads.l3_hit_e.hitm_other_coreALL_READS & L3_HIT_E & HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_s.snoop_noneocr.demand_code_rd.pmm_hit_local_pmm.any_snoopCounts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOPocr.all_data_rd.l3_hit_e.hit_other_core_no_fwdALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.supplier_none.hit_other_core_fwdCounts demand data reads  DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.other.l3_hit_f.hit_other_core_fwdCounts any other requests  OTHER & L3_HIT_F & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.supplier_none.snoop_noneocr.demand_data_rd.l3_hit.any_snoopCounts demand data reads DEMAND_DATA_RD & L3_HIT & ANY_SNOOPocr.pf_l3_data_rd.l3_hit_m.snoop_missocr.pf_l1d_and_sw.l3_hit.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_MISSocr.all_pf_rfo.l3_hit.snoop_hit_with_fwdALL_PF_RFO & L3_HIT & SNOOP_HIT_WITH_FWDocr.all_pf_rfo.supplier_none.hitm_other_coreALL_PF_RFO & SUPPLIER_NONE & HITM_OTHER_COREocr.other.l3_hit_s.hit_other_core_no_fwdCounts any other requests  OTHER & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwdALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_s.snoop_noneocr.pf_l3_data_rd.supplier_none.snoop_missocr.all_reads.pmm_hit_local_pmm.snoop_not_neededALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l2_data_rd.l3_hit_m.any_snoopCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_M & ANY_SNOOPocr.pf_l2_data_rd.l3_hit_f.any_snoopCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_F & ANY_SNOOPocr.demand_code_rd.l3_hit.no_snoop_neededCounts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l3_rfo.l3_hit_f.snoop_missocr.pf_l3_data_rd.l3_hit_f.snoop_noneocr.pf_l2_rfo.l3_hit_m.snoop_missocr.pf_l3_data_rd.supplier_none.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_reads.l3_hit_m.hitm_other_coreALL_READS & L3_HIT_M & HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_s.snoop_missocr.all_reads.supplier_none.hitm_other_coreALL_READS & SUPPLIER_NONE & HITM_OTHER_COREocr.all_data_rd.l3_hit_m.any_snoopALL_DATA_RD & L3_HIT_M & ANY_SNOOPocr.all_rfo.l3_hit_e.no_snoop_neededALL_RFO & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_f.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_F & ANY_SNOOPocr.pf_l2_data_rd.l3_hit_m.snoop_missocr.pf_l3_data_rd.l3_hit_e.snoop_noneocr.demand_code_rd.l3_hit_f.snoop_noneocr.other.l3_hit.no_snoop_neededCounts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.all_pf_rfo.l3_hit_f.hitm_other_coreALL_PF_RFO & L3_HIT_F & HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_s.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_S & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit.snoop_hit_with_fwdocr.all_rfo.l3_hit.any_snoopALL_RFO & L3_HIT & ANY_SNOOPocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_e.no_snoop_neededCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.other.l3_hit_e.snoop_missocr.pf_l1d_and_sw.l3_hit_e.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_E & ANY_SNOOPocr.all_data_rd.supplier_none.any_snoopALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOPocr.all_rfo.l3_hit_m.snoop_noneALL_RFO & L3_HIT_M & SNOOP_NONEocr.pf_l2_rfo.supplier_none.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.demand_rfo.supplier_none.snoop_noneocr.demand_rfo.l3_hit_s.snoop_missocr.all_rfo.supplier_none.any_snoopALL_RFO & SUPPLIER_NONE & ANY_SNOOPocr.pf_l3_data_rd.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.demand_data_rd.supplier_none.hit_other_core_no_fwdCounts demand data reads  DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_m.hitm_other_coreALL_PF_DATA_RD & L3_HIT_M & HITM_OTHER_COREperiod=2000003,umask=0x8,event=0x32ocr.all_pf_data_rd.l3_hit_s.snoop_missALL_PF_DATA_RD & L3_HIT_S & SNOOP_MISSocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_e.hit_other_core_fwdALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_m.any_snoopALL_PF_RFO & L3_HIT_M & ANY_SNOOPocr.all_pf_rfo.l3_hit_m.snoop_missALL_PF_RFO & L3_HIT_M & SNOOP_MISSocr.pf_l2_data_rd.supplier_none.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwdALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit.any_snoopCounts all demand code reads DEMAND_CODE_RD & L3_HIT & ANY_SNOOPocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwdALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_e.snoop_missALL_RFO & L3_HIT_E & SNOOP_MISSocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l3_data_rd.l3_hit_m.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_M & HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_e.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_E & HITM_OTHER_COREocr.all_pf_rfo.supplier_none.no_snoop_neededALL_PF_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_s.hit_other_core_fwdALL_RFO & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_pf_rfo.supplier_none.hit_other_core_no_fwdALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDperiod=200003,umask=0x18,event=0x28ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.supplier_none.snoop_noneocr.pf_l2_rfo.l3_hit_m.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_M & HITM_OTHER_COREocr.demand_data_rd.pmm_hit_local_pmm.snoop_noneCounts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONEocr.demand_code_rd.l3_hit_e.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_e.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_E & ANY_SNOOPocr.all_pf_data_rd.l3_hit_s.snoop_noneALL_PF_DATA_RD & L3_HIT_S & SNOOP_NONEocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_e.any_snoopALL_RFO & L3_HIT_E & ANY_SNOOPocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWDocr.all_data_rd.pmm_hit_local_pmm.snoop_not_neededALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l3_data_rd.l3_hit_e.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_f.any_snoopCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_F & ANY_SNOOPocr.all_pf_rfo.l3_hit.snoop_noneALL_PF_RFO & L3_HIT & SNOOP_NONEperiod=203,umask=0x1,event=0xcbocr.pf_l3_data_rd.l3_hit_f.snoop_missocr.pf_l2_rfo.supplier_none.snoop_missocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdocr.pf_l2_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HITM_OTHER_COREocr.other.l3_hit_s.hitm_other_coreCounts any other requests  OTHER & L3_HIT_S & HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_s.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_m.snoop_noneocr.demand_rfo.l3_hit.snoop_noneCounts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_NONEocr.all_data_rd.l3_hit_m.hit_other_core_no_fwdALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.supplier_none.hit_other_core_fwdALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_s.no_snoop_neededALL_PF_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDEDocr.demand_rfo.any_responseocr.demand_code_rd.l3_hit_m.hitm_other_coreCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_M & HITM_OTHER_COREocr.demand_code_rd.supplier_none.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_s.snoop_noneocr.demand_rfo.supplier_none.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_s.hit_other_core_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.other.l3_hit_f.hit_other_core_no_fwdCounts any other requests  OTHER & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.any_responseocr.all_data_rd.l3_hit_e.snoop_missALL_DATA_RD & L3_HIT_E & SNOOP_MISSocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_m.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_M & NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_s.any_snoopCounts demand data reads  DEMAND_DATA_RD & L3_HIT_S & ANY_SNOOPocr.all_data_rd.l3_hit.snoop_missALL_DATA_RD & L3_HIT & SNOOP_MISSocr.other.l3_hit_m.hit_other_core_no_fwdCounts any other requests  OTHER & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit.any_snoopCounts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & ANY_SNOOPocr.other.l3_hit_f.snoop_missocr.all_pf_data_rd.l3_hit.snoop_noneALL_PF_DATA_RD & L3_HIT & SNOOP_NONEocr.all_pf_rfo.supplier_none.any_snoopALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOPocr.pf_l2_data_rd.l3_hit.no_snoop_neededCounts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l1d_and_sw.l3_hit_f.snoop_noneocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_f.hit_other_core_fwdALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_s.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_S & HITM_OTHER_COREocr.pf_l2_data_rd.supplier_none.snoop_noneocr.demand_code_rd.l3_hit_m.snoop_noneocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_m.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_M & HITM_OTHER_COREocr.demand_data_rd.supplier_none.snoop_missocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwdCounts demand data reads  DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_f.hit_other_core_no_fwdALL_READS & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_e.hitm_other_coreALL_RFO & L3_HIT_E & HITM_OTHER_COREocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwdocr.demand_rfo.l3_hit_f.hit_other_core_no_fwdCounts all demand data writes (RFOs)  DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_e.snoop_missocr.pf_l1d_and_sw.supplier_none.snoop_noneocr.all_data_rd.supplier_none.no_snoop_neededALL_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_s.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_S & ANY_SNOOPocr.all_pf_rfo.l3_hit_f.any_snoopALL_PF_RFO & L3_HIT_F & ANY_SNOOPocr.pf_l1d_and_sw.l3_hit.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_f.hitm_other_coreCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_F & HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_m.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_M & NO_SNOOP_NEEDEDocr.other.l3_hit.hitm_other_coreCounts any other requests OTHER & L3_HIT & HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_s.snoop_missocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_f.hitm_other_coreCounts demand data reads  DEMAND_DATA_RD & L3_HIT_F & HITM_OTHER_COREperiod=2000003,umask=0x1,event=0x32ocr.demand_code_rd.l3_hit_f.no_snoop_neededCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_F & NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_m.hit_other_core_fwdCounts all demand code reads  DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_s.snoop_noneALL_PF_RFO & L3_HIT_S & SNOOP_NONEocr.demand_code_rd.l3_hit_s.snoop_noneocr.pf_l1d_and_sw.l3_hit_m.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_M & NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_f.snoop_missocr.all_rfo.l3_hit_e.snoop_noneALL_RFO & L3_HIT_E & SNOOP_NONEocr.pf_l2_rfo.l3_hit_s.any_snoopCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_S & ANY_SNOOPocr.pf_l2_rfo.l3_hit_s.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  PF_L2_RFO & L3_HIT_S & NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_f.snoop_noneALL_RFO & L3_HIT_F & SNOOP_NONEocr.pf_l3_data_rd.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_m.no_snoop_neededCounts demand data reads  DEMAND_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWDocr.all_data_rd.supplier_none.hitm_other_coreALL_DATA_RD & SUPPLIER_NONE & HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwdALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.other.l3_hit_f.no_snoop_neededCounts any other requests  OTHER & L3_HIT_F & NO_SNOOP_NEEDEDocr.all_reads.l3_hit_s.any_snoopALL_READS & L3_HIT_S & ANY_SNOOPocr.demand_rfo.l3_hit_e.snoop_missocr.pf_l2_data_rd.supplier_none.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_f.snoop_noneocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWDocr.all_rfo.pmm_hit_local_pmm.snoop_not_neededALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_m.any_snoopCounts all prefetch (that bring data to LLC only) data reads  PF_L3_DATA_RD & L3_HIT_M & ANY_SNOOPocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDEDocr.all_data_rd.supplier_none.hit_other_core_fwdALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_s.snoop_missALL_READS & L3_HIT_S & SNOOP_MISSperiod=100007,umask=0x40,event=0xc4Far branch instructions retired  Spec update: SKL091 (Precise event)This event counts far branch instructions retired  Spec update: SKL091 (Precise event)cmask=4,period=2000003,umask=0x4,event=0xa3period=2000003,umask=0x20,event=0xecmask=10,inv=1,period=2000003,umask=0x2,event=0xc2period=2000003,event=0x3ccmask=1,inv=1,period=2000003,umask=0x2,event=0xc2cmask=1,inv=1,period=2000003,umask=0x2,event=0xb1any=1,period=2000003,umask=0x1,event=0xdcmask=4,period=2000003,umask=0x1,event=0xa8any=1,period=25003,umask=0x1,event=0x3cperiod=100007,umask=0x2,event=0xc4This event counts both direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)cmask=1,period=2000003,umask=0x1,event=0x14period=25003,umask=0x2,event=0x3cperiod=400009,umask=0x20,event=0xc5period=2000003,umask=0x20,event=0xccperiod=400009,umask=0x1,event=0xc4This event counts conditional branch instructions retired  Spec update: SKL091 (Precise event)period=2000003,umask=0x80,event=0xdcmask=1,period=2000003,umask=0x1,event=0xb1cmask=1,inv=1,period=2000003,umask=0x1,event=0xb1period=2000003,umask=0x10,event=0xa6cmask=5,period=2000003,umask=0x5,event=0xa3period=400009,umask=0x4,event=0xc5cmask=2,period=2000003,umask=0x1,event=0xb1period=25003,umask=0x1,event=0x3cperiod=400009,event=0xc4period=2000003,umask=0x1,event=0xa1period=2000003,umask=0x2,event=0xa1period=2000003,umask=0x4,event=0xa1period=2000003,umask=0x8,event=0xa1period=2000003,umask=0x10,event=0xa1period=2000003,umask=0x20,event=0xa1period=2000003,umask=0x40,event=0xa1period=2000003,umask=0x80,event=0xa1period=2000003,umask=0x8,event=0xa6cmask=1,edge=1,inv=1,period=2000003,umask=0x1,event=0x5ecmask=1,inv=1,period=2000003,umask=0x1,event=0xeperiod=2000003,umask=0x1,event=0xa8period=2000003,umask=0x1,event=0x87period=400009,umask=0x20,event=0xc4This event counts taken branch instructions retired  Spec update: SKL091 (Precise event)period=2000003,umask=0x1,event=0xeperiod=2000003,umask=0x1,event=0xa2cmask=20,period=2000003,umask=0x14,event=0xa3period=2000003,umask=0x1,event=0xa6period=2000003,umask=0x8,event=0xa2period=400009,umask=0x10,event=0xc4Not taken branch instructions retired  Spec update: SKL091This event counts not taken branch instructions retired  Spec update: SKL091cmask=12,period=2000003,umask=0xc,event=0xa3period=2000003,umask=0x4,event=0xa6period=2000003,umask=0x10,event=0xb1period=100003,umask=0x1,event=0x4cperiod=400009,umask=0x2,event=0xc5Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event)period=2000003,umask=0x1,event=0xb1cmask=3,period=2000003,umask=0x1,event=0xb1cmask=1,period=2000003,umask=0x1,event=0xa8period=2000003,umask=0x1,event=0xdcmask=8,period=2000003,umask=0x8,event=0xa3period=2000003,umask=0x1,event=0xc0br_inst_retired.cond_ntakencmask=3,period=2000003,umask=0x2,event=0xb1cmask=1,period=2000003,umask=0x2,event=0xb1cmask=4,period=2000003,umask=0x2,event=0xb1period=100003,umask=0x3f,event=0xc1period=2000003,umask=0x40,event=0xa6cmask=16,period=2000003,umask=0x10,event=0xa3period=2000003,umask=0x40,event=0xcccmask=4,period=2000003,umask=0x1,event=0xb1period=2000003,umask=0x1,event=0x59period=2000003,umask=0x2,event=0xc2period=2000003,umask=0x2,event=0xeCounts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guideperiod=100007,umask=0x8,event=0xc4This event counts return instructions retired  Spec update: SKL091 (Precise event)cmask=2,period=2000003,umask=0x2,event=0xb1period=400009,umask=0x1,event=0xc5cmask=10,inv=1,period=2000003,umask=0x1,event=0xc0period=100003,umask=0x1,event=0x7cmask=1,edge=1,period=100003,umask=0x1,event=0xc3period=100003,umask=0x1,event=0xe6period=100003,umask=0x2,event=0x3Loads blocked due to overlapping with a preceding store that cannot be forwardedCounts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guideperiod=2000003,umask=0x3,event=0period=400009,event=0xc5period=100003,umask=0x8,event=0x3period=100003,umask=0x4,event=0xc3any=1,period=2000003,event=0x3cperiod=2000003,umask=0x1,event=0x5ecmask=1,edge=1,period=100007,event=0x3cperiod=400009,umask=0x4,event=0xc4period=2000003,umask=0x2,event=0xa6period=2000003,umask=0x2,event=0xb1cmask=1,period=2000003,umask=0x1,event=0xa3Cycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc unc_m_pmm_rpq_insertsevent=0xe3Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_wpq_insertsevent=0xe7unc_m_pmm_bandwidth.readIntel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc 6.103515625E-5MB/secunc_m_pmm_bandwidth.writeIntel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc unc_m_pmm_bandwidth.totalIntel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc unc_m_pmm_rpq_inserts + unc_m_pmm_wpq_insertsUNC_M_PMM_BANDWIDTH.TOTALunc_m_pmm_rpq_occupancy.allumask=0x1,event=0xe0Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_read_latencyIntel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc 6000000000nsunc_m_pmm_rpq_occupancy.all / unc_m_pmm_rpq_inserts / unc_m_clockticksUNC_M_PMM_READ_LATENCYAll DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc unc_m_cas_count.wr_wmmumask=0x4,event=0x4DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Modeunc_m_pmm_cmd1.allumask=0x1,event=0xeaAll commands for Intel Optane DC persistent memory. Unit: uncore_imc All commands for Intel Optane DC persistent memoryunc_m_pmm_cmd1.rdumask=0x2,event=0xeaRegular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc All Reads - RPQ or Ufillunc_m_pmm_cmd1.ufill_rdumask=0x8,event=0xeaUnderfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc Underfill readsunc_m_pmm_cmd1.wrumask=0x4,event=0xeaWrite commands for Intel Optane DC persistent memory. Unit: uncore_imc Writesunc_m_pmm_wpq_occupancy.allumask=0x1,event=0xe4Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memoryunc_m_tagchk.hitumask=0x1,event=0xd3All hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Hitunc_m_tagchk.miss_cleanumask=0x2,event=0xd3All Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Cleanunc_m_tagchk.miss_dirtyumask=0x4,event=0xd3All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; DirtyCounts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???umask=0xf,event=0x2unc_iio_data_req_of_cpu.mem_write.part0 + unc_iio_data_req_of_cpu.mem_write.part1 + unc_iio_data_req_of_cpu.mem_write.part2 + unc_iio_data_req_of_cpu.mem_write.part3unc_cha_fast_asserted.horzumask=0x02,event=0xa5FaST wire asserted; Horizontal. Unit: uncore_cha Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and acrossunc_cha_llc_victims.total_eumask=0x02,event=0x37Lines Victimized; Lines in E state. Unit: uncore_cha Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was inunc_cha_llc_victims.total_fumask=0x08,event=0x37Lines Victimized; Lines in F State. Unit: uncore_cha unc_cha_llc_victims.total_mumask=0x01,event=0x37Lines Victimized; Lines in M state. Unit: uncore_cha unc_cha_llc_victims.total_sumask=0x04,event=0x37Lines Victimized; Lines in S State. Unit: uncore_cha unc_cha_rxc_inserts.irqumask=0x01,event=0x13Ingress (from CMS) Allocations; IRQ. Unit: uncore_cha Counts number of allocations per cycle into the specified Ingress queueunc_cha_rxc_irq1_reject.pa_matchumask=0x80,event=0x19Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Matchunc_cha_rxc_occupancy.irqumask=0x01,event=0x11Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha Counts number of entries in the specified Ingress queue in each cycleunc_cha_sf_eviction.e_stateumask=0x02,event=0x3dSnoop filter capacity evictions for E-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_cha_sf_eviction.m_stateumask=0x01,event=0x3dSnoop filter capacity evictions for M-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_cha_sf_eviction.s_stateumask=0x04,event=0x3dSnoop filter capacity evictions for S-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineCounts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownershipCounts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busWrite request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busWrite request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc0Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc0Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc0Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc0Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc0Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc0Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc0Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc0Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x83Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x83Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x83Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x83Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x83Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x83Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x83Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x83Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc1Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc1Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc1Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc1Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc1Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc1Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc1Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc1Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x84Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part1fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x84Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part2fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x84Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x84Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part0fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x84Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x84Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x84Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part3fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x84Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busMulti-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m Multi-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m Multi-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Multi-socket cacheline Directory update from/to Any state. Unit: uncore_m2m unc_m2m_imc_reads.to_pmmumask=0x8,event=0x37Read requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m M2M Reads Issued to iMC; All, regardless of priorityunc_m2m_imc_writes.niumask=0x80,event=0x38M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priorityunc_m2m_imc_writes.to_pmmumask=0x20,event=0x38Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable MemoryCounts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, andunc_m2m_rxc_ad_occupancyevent=0x2AD Ingress (from CMS) Occupancy. Unit: uncore_m2m AD Ingress (from CMS) Occupancyunc_m2m_rxc_bl_insertsBL Ingress (from CMS) Allocations. Unit: uncore_m2m BL Ingress (from CMS) Allocationsunc_m2m_rxc_bl_occupancyBL Ingress (from CMS) Occupancy. Unit: uncore_m2m BL Ingress (from CMS) Occupancyunc_m2m_tag_hit.nm_rd_hit_dirtyumask=0x02,event=0x2cDirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Read Hit from NearMem, Dirty  Lineunc_m2m_tag_hit.nm_ufill_hit_cleanumask=0x04,event=0x2cClean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Clean Lineunc_m2m_tag_hit.nm_ufill_hit_dirtyumask=0x08,event=0x2cDirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Dirty  Lineunc_m2m_txc_ad_insertsevent=0x9AD Egress (to CMS) Allocations. Unit: uncore_m2m AD Egress (to CMS) Allocationsunc_m2m_txc_ad_occupancyAD Egress (to CMS) Occupancy. Unit: uncore_m2m AD Egress (to CMS) Occupancyunc_m2m_txc_bl_inserts.allumask=0x03,event=0x15BL Egress (to CMS) Allocations; All. Unit: uncore_m2m BL Egress (to CMS) Allocations; Allunc_m2m_txc_bl_occupancy.allumask=0x03,event=0x16BL Egress (to CMS) Occupancy; All. Unit: uncore_m2m BL Egress (to CMS) Occupancy; AllCounts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyCounts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyFLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_txl_flits.dataValid Flits Sent; Data. Unit: uncore_upi ll Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting.period=100003,umask=0x4,event=0x49period=100003,umask=0x10,event=0x85period=100003,umask=0xe,event=0x85period=100003,umask=0x1,event=0x8period=100007,umask=0x20,event=0xbdcmask=1,period=100003,umask=0x10,event=0x8period=100003,umask=0x8,event=0x49period=100003,umask=0x1,event=0x49period=100007,umask=0x1,event=0xaeperiod=2000003,umask=0x10,event=0x49period=2000003,umask=0x2,event=0x8period=2000003,umask=0x4,event=0x8period=2000003,umask=0x10,event=0x8period=2000003,umask=0x10,event=0x4fcmask=1,period=100003,umask=0x10,event=0x49period=100003,umask=0x1,event=0x85period=100003,umask=0x20,event=0x49period=100003,umask=0xe,event=0x8period=100003,umask=0x2,event=0x49period=100003,umask=0x2,event=0x85period=100003,umask=0x8,event=0x85period=100003,umask=0x20,event=0x85period=2000003,umask=0x8,event=0x8period=100003,umask=0x4,event=0x85period=100003,umask=0xe,event=0x49cmask=1,period=100003,umask=0x10,event=0x85period=2000003,umask=0x20,event=0x8period=100007,umask=0x1,event=0xbdCounts demand requests that miss L2 cachel2_rqsts.swpf_missumask=0x28,period=200003,event=0x24SW prefetch requests that miss L2 cacheCounts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructionsCounts the number of demand Data Read requests initiated by load instructions that hit L2 cachel2_rqsts.swpf_hitumask=0xc8,period=200003,event=0x24SW prefetch requests that hit L2 cacheCounts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructionsCounts demand requests to L2 cacheNumber of L1D misses that are outstandingCounts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeNumber of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablabilityCounts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesl1d_pend_miss.fb_full_periodsumask=0x2,period=2000003,cmask=1,edge=1,event=0x48Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablabilityCounts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesl1d_pend_miss.l2_stallumask=0x4,period=2000003,event=0x48Number of cycles a demand request has waited due to L1D due to lack of L2 resourcesCounts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesCounts the number of cache lines replaced in L1 data cacheCounts retired load instructions that true miss the STLB  Supports address when precise (Precise event)Counts retired store instructions that true miss the STLB  Supports address when precise (Precise event)Counts retired load instructions with locked access  Supports address when precise (Precise event)Counts all retired load instructions. This event accounts for SW prefetch instructions for loads  Supports address when precise (Precise event)Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores  Supports address when precise (Precise event)Counts retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)Counts retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise (Precise event)Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Counts retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)Counts retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)sq_misc.sq_fullumask=0x4,period=100003,event=0xf4Cycles the thread is active and superQ cannot take any more entriesCounts the cycles for which the thread is active and the superQ cannot take any more entriesassists.fpumask=0x2,period=100003,cmask=1,event=0xc1Counts all microcode FP assistsCounts all microcode Floating Point assistsNumber of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.mite_cycles_okumask=0x4,period=2000003,cmask=5,event=0x79Cycles MITE is delivering optimal number of UopsCounts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)idq.mite_cycles_anyCounts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathidq.dsb_cycles_okumask=0x8,period=2000003,cmask=5,event=0x79Cycles DSB is delivering optimal number of Uopsidq.dsb_cycles_anyCounts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathumask=0x30,period=2000003,cmask=1,edge=1,event=0x79Number of switches from DSB or MITE to the MSUops delivered to IDQ while MS is busyidq.ms_cycles_anyCycles when uops are being delivered to IDQ while MS is busyCounts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITECounts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularityCounts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesCounts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesCounts cycles where a code fetch is stalled due to L1 instruction cache tag missUops not delivered by IDQ when backend of the machine is not stalledCounts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleumask=0x1,period=2000003,cmask=5,event=0x9cCycles when no uops are not delivered by the IDQ when backend of the machine is not stalledCounts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleCycles when optimal number of uops was delivered to the back-end when the back-end is not stalledCounts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleDSB-to-MITE switch true penalty cyclesDecode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITERetired Instructions who experienced DSB miss (Precise event)Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event)Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x500206Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x500406Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x500806umask=0x1,period=100007,event=0xc6,frontend=0x501006umask=0x1,period=100007,event=0xc6,frontend=0x502006umask=0x1,period=100007,event=0xc6,frontend=0x504006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x508006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x510006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)umask=0x1,period=100007,event=0xc6,frontend=0x520006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)Counts the number of times a TSX line had a cache conflictSpeculatively counts the number TSX Aborts due to a data capacity limitation for transactional writesSpeculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writesumask=0x4,period=100003,event=0x54Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lockCounts the number of times a TSX Abort was triggered due to commit but Lock Buffer not emptyCounts the number of times a TSX Abort was triggered due to release/commit but data and address mismatchCounts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock BufferCounts the number of times we could not allocate Lock BufferCounts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionCounts Unfriendly TSX abort triggered by a vzeroupper instructionNumber of times an instruction execution caused the transactional nest count supported to be exceededCounts Unfriendly TSX abort triggered by a nest count that is too deepNumber of machine clears due to memory ordering conflictsCounts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architectureCounts the number of times we entered an HLE region. Does not count nested transactionsNumber of times an HLE execution successfully committed  Supports address when preciseCounts the number of times HLE commit succeeded  Supports address when preciseNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one)Counts the number of times HLE abort was triggeredCounts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts)Counts the number of times we entered an RTM region. Does not count nested transactionsCounts the number of times RTM commit succeededNumber of times an RTM execution aborted  Supports address when preciseCounts the number of times RTM abort was triggered  Supports address when preciseCounts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)Counts the number of times an RTM execution aborted due to HLE-unfriendly instructionsCounts the number of times an RTM execution aborted due to incompatible memory typeCounts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)topdown.slotsumask=0x4,period=10000003,event=0Counts the number of available slots for an unhalted logical processorCounts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the Top-down Microarchitecture Analysis method. This event is counted on a designated fixed counter (Fixed Counter 3) and is an architectural eventCounts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codesCounts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionsCore cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructionsCounts the number of PREFETCHNTA instructions executedCounts the number of PREFETCHT0 instructions executedCounts the number of PREFETCHT1 or PREFETCHT2 instructions executedCounts the number of PREFETCHW instructions executedtopdown.slots_pumask=0x1,period=10000003,event=0xa4Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical coretopdown.backend_bound_slotsumask=0x2,period=10000003,event=0xa4Issue slots where no uops were being issued due to lack of back end resourcesassists.anyumask=0x7,period=100003,event=0xc1Number of occurrences where a microcode assist is invoked by hardwareCounts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assistsNumber of instructions retired. Fixed Counter - architectural eventCounts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counterumask=0x1,period=2000003,event=0Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Must be precise)A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Must be precise)Counts the number of times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations, c. preceding lock RMW operations are not forwarded, d. store has the no-forward bit set (uncacheable/page-split/masked stores), e. all-blocking stores are used (mostly, fences and port I/O), and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization GuideCounts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useCounts the number of times a load got blocked due to false dependencies in MOB due to partial compare on addressCore cycles the allocator was stalled due to recovery from earlier clear event for this threadCounts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventint_misc.all_recovery_cyclesCycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallCounts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallCounts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathCycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathUops that RAT issues to RSCycles when RAT does not issue Uops to RS for the threadumask=0x9,period=2000003,cmask=1,event=0x14Cycles when divide unit is busy executing divide or square root operationsCounts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationsumask=0x1,period=25003,event=0x3cCounts core crystal clock cycles when the thread is unhaltedumask=0x2,period=25003,event=0x3cCounts Core crystal clock cycles when current thread is unhalted and the other thread is haltedload_hit_prefetch.swpfCounts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCounts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)inv=1,umask=0x1,period=2000003,cmask=1,edge=1,event=0x5eCounts end of periods where the Reservation Station (RS) was emptyCounts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)uops_dispatched.port_0Number of uops executed on port 0uops_dispatched.port_1Number of uops executed on port 1uops_dispatched.port_2_3Number of uops executed on port 2 and 3Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3uops_dispatched.port_4_9Number of uops executed on port 4 and 9Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9uops_dispatched.port_5Number of uops executed on port 5uops_dispatched.port_6Number of uops executed on port 6uops_dispatched.port_7_8Number of uops executed on port 7 and 8Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8resource_stalls.scoreboardCounts cycles where the pipeline is stalled due to serializing operationsumask=0x40,period=2000003,cmask=2,event=0xa6Cycles where the Store Buffer was full and no loads caused an execution stallCounts cycles where the Store Buffer was full and no loads caused an execution stallumask=0x80,period=2000003,event=0xa6Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector)lsd.cycles_okumask=0x1,period=2000003,cmask=5,event=0xa8Cycles optimal number of Uops delivered by the LSD, but did not come from the decoderCounts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector)uops_executed.cycles_ge_1uops_executed.cycles_ge_2uops_executed.cycles_ge_3uops_executed.cycles_ge_4Counts the number of uops executed from any threadCounts cycles when at least 1 micro-op is executed from any thread on physical coreCounts cycles when at least 2 micro-ops are executed from any thread on physical coreCounts cycles when at least 3 micro-ops are executed from any thread on physical coreCounts cycles when at least 4 micro-ops are executed from any thread on physical coreNumber of instructions retired. General Counter - architectural eventCounts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired eventuops_retired.slotsCounts the retirement slots used each cycleumask=0x1,period=100003,cmask=1,edge=1,event=0xc3Counts the number of machine clears (nukes) of any typeAll branch instructions retired (Precise event)Counts all branch instructions retired (Precise event)br_inst_retired.cond_takenTaken conditional branch instructions retired (Precise event)Counts taken conditional branch instructions retired (Precise event)Counts both direct and indirect near call instructions retired (Precise event)Counts return instructions retired (Precise event)Not taken branch instructions retired (Precise event)Counts not taken branch instructions retired (Precise event)br_inst_retired.condumask=0x11,period=400009,event=0xc4Counts conditional branch instructions retired (Precise event)Counts taken branch instructions retired (Precise event)Far branch instructions retired (Precise event)Counts far branch instructions retired (Precise event)br_inst_retired.indirectumask=0x80,period=100003,event=0xc4All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch) (Precise event)Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)All mispredicted branch instructions retired  Supports address when precise (Precise event)Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path  Supports address when precise (Precise event)br_misp_retired.cond_takennumber of branch instructions retired that were mispredicted and taken. Non PEBS  Supports address when precise (Precise event)Counts taken conditional mispredicted branch instructions retired  Supports address when precise (Precise event)br_misp_retired.condumask=0x11,period=400009,event=0xc5Mispredicted conditional branch instructions retired  Supports address when precise (Precise event)Counts mispredicted conditional branch instructions retired  Supports address when precise (Precise event)Number of near branch instructions retired that were mispredicted and taken  Supports address when precise (Precise event)Counts number of near branch instructions retired that were mispredicted and taken  Supports address when precise (Precise event)br_misp_retired.indirectumask=0x80,period=100003,event=0xc5All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch)  Supports address when precise (Precise event)Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch)  Supports address when precise (Precise event)misc_retired.lbr_insertsmisc_retired.pause_instNumber of retired PAUSE instructionsCounts number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted)cpu_clk_unhalted.distributedumask=0x2,period=2000003,event=0xecCycle counts are evenly distributed between active threads in the CoreThis event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthreadPage walks completed due to a demand data load to a 4K pagePage walks completed due to a demand data load to a 2M/4M pageNumber of page walks outstanding for a demand load in the PMH each cycleCounts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycleCycles when at least one PMH is busy with a page walk for a demand loadCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand loadPage walks completed due to a demand data store to a 4K pagePage walks completed due to a demand data store to a 2M/4M pageNumber of page walks outstanding for a store in the PMH each cycleCounts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycleCycles when at least one PMH is busy with a page walk for a storeCounts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a faultCounts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultNumber of page walks outstanding for an outstanding code request in the PMH each cycleCounts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycleCycles when at least one PMH is busy with a page walk for code (instruction fetch) requestCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) requestCounts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB)Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts cacheable memory requests that miss in the the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts cacheable memory requests that access the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts the number of load uops retired  Supports address when precise (Precise event)Counts the number of load uops retired. This event is Precise Event capable  Supports address when precise (Precise event)Counts the number of store uops retired  Supports address when precise (Precise event)Counts the number of store uops retired. This event is Precise Event capable  Supports address when precise (Precise event)Counts the number of load uops retired that hit the level 1 data cache  Supports address when precise (Precise event)Counts the number of load uops retired that hit in the level 2 cache  Supports address when precise (Precise event)umask=0x4,period=200003,event=0xd1Counts the number of load uops retired that miss in the level 3 cache (Precise event)Counts the number of load uops retired that miss in the level 1 data cache  Supports address when precise (Precise event)Counts the number of load uops retired that miss in the level 2 cache  Supports address when precise (Precise event)Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss)Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICacheCounts requests to the Instruction Cache (ICache) for one or more bytes cache LineCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new lineocr.demand_data_rd.l3_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000001Counts demand data reads that was not supplied by the L3 cacheocr.demand_rfo.l3_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000002Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010001Counts demand data reads that have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010002Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response typeCounts the number of instructions retired. (Fixed event) (Precise event)Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0 (Precise event)Counts the number of unhalted core clock cycles. (Fixed event)Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  The core frequency may change from time.  This event is not affected by core frequency changes and at a fixed frequency.  This event uses fixed counter 2Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses a programmable general purpose performance counterCounts the number of unhalted reference clock cycles at TSC frequencyCounts reference cycles (at TSC frequency) when core is not halted.  This event uses a programmable general purpose perfmon counterCounts the number of instructions retired (Precise event)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event (Precise event)machine_clears.anyperiod=20003,event=0xc3Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assistperiod=200003,event=0xc4Counts the number of branch instructions retired for all branch types (Precise event)Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event)period=200003,event=0xc5Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event)cycles_div_busy.anyperiod=2000003,event=0xcdCounts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either dividerumask=0x0f,event=0x4umask=0x30,event=0x4umask=0x04,event=0x2umask=0x08,event=0x2unc_m_pre_count.allumask=0x1c,event=0x2Precharge due to read on page miss, write on page miss or PGT. Unit: uncore_imc unc_m_pre_count.pgtumask=0x10,event=0x2DRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channelumask=0xC001FE01,event=0x35,config1=0x40e33umask=0xC001FE01,event=0x35,config1=0x40040e33umask=0xC001FE01,event=0x35,config1=0x40041e33umask=0xC001FE01,event=0x35,config1=0x41833umask=0xC001FE01,event=0x35,config1=0x41a33unc_iio_data_req_of_cpu.mem_read.part0 +unc_iio_data_req_of_cpu.mem_read.part1 +unc_iio_data_req_of_cpu.mem_read.part2 +unc_iio_data_req_of_cpu.mem_read.part3unc_cha_tor_inserts.ia_miss_crdumask=0xC80FFE01,event=0x35TOR Inserts; CRd misses from local IA. Unit: uncore_cha TOR Inserts; Code read from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_crd_prefumask=0xC88FFE01,event=0x35TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha TOR Inserts; Code read prefetch from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_drd_optumask=0xC827FE01,event=0x35TOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha TOR Inserts; Data read opt from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_drd_opt_prefumask=0xC8A7FE01,event=0x35TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_rfoumask=0xC807FE01,event=0x35TOR Inserts; RFO misses from local IA. Unit: uncore_cha TOR Inserts; Read for ownership from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_rfo_prefumask=0xC887FE01,event=0x35TOR Inserts; RFO pref misses from local IA. Unit: uncore_cha TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_wcilumask=0xC86FFE01,event=0x35TOR Inserts; WCiL misses from local IA. Unit: uncore_cha TOR Inserts; Data read from local IA that misses in the snoop filterunc_cha_tor_inserts.ia_miss_wcilfumask=0xC867FE01,event=0x35TOR Inserts; WCiLF misses from local IA. Unit: uncore_cha Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio Clockticks of the integrated IO (IIO) traffic controllerunc_iio_data_req_of_cpu.mem_read.part4fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0x83Data requested of the CPU : Card reading from DRAM. Unit: uncore_iio Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0unc_iio_data_req_of_cpu.mem_read.part5fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0x83Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1unc_iio_data_req_of_cpu.mem_read.part6fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0x83Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1unc_iio_data_req_of_cpu.mem_read.part7fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0x83Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3unc_iio_data_req_of_cpu.mem_write.part4fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0x83Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0unc_iio_data_req_of_cpu.mem_write.part5fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0x83Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1unc_iio_data_req_of_cpu.mem_write.part6fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0x83Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1unc_iio_data_req_of_cpu.mem_write.part7fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0x83Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3unc_i_clockticksClockticks of the IO coherency tracker (IRP). Unit: uncore_irp Clockticks of the IO coherency tracker (IRP)uncore_irpunc_m2m_clockticksClockticks of the mesh to memory (M2M). Unit: uncore_m2m Clockticks of the mesh to memory (M2M)unc_m2p_clockticksClockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie Clockticks of the mesh to PCI (M2P)uncore_m2pcieunc_u_clockticksevent=0xffClockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox Clockticks in the UBOX using a dedicated 48-bit Fixed Counteruncore_uboxClockticks of the power control unit (PCU). Unit: uncore_pcu Clockticks of the power control unit (PCU)itlb.fillsCounts the number of times there was an ITLB miss and a new translation was filled into the ITLBCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBbp_l1_btb_correctevent=0x8aL1 BTB Correctionbranchbp_l2_btb_correctevent=0x8bL2 BTB Correctionbp_dyn_ind_predevent=0x8eDynamic Indirect PredictionsIndirect Branch Prediction for potential multi-target branch (speculative)bp_de_redirectevent=0x91Decoder Overrides Existing Branch Prediction (speculative)ic_fw32The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)ic_fw32_missThe number of 32B fetch windows tried to read the L1 IC and missed in the full tagic_cache_fill_l2event=0x82The number of 64 byte instruction cache line was fulfilled from the L2 cacheic_cache_fill_sysevent=0x83The number of 64 byte instruction cache line fulfilled from system memory or another cachebp_l1_tlb_miss_l2_hitevent=0x84The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBbp_l1_tlb_miss_l2_missThe number of instruction fetches that miss in both the L1 and L2 TLBsbp_snp_re_syncThe number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely eventic_fetch_stall.ic_stall_anyumask=0x4,event=0x87Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1)ic_fetch_stall.ic_stall_dq_emptyumask=0x2,event=0x87Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ emptyic_fetch_stall.ic_stall_back_pressureumask=0x1,event=0x87Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressureic_cache_inval.l2_invalidating_probeumask=0x2,event=0x8cIC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another coreic_cache_inval.fill_invalidatedumask=0x1,event=0x8cIC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another corebp_tlb_relevent=0x99The number of ITLB reload requestsl2_request_g1.rd_blk_lumask=0x80,event=0x60All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch)l2_request_g1.rd_blk_xumask=0x40,event=0x60All L2 Cache Requests (Breakdown 1 - Common). Data cache storesl2_request_g1.ls_rd_blk_c_sumask=0x20,event=0x60All L2 Cache Requests (Breakdown 1 - Common). Data cache shared readsl2_request_g1.cacheable_ic_readumask=0x10,event=0x60All L2 Cache Requests (Breakdown 1 - Common). Instruction cache readsl2_request_g1.change_to_xumask=0x8,event=0x60All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current statel2_request_g1.prefetch_l2_cmdumask=0x4,event=0x60All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmdl2_request_g1.l2_hw_pfumask=0x2,event=0x60All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon eventl2_request_g1.group2umask=0x1,event=0x60Miscellaneous events covered in more detail by l2_request_g2 (PMCx061)l2_request_g2.group1umask=0x80,event=0x61Miscellaneous events covered in more detail by l2_request_g1 (PMCx060)l2_request_g2.ls_rd_sizedumask=0x40,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sizedl2_request_g2.ls_rd_sized_ncumask=0x20,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheablel2_request_g2.ic_rd_sizedumask=0x10,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sizedl2_request_g2.ic_rd_sized_ncumask=0x8,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheablel2_request_g2.smc_invalumask=0x4,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidatesl2_request_g2.bus_locks_originatorumask=0x2,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Bus locksl2_request_g2.bus_locks_responsesumask=0x1,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Bus lock responsel2_latency.l2_cycles_waiting_on_fillsumask=0x1,event=0x62Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be usedl2_wcb_req.wcb_writeumask=0x40,event=0x63LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requestsl2_wcb_req.wcb_closeumask=0x20,event=0x63LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requestsl2_wcb_req.zero_byte_storeumask=0x4,event=0x63LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requestsl2_wcb_req.cl_zeroumask=0x1,event=0x63LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requestsl2_cache_req_stat.ls_rd_blk_csumask=0x80,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_xumask=0x40,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_sumask=0x20,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2l2_cache_req_stat.ls_rd_blk_xumask=0x10,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2l2_cache_req_stat.ls_rd_blk_cumask=0x8,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types)l2_cache_req_stat.ic_fill_hit_xumask=0x4,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2l2_cache_req_stat.ic_fill_hit_sumask=0x2,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2l2_cache_req_stat.ic_fill_missumask=0x1,event=0x64Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2l2_fill_pending.l2_fill_busyumask=0x1,event=0x6dCycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2l3_request_g1.caching_l3_cache_accessesumask=0x80,event=0x1Caching: L3 cache accesses. Unit: uncore_l3pmc uncore_l3pmcl3_lookup_state.all_l3_req_typsumask=0xff,event=0x4All L3 Request Types. Unit: uncore_l3pmc l3_comb_clstr_state.other_l3_miss_typsumask=0xfe,event=0x6Other L3 Miss Request Types. Unit: uncore_l3pmc l3_comb_clstr_state.request_missumask=0x01,event=0x6L3 cache misses. Unit: uncore_l3pmc xi_sys_fill_latencyumask=0x00,event=0x90L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc xi_ccx_sdp_req1.all_l3_miss_req_typsumask=0x3f,event=0x9aAll L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc ex_ret_instrRetired Instructionsex_ret_copsevent=0xc1Retired UopsThe number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4ex_ret_brnevent=0xc2Retired Branch InstructionsThe number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interruptsex_ret_brn_mispevent=0xc3Retired Branch Instructions MispredictedThe number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)ex_ret_brn_tknevent=0xc4Retired Taken Branch InstructionsThe number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interruptsex_ret_brn_tkn_mispevent=0xc5Retired Taken Branch Instructions MispredictedThe number of retired taken branch instructions that were mispredictedex_ret_brn_farevent=0xc6Retired Far Control TransfersThe number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch predictionex_ret_brn_resyncevent=0xc7Retired Branch ResyncsThe number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rareex_ret_near_retevent=0xc8Retired Near ReturnsThe number of near return instructions (RET or RET Iw) retiredex_ret_near_ret_mispredevent=0xc9Retired Near Returns MispredictedThe number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instructionex_ret_brn_ind_mispevent=0xcaRetired Indirect Branch Instructions Mispredictedex_ret_mmx_fp_instr.sse_instrumask=0x4,event=0xcbSSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)ex_ret_mmx_fp_instr.mmx_instrumask=0x2,event=0xcbMMX instructionsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructionsex_ret_mmx_fp_instr.x87_instrumask=0x1,event=0xcbx87 instructionsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructionsex_ret_condevent=0xd1Retired Conditional Branch Instructionsex_div_busyevent=0xd3Div Cycles Busy countex_div_countevent=0xd4Div Op Countex_tagged_ibs_ops.ibs_count_rolloverumask=0x4,event=0x1cfTagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retiredex_tagged_ibs_ops.ibs_tagged_ops_retumask=0x2,event=0x1cfTagged IBS Ops. Number of Ops tagged by IBS that retiredex_tagged_ibs_ops.ibs_tagged_opsumask=0x1,event=0x1cfTagged IBS Ops. Number of Ops tagged by IBSex_ret_fus_brnch_instevent=0x1d0The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3df_ccm_reqa.node0.anydramumask=0x0F,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transactiondata fabricdf_ccm_reqa.node1.anydramumask=0x2F,event=0x8bdf_ccm_reqa.node2.anydramumask=0x4F,event=0x8bdf_ccm_reqa.node3.anydramumask=0x6F,event=0x8bdf_ccm_reqa.node4.anydramumask=0x8F,event=0x8bdf_ccm_reqa.node5.anydramumask=0xAF,event=0x8bdf_ccm_reqa.node6.anydramumask=0xCF,event=0x8bdf_ccm_reqa.node7.anydramumask=0xEF,event=0x8bdf_ccm_reqa.node0.wrsizedfullzeroumask=0x0E,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZerodf_ccm_reqa.node1.wrsizedfullzeroumask=0x2E,event=0x8bdf_ccm_reqa.node2.wrsizedfullzeroumask=0x4E,event=0x8bdf_ccm_reqa.node3.wrsizedfullzeroumask=0x6E,event=0x8edf_ccm_reqa.node4.wrsizedfullzeroumask=0x8E,event=0x8bdf_ccm_reqa.node5.wrsizedfullzeroumask=0xAE,event=0x8bdf_ccm_reqa.node6.wrsizedfullzeroumask=0xCE,event=0x8bdf_ccm_reqa.node7.wrsizedfullzeroumask=0xEE,event=0x8bdf_ccm_reqa.node0.wrsizedfullncumask=0x0D,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncdf_ccm_reqa.node1.wrsizedfullncumask=0x2D,event=0x8adf_ccm_reqa.node2.wrsizedfullncumask=0x4D,event=0x8bdf_ccm_reqa.node3.wrsizedfullncumask=0x6D,event=0x8bdf_ccm_reqa.node4.wrsizedfullncumask=0x8D,event=0x8bdf_ccm_reqa.node5.wrsizedfullncumask=0xAD,event=0x8bdf_ccm_reqa.node6.wrsizedfullncumask=0xCD,event=0x8bdf_ccm_reqa.node7.wrsizedfullncumask=0xED,event=0x8bdf_ccm_reqa.node0.wrsizedumask=0x0C,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizeddf_ccm_reqa.node1.wrsizedumask=0x2C,event=0x8bdf_ccm_reqa.node2.wrsizedumask=0x4C,event=0x8bdf_ccm_reqa.node3.wrsizedumask=0x6C,event=0x8bdf_ccm_reqa.node4.wrsizedumask=0x8C,event=0x8bdf_ccm_reqa.node5.wrsizedumask=0xAC,event=0x8bdf_ccm_reqa.node6.wrsizedumask=0xCC,event=0x8bdf_ccm_reqa.node7.wrsizedumask=0xEC,event=0x8bumask=0x0B,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzeroumask=0x2B,event=0x8bumask=0x4B,event=0x8bumask=0x6B,event=0x8bumask=0x8B,event=0x8bumask=0xAB,event=0x8bumask=0xCB,event=0x8bumask=0xEB,event=0x8bumask=0x0A,event=0x8bumask=0x2A,event=0x8bumask=0x4A,event=0x8bumask=0x6A,event=0x8bumask=0x8A,event=0x8bumask=0xAA,event=0x8bumask=0xCA,event=0x8bumask=0xEA,event=0x8bumask=0x09,event=0x8bumask=0x29,event=0x8bumask=0x49,event=0x8bumask=0x69,event=0x8bumask=0x89,event=0x8bumask=0xA9,event=0x8bumask=0xC9,event=0x8bumask=0xE9,event=0x8bdf_ccm_reqa.node0.rdsizedncumask=0x08,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizedncdf_ccm_reqa.node1.rdsizedncumask=0x28,event=0x8bdf_ccm_reqa.node2.rdsizedncumask=0x48,event=0x8bdf_ccm_reqa.node3.rdsizedncumask=0x68,event=0x8bdf_ccm_reqa.node4.rdsizedncumask=0x88,event=0x8bdf_ccm_reqa.node5.rdsizedncumask=0xA8,event=0x8bdf_ccm_reqa.node6.rdsizedncumask=0xC8,event=0x8bdf_ccm_reqa.node7.rdsizedncumask=0xE8,event=0x8bdf_ccm_reqa.node0.rdsizedumask=0x07,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizeddf_ccm_reqa.node1.rdsizedumask=0x27,event=0x8bdf_ccm_reqa.node2.rdsizedumask=0x47,event=0x8bdf_ccm_reqa.node3.rdsizedumask=0x67,event=0x8bdf_ccm_reqa.node4.rdsizedumask=0x87,event=0x8bdf_ccm_reqa.node5.rdsizedumask=0xA7,event=0x8bdf_ccm_reqa.node6.rdsizedumask=0xC7,event=0x8bdf_ccm_reqa.node7.rdsizedumask=0xE7,event=0x8bdf_ccm_reqa.node0.specdramrdumask=0x06,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrddf_ccm_reqa.node1.specdramrdumask=0x26,event=0x8bdf_ccm_reqa.node2.specdramrdumask=0x46,event=0x8bdf_ccm_reqa.node3.specdramrdumask=0x66,event=0x8bdf_ccm_reqa.node4.specdramrdumask=0x86,event=0x8bdf_ccm_reqa.node5.specdramrdumask=0xA6,event=0x8bdf_ccm_reqa.node6.specdramrdumask=0xC6,event=0x8bdf_ccm_reqa.node7.specdramrdumask=0xE6,event=0x8bdf_ccm_reqa.node0.anyrdblkumask=0x05,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblkdf_ccm_reqa.node1.anyrdblkumask=0x25,event=0x8bdf_ccm_reqa.node2.anyrdblkumask=0x45,event=0x8bdf_ccm_reqa.node3.anyrdblkumask=0x65,event=0x8bdf_ccm_reqa.node4.anyrdblkumask=0x85,event=0x8bdf_ccm_reqa.node5.anyrdblkumask=0xA5,event=0x8bdf_ccm_reqa.node6.anyrdblkumask=0xC5,event=0x8bdf_ccm_reqa.node7.anyrdblkumask=0xE5,event=0x8bdf_ccm_reqa.node0.rdvlkcumask=0x04,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkcdf_ccm_reqa.node1.rdvlkcumask=0x24,event=0x8bdf_ccm_reqa.node2.rdvlkcumask=0x44,event=0x8bdf_ccm_reqa.node3.rdvlkcumask=0x64,event=0x8bdf_ccm_reqa.node4.rdvlkcumask=0x84,event=0x8bdf_ccm_reqa.node5.rdvlkcumask=0xA4,event=0x8bdf_ccm_reqa.node6.rdvlkcumask=0xC4,event=0x8bdf_ccm_reqa.node7.rdvlkcumask=0xE4,event=0x8bdf_ccm_reqa.node0.rdvlkxumask=0x03,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkxdf_ccm_reqa.node1.rdvlkxumask=0x23,event=0x8bdf_ccm_reqa.node2.rdvlkxumask=0x43,event=0x8bdf_ccm_reqa.node3.rdvlkxumask=0x63,event=0x8bdf_ccm_reqa.node4.rdvlkxumask=0x83,event=0x8bdf_ccm_reqa.node5.rdvlkxumask=0xA3,event=0x8bdf_ccm_reqa.node6.rdvlkxumask=0xC3,event=0x8bdf_ccm_reqa.node7.rdvlkxumask=0xE3,event=0x8bdf_ccm_reqa.node0.rdvlksumask=0x02,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlksdf_ccm_reqa.node1.rdvlksumask=0x22,event=0x8bdf_ccm_reqa.node2.rdvlksumask=0x42,event=0x8bdf_ccm_reqa.node3.rdvlksumask=0x62,event=0x8bdf_ccm_reqa.node4.rdvlksumask=0x82,event=0x8bdf_ccm_reqa.node5.rdvlksumask=0xA2,event=0x8bdf_ccm_reqa.node6.rdvlksumask=0xC2,event=0x8bdf_ccm_reqa.node7.rdvlksumask=0xE2,event=0x8bdf_ccm_reqa.node0.rdvlklumask=0x01,event=0x8bData Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkldf_ccm_reqa.node1.rdvlklumask=0x21,event=0x8bdf_ccm_reqa.node2.rdvlklumask=0x41,event=0x8bdf_ccm_reqa.node3.rdvlklumask=0x61,event=0x8bdf_ccm_reqa.node4.rdvlklumask=0x81,event=0x8bdf_ccm_reqa.node5.rdvlklumask=0xA1,event=0x8bdf_ccm_reqa.node6.rdvlklumask=0xC1,event=0x8bdf_ccm_reqa.node7.rdvlklumask=0xE1,event=0x8bdf_ccm_reqb.node0.chgtoxumask=0x0E,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtoxdf_ccm_reqb.node1.chgtoxumask=0x2E,event=0x8cdf_ccm_reqb.node2.chgtoxumask=0x4E,event=0x8cdf_ccm_reqb.node3.chgtoxdf_ccm_reqb.node4.chgtoxumask=0x8E,event=0x8cdf_ccm_reqb.node5.chgtoxumask=0xAE,event=0x8cdf_ccm_reqb.node6.chgtoxumask=0xCE,event=0x8cdf_ccm_reqb.node7.chgtoxumask=0xEE,event=0x8cdf_ccm_reqb.node0.vicblkfull.umask=0x0D,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfulldf_ccm_reqb.node1.vicblkfull.df_ccm_reqb.node2.vicblkfull.umask=0x4D,event=0x8cdf_ccm_reqb.node3.vicblkfull.umask=0x6D,event=0x8cdf_ccm_reqb.node4.vicblkfull.umask=0x8D,event=0x8cdf_ccm_reqb.node5.vicblkfull.umask=0xAD,event=0x8cdf_ccm_reqb.node6.vicblkfull.umask=0xCD,event=0x8cdf_ccm_reqb.node7.vicblkfull.umask=0xED,event=0x8cdf_ccm_reqb.node0.wbinvblkallumask=0x0C,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkalldf_ccm_reqb.node1.wbinvblkallumask=0x2C,event=0x8cdf_ccm_reqb.node2.wbinvblkallumask=0x4C,event=0x8cdf_ccm_reqb.node3.wbinvblkallumask=0x6C,event=0x8cdf_ccm_reqb.node4.wbinvblkallumask=0x8C,event=0x8cdf_ccm_reqb.node5.wbinvblkallumask=0xAC,event=0x8cdf_ccm_reqb.node6.wbinvblkallumask=0xCC,event=0x8cdf_ccm_reqb.node7.wbinvblkallumask=0xEC,event=0x8cdf_ccm_reqb.node0.vicblkfullzeroumask=0x0B,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzerodf_ccm_reqb.node1.vicblkfullzeroumask=0x2B,event=0x8cdf_ccm_reqb.node2.vicblkfullzeroumask=0x4B,event=0x8cdf_ccm_reqb.node3.vicblkfullzeroumask=0x6B,event=0x8cdf_ccm_reqb.node4.vicblkfullzeroumask=0x8B,event=0x8cdf_ccm_reqb.node5.vicblkfullzeroumask=0xAB,event=0x8cdf_ccm_reqb.node6.vicblkfullzeroumask=0xCB,event=0x8cdf_ccm_reqb.node7.vicblkfullzeroumask=0xEB,event=0x8cumask=0x0A,event=0x8cumask=0x2A,event=0x8cumask=0x4A,event=0x8cumask=0x6A,event=0x8cumask=0x8A,event=0x8cumask=0xAA,event=0x8cumask=0xCA,event=0x8cumask=0xEA,event=0x8cdf_ccm_reqb.node0.vicblkclnumask=0x09,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkclndf_ccm_reqb.node1.vicblkclnumask=0x29,event=0x8cdf_ccm_reqb.node2.vicblkclnumask=0x49,event=0x8cdf_ccm_reqb.node3.vicblkclnumask=0x69,event=0x8cdf_ccm_reqb.node4.vicblkclnumask=0x89,event=0x8cdf_ccm_reqb.node5.vicblkclnumask=0xA9,event=0x8cdf_ccm_reqb.node6.vicblkclnumask=0xC9,event=0x8cdf_ccm_reqb.node7.vicblkclnumask=0xE9,event=0x8cdf_ccm_reqb.node0.anyiorequest.umask=0x07,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequestdf_ccm_reqb.node1.anyiorequest.umask=0x27,event=0x8cdf_ccm_reqb.node2.anyiorequest.umask=0x47,event=0x8cdf_ccm_reqb.node3.anyiorequest.umask=0x67,event=0x8cdf_ccm_reqb.node4.anyiorequest.umask=0x87,event=0x8cdf_ccm_reqb.node5.anyiorequest.umask=0xA7,event=0x8cdf_ccm_reqb.node6.anyiorequest.umask=0xC7,event=0x8cdf_ccm_reqb.node7.anyiorequest.umask=0xE7,event=0x8cdf_ccm_reqb.node0.anywrsizedumask=0x06,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsizeddf_ccm_reqb.node1.anywrsizedumask=0x26,event=0x8cdf_ccm_reqb.node2.anywrsizedumask=0x46,event=0x8cdf_ccm_reqb.node3.anywrsizedumask=0x66,event=0x8cdf_ccm_reqb.node4.anywrsizedumask=0x86,event=0x8cdf_ccm_reqb.node5.anywrsizedumask=0xA6,event=0x8cdf_ccm_reqb.node6.anywrsizedumask=0xC6,event=0x8cdf_ccm_reqb.node7.anywrsizedumask=0xE6,event=0x8cdf_ccm_reqb.node0.wrsizedfullncumask=0x05,event=0x8cdf_ccm_reqb.node1.wrsizedfullncumask=0x25,event=0x8cdf_ccm_reqb.node2.wrsizedfullncumask=0x45,event=0x8cdf_ccm_reqb.node3.wrsizedfullncumask=0x65,event=0x8cdf_ccm_reqb.node4.wrsizedfullncumask=0x85,event=0x8cdf_ccm_reqb.node5.wrsizedfullncumask=0xA5,event=0x8cdf_ccm_reqb.node6.wrsizedfullncumask=0xC5,event=0x8cdf_ccm_reqb.node7.wrsizedfullncumask=0xE5,event=0x8cdf_ccm_reqb.node0.wrsizedncumask=0x04,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncdf_ccm_reqb.node1.wrsizedncumask=0x24,event=0x8cdf_ccm_reqb.node2.wrsizedncumask=0x44,event=0x8cdf_ccm_reqb.node3.wrsizedncumask=0x64,event=0x8cdf_ccm_reqb.node4.wrsizedncumask=0x84,event=0x8cdf_ccm_reqb.node5.wrsizedncumask=0xA4,event=0x8cdf_ccm_reqb.node6.wrsizedncumask=0xC4,event=0x8cdf_ccm_reqb.node7.wrsizedncumask=0xE4,event=0x8cdf_ccm_reqb.node0.wrsizedfullncpostedumask=0x03,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposteddf_ccm_reqb.node1.wrsizedfullncpostedumask=0x23,event=0x8cdf_ccm_reqb.node2.wrsizedfullncpostedumask=0x43,event=0x8cdf_ccm_reqb.node3.wrsizedfullncpostedumask=0x63,event=0x8cdf_ccm_reqb.node4.wrsizedfullncpostedumask=0x83,event=0x8cdf_ccm_reqb.node5.wrsizedfullncpostedumask=0xA3,event=0x8cdf_ccm_reqb.node6.wrsizedfullncpostedumask=0xC3,event=0x8cdf_ccm_reqb.node7.wrsizedfullncpostedumask=0xE3,event=0x8cdf_ccm_reqb.node0.wrsizedncpostedumask=0x02,event=0x8cData Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposteddf_ccm_reqb.node1.wrsizedncpostedumask=0x22,event=0x8cdf_ccm_reqb.node2.wrsizedncpostedumask=0x42,event=0x8cdf_ccm_reqb.node3.wrsizedncpostedumask=0x62,event=0x8cdf_ccm_reqb.node4.wrsizedncpostedumask=0x82,event=0x8cdf_ccm_reqb.node5.wrsizedncpostedumask=0xA2,event=0x8cdf_ccm_reqb.node6.wrsizedncpostedumask=0xC2,event=0x8cdf_ccm_reqb.node7.wrsizedncpostedumask=0xE2,event=0x8cdf_ccm_reqb.node0.rdsizedumask=0x01,event=0x8cdf_ccm_reqb.node1.rdsizedumask=0x21,event=0x8cdf_ccm_reqb.node2.rdsizedumask=0x41,event=0x8cdf_ccm_reqb.node3.rdsizedumask=0x61,event=0x8cdf_ccm_reqb.node4.rdsizedumask=0x81,event=0x8cdf_ccm_reqb.node5.rdsizedumask=0xA1,event=0x8cdf_ccm_reqb.node6.rdsizedumask=0xC1,event=0x8cdf_ccm_reqb.node7.rdsizedumask=0xE1,event=0x8cdf_ccm_reqc.apicaccessumask=0x01,event=0x8dData Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC accessdf_ccm_reqc.apicucodeaccessumask=0x02,event=0x8dData Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC ucode accessdf_ccm_reqc.fasttprwriteumask=0x03,event=0x8dData Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)Fast TPR writedf_ccm_reqc.anybuslockrequestumask=0x04,event=0x8dData Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access Any Bus Lock requestdf_ioms_reqa.node0.masterabortumask=0x0C,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabortdf_ioms_reqa.node1.masterabortumask=0x2C,event=0x108df_ioms_reqa.node2.masterabortumask=0x4C,event=0x108df_ioms_reqa.node3.masterabortumask=0x6C,event=0x108df_ioms_reqa.node4.masterabortumask=0x8C,event=0x108df_ioms_reqa.node5.masterabortumask=0xAC,event=0x108df_ioms_reqa.node6.masterabortumask=0xCC,event=0x108df_ioms_reqa.node7.masterabortumask=0xEC,event=0x108df_ioms_reqa.node0.ios_respumask=0x0B,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_respdf_ioms_reqa.node1.ios_respumask=0x2B,event=0x108df_ioms_reqa.node2.ios_respumask=0x4B,event=0x108df_ioms_reqa.node3.ios_respumask=0x6B,event=0x108df_ioms_reqa.node4.ios_respumask=0x8B,event=0x108df_ioms_reqa.node5.ios_respumask=0xAB,event=0x108df_ioms_reqa.node6.ios_respumask=0xCB,event=0x108df_ioms_reqa.node7.ios_respumask=0xEB,event=0x108df_ioms_reqa.node0.flushumask=0x0A,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flushdf_ioms_reqa.node1.flushumask=0x2A,event=0x108df_ioms_reqa.node2.flushumask=0x4A,event=0x108df_ioms_reqa.node3.flushumask=0x6A,event=0x108df_ioms_reqa.node4.flushumask=0x8A,event=0x108df_ioms_reqa.node5.flushumask=0xAA,event=0x108df_ioms_reqa.node6.flushumask=0xCA,event=0x108df_ioms_reqa.node7.flushumask=0xEA,event=0x108df_ioms_reqa.node0.fenceumask=0x09,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fencedf_ioms_reqa.node1.fenceumask=0x29,event=0x108df_ioms_reqa.node2.fenceumask=0x49,event=0x108df_ioms_reqa.node3.fenceumask=0x69,event=0x108df_ioms_reqa.node4.fenceumask=0x89,event=0x108df_ioms_reqa.node5.fenceumask=0xA9,event=0x108df_ioms_reqa.node6.fenceumask=0xC9,event=0x108df_ioms_reqa.node7.fenceumask=0xE9,event=0x108df_ioms_reqa.node0.anydramtransactionumask=0x08,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransactiondf_ioms_reqa.node1.anydramtransactionumask=0x28,event=0x108df_ioms_reqa.node2.anydramtransactionumask=0x48,event=0x108df_ioms_reqa.node3.anydramtransactionumask=0x68,event=0x108df_ioms_reqa.node4.anydramtransactionumask=0x88,event=0x108df_ioms_reqa.node5.anydramtransactionumask=0xA8,event=0x108df_ioms_reqa.node6.anydramtransactionumask=0xC8,event=0x108df_ioms_reqa.node7.anydramtransactionumask=0xE8,event=0x108df_ioms_reqa.node0.anyatomicumask=0x07,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomicdf_ioms_reqa.node1.anyatomicumask=0x27,event=0x108df_ioms_reqa.node2.anyatomicumask=0x47,event=0x108df_ioms_reqa.node3.anyatomicumask=0x67,event=0x108df_ioms_reqa.node4.anyatomicumask=0x87,event=0x108df_ioms_reqa.node5.anyatomicumask=0xA7,event=0x108df_ioms_reqa.node6.anyatomicumask=0xC7,event=0x108df_ioms_reqa.node7.anyatomicumask=0xE7,event=0x108df_ioms_reqa.node0.anywrsized=64bumask=0x06,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64bdf_ioms_reqa.node1.anywrsized=64bumask=0x26,event=0x108df_ioms_reqa.node2.anywrsized=64bumask=0x46,event=0x108df_ioms_reqa.node3.anywrsized=64bumask=0x66,event=0x108df_ioms_reqa.node4.anywrsized=64bumask=0x86,event=0x108df_ioms_reqa.node5.anywrsized=64bumask=0xA6,event=0x108df_ioms_reqa.node6.anywrsized=64bumask=0xC6,event=0x108df_ioms_reqa.node7.anywrsized=64bumask=0xE6,event=0x108df_ioms_reqa.node0.anywrsized>32band<64bumask=0x05,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64bdf_ioms_reqa.node1.anywrsized>32band<64bumask=0x25,event=0x108df_ioms_reqa.node2.anywrsized>32band<64bumask=0x45,event=0x108df_ioms_reqa.node3.anywrsized>32band<64bumask=0x65,event=0x108df_ioms_reqa.node4.anywrsized>32band<64bumask=0x85,event=0x108df_ioms_reqa.node5.anywrsized>32band<64bumask=0xA5,event=0x108df_ioms_reqa.node6.anywrsized>32band<64bumask=0xC5,event=0x108df_ioms_reqa.node7.anywrsized>32band<64bumask=0xE5,event=0x108df_ioms_reqa.node0.anywrsized=32bumask=0x04,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32bdf_ioms_reqa.node1.anywrsized=32bumask=0x24,event=0x108df_ioms_reqa.node2.anywrsized=32bumask=0x44,event=0x108df_ioms_reqa.node3.anywrsized=32bumask=0x64,event=0x108df_ioms_reqa.node4.anywrsized=32bumask=0x84,event=0x108df_ioms_reqa.node5.anywrsized=32bumask=0xA4,event=0x108df_ioms_reqa.node6.anywrsized=32bumask=0xC4,event=0x108df_ioms_reqa.node7.anywrsized=32bumask=0xE4,event=0x108df_ioms_reqa.node0.anywrsized<32bumask=0x03,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32bdf_ioms_reqa.node1.anywrsized<32bumask=0x23,event=0x108df_ioms_reqa.node2.anywrsized<32bumask=0x43,event=0x108df_ioms_reqa.node3.anywrsized<32bumask=0x63,event=0x108df_ioms_reqa.node4.anywrsized<32bumask=0x83,event=0x108df_ioms_reqa.node5.anywrsized<32bumask=0xA3,event=0x108df_ioms_reqa.node6.anywrsized<32bumask=0xC3,event=0x108df_ioms_reqa.node7.anywrsized<32bumask=0xE3,event=0x108df_ioms_reqa.node0.anyrdsizedumask=0x02,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsizeddf_ioms_reqa.node1.anyrdsizedumask=0x22,event=0x108df_ioms_reqa.node2.anyrdsizedumask=0x42,event=0x108df_ioms_reqa.node3.anyrdsizedumask=0x62,event=0x108df_ioms_reqa.node4.anyrdsizedumask=0x82,event=0x108df_ioms_reqa.node5.anyrdsizedumask=0xA2,event=0x108df_ioms_reqa.node6.anyrdsizedumask=0xC2,event=0x108df_ioms_reqa.node7.anyrdsizedumask=0xE2,event=0x108df_ioms_reqa.node0.largereadumask=0x01,event=0x108Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largereaddf_ioms_reqa.node1.largereadumask=0x21,event=0x108df_ioms_reqa.node2.largereadumask=0x41,event=0x108df_ioms_reqa.node3.largereadumask=0x61,event=0x108df_ioms_reqa.node4.largereadumask=0x81,event=0x108df_ioms_reqa.node5.largereadumask=0xA1,event=0x108df_ioms_reqa.node6.largereadumask=0xC1,event=0x108df_ioms_reqa.node7.largereadumask=0xE1,event=0x108df_ioms_reqb.node0.pieiorequestumask=0x0F,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transactiondf_ioms_reqb.node1.pieiorequestumask=0x2F,event=0x109df_ioms_reqb.node2.pieiorequestumask=0x4F,event=0x109df_ioms_reqb.node3.pieiorequestumask=0x6F,event=0x109df_ioms_reqb.node4.pieiorequestumask=0x8F,event=0x109df_ioms_reqb.node5.pieiorequestumask=0xAF,event=0x109df_ioms_reqb.node6.pieiorequestumask=0xCF,event=0x109df_ioms_reqb.node7.pieiorequestumask=0xEF,event=0x109df_ioms_reqb.node0.piesystemmanagementumask=0x0E,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagementdf_ioms_reqb.node1.piesystemmanagementumask=0x2E,event=0x109df_ioms_reqb.node2.piesystemmanagementumask=0x4E,event=0x109df_ioms_reqb.node3.piesystemmanagementumask=0x6E,event=0x109df_ioms_reqb.node4.piesystemmanagementumask=0x8E,event=0x109df_ioms_reqb.node5.piesystemmanagementumask=0xAE,event=0x109df_ioms_reqb.node6.piesystemmanagementumask=0xCE,event=0x109df_ioms_reqb.node7.piesystemmanagementumask=0xEE,event=0x109df_ioms_reqb.node0.pieinterruptumask=0x0D,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterruptdf_ioms_reqb.node1.pieinterruptumask=0x2D,event=0x109df_ioms_reqb.node2.pieinterruptumask=0x4D,event=0x109df_ioms_reqb.node3.pieinterruptumask=0x6D,event=0x109df_ioms_reqb.node4.pieinterruptumask=0x8D,event=0x109df_ioms_reqb.node5.pieinterruptumask=0xAD,event=0x109df_ioms_reqb.node6.pieinterruptumask=0xCD,event=0x109df_ioms_reqb.node7.pieinterruptumask=0xED,event=0x109df_ioms_reqb.node0.anyiotransactionumask=0x0C,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransactiondf_ioms_reqb.node1.anyiotransactionumask=0x2C,event=0x109df_ioms_reqb.node2.anyiotransactionumask=0x4C,event=0x109df_ioms_reqb.node3.anyiotransactionumask=0x6C,event=0x109df_ioms_reqb.node4.anyiotransactionumask=0x8C,event=0x109df_ioms_reqb.node5.anyiotransactionumask=0xAC,event=0x109df_ioms_reqb.node6.anyiotransactionumask=0xCC,event=0x109df_ioms_reqb.node7.anyiotransactionumask=0xEC,event=0x109df_ioms_reqb.node0.ioanyatomicumask=0x0B,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomicdf_ioms_reqb.node1.ioanyatomicumask=0x2B,event=0x109df_ioms_reqb.node2.ioanyatomicumask=0x4B,event=0x109df_ioms_reqb.node3.ioanyatomicumask=0x6B,event=0x109df_ioms_reqb.node4.ioanyatomicumask=0x8B,event=0x109df_ioms_reqb.node5.ioanyatomicumask=0xAB,event=0x109df_ioms_reqb.node6.ioanyatomicumask=0xCB,event=0x109df_ioms_reqb.node7.ioanyatomicumask=0xEB,event=0x109df_ioms_reqb.node0.ioanynon-postedwrsized=64bumask=0x0A,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64bdf_ioms_reqb.node1.ioanynon-postedwrsized=64bumask=0x2A,event=0x109df_ioms_reqb.node2.ioanynon-postedwrsized=64bumask=0x4A,event=0x109df_ioms_reqb.node3.ioanynon-postedwrsized=64bumask=0x6A,event=0x109df_ioms_reqb.node4.ioanynon-postedwrsized=64bumask=0x8A,event=0x109df_ioms_reqb.node5.ioanynon-postedwrsized=64bumask=0xAA,event=0x109df_ioms_reqb.node6.ioanynon-postedwrsized=64bumask=0xCA,event=0x109df_ioms_reqb.node7.ioanynon-postedwrsized=64bumask=0xEA,event=0x109df_ioms_reqb.node0.ioanynon-postedwrsized>32band<64bumask=0x09,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64bdf_ioms_reqb.node1.ioanynon-postedwrsized>32band<64bumask=0x29,event=0x109df_ioms_reqb.node2.ioanynon-postedwrsized>32band<64bumask=0x49,event=0x109df_ioms_reqb.node3.ioanynon-postedwrsized>32band<64bumask=0x69,event=0x109df_ioms_reqb.node4.ioanynon-postedwrsized>32band<64bumask=0x89,event=0x109df_ioms_reqb.node5.ioanynon-postedwrsized>32band<64bumask=0xA9,event=0x109df_ioms_reqb.node6.ioanynon-postedwrsized>32band<64bumask=0xC9,event=0x109df_ioms_reqb.node7.ioanynon-postedwrsized>32band<64bumask=0xE9,event=0x109df_ioms_reqb.node0.ioanynon-postedwrsized=32bumask=0x08,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32bdf_ioms_reqb.node1.ioanynon-postedwrsized=32bumask=0x28,event=0x109df_ioms_reqb.node2.ioanynon-postedwrsized=32bumask=0x48,event=0x109df_ioms_reqb.node3.ioanynon-postedwrsized=32bumask=0x68,event=0x109df_ioms_reqb.node4.ioanynon-postedwrsized=32bumask=0x88,event=0x109df_ioms_reqb.node5.ioanynon-postedwrsized=32bumask=0xA8,event=0x109df_ioms_reqb.node6.ioanynon-postedwrsized=32bumask=0xC8,event=0x109df_ioms_reqb.node7.ioanynon-postedwrsized=32bumask=0xE8,event=0x109df_ioms_reqb.node0.ioanynon-postedwrsized<32bumask=0x07,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32bdf_ioms_reqb.node1.ioanynon-postedwrsized<32bumask=0x27,event=0x109df_ioms_reqb.node2.ioanynon-postedwrsized<32bumask=0x47,event=0x109df_ioms_reqb.node3.ioanynon-postedwrsized<32bumask=0x67,event=0x109df_ioms_reqb.node4.ioanynon-postedwrsized<32bumask=0x87,event=0x109df_ioms_reqb.node5.ioanynon-postedwrsized<32bumask=0xA7,event=0x109df_ioms_reqb.node6.ioanynon-postedwrsized<32bumask=0xC7,event=0x109df_ioms_reqb.node7.ioanynon-postedwrsized<32bumask=0xE7,event=0x109df_ioms_reqb.node0.ioanypostedwrsized=64bumask=0x06,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64bdf_ioms_reqb.node1.ioanypostedwrsized=64bumask=0x26,event=0x109df_ioms_reqb.node2.ioanypostedwrsized=64bumask=0x46,event=0x109df_ioms_reqb.node3.ioanypostedwrsized=64bumask=0x66,event=0x109df_ioms_reqb.node4.ioanypostedwrsized=64bumask=0x86,event=0x109df_ioms_reqb.node5.ioanypostedwrsized=64bumask=0xA6,event=0x109df_ioms_reqb.node6.ioanypostedwrsized=64bumask=0xC6,event=0x109df_ioms_reqb.node7.ioanypostedwrsized=64bumask=0xE6,event=0x109df_ioms_reqb.node0.ioanypostedwrsized>32band<64bumask=0x05,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64bdf_ioms_reqb.node1.ioanypostedwrsized>32band<64bumask=0x25,event=0x109df_ioms_reqb.node2.ioanypostedwrsized>32band<64bumask=0x45,event=0x109df_ioms_reqb.node3.ioanypostedwrsized>32band<64bumask=0x65,event=0x109df_ioms_reqb.node4.ioanypostedwrsized>32band<64bumask=0x85,event=0x109df_ioms_reqb.node5.ioanypostedwrsized>32band<64bumask=0xA5,event=0x109df_ioms_reqb.node6.ioanypostedwrsized>32band<64bumask=0xC5,event=0x109df_ioms_reqb.node7.ioanypostedwrsized>32band<64bumask=0xE5,event=0x109df_ioms_reqb.node0.ioanypostedwrsized=32umask=0x04,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32df_ioms_reqb.node1.ioanypostedwrsized=32umask=0x24,event=0x109df_ioms_reqb.node2.ioanypostedwrsized=32umask=0x44,event=0x109df_ioms_reqb.node3.ioanypostedwrsized=32umask=0x64,event=0x109df_ioms_reqb.node4.ioanypostedwrsized=32umask=0x84,event=0x109df_ioms_reqb.node5.ioanypostedwrsized=32umask=0xA4,event=0x109df_ioms_reqb.node6.ioanypostedwrsized=32umask=0xC4,event=0x109df_ioms_reqb.node7.ioanypostedwrsized=32umask=0xE4,event=0x109df_ioms_reqb.node0.ioanypostedwrsized<32umask=0x03,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32df_ioms_reqb.node1.ioanypostedwrsized<32umask=0x23,event=0x109df_ioms_reqb.node2.ioanypostedwrsized<32umask=0x43,event=0x109df_ioms_reqb.node3.ioanypostedwrsized<32umask=0x63,event=0x109df_ioms_reqb.node4.ioanypostedwrsized<32umask=0x83,event=0x109df_ioms_reqb.node5.ioanypostedwrsized<32umask=0xA3,event=0x109df_ioms_reqb.node6.ioanypostedwrsized<32umask=0xC3,event=0x109df_ioms_reqb.node7.ioanypostedwrsized<32umask=0xE3,event=0x109df_ioms_reqb.node0.ioanyrdsizedumask=0x02,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsizeddf_ioms_reqb.node1.ioanyrdsizedumask=0x22,event=0x109df_ioms_reqb.node2.ioanyrdsizedumask=0x42,event=0x109df_ioms_reqb.node3.ioanyrdsizedumask=0x62,event=0x109df_ioms_reqb.node4.ioanyrdsizedumask=0x82,event=0x109df_ioms_reqb.node5.ioanyrdsizedumask=0xA2,event=0x109df_ioms_reqb.node6.ioanyrdsizedumask=0xC2,event=0x109df_ioms_reqb.node7.ioanyrdsizedumask=0xE2,event=0x109df_ioms_reqb.node0.iolargereadumask=0x01,event=0x109Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargereaddf_ioms_reqb.node1.iolargereadumask=0x21,event=0x109df_ioms_reqb.node2.iolargereadumask=0x41,event=0x109df_ioms_reqb.node3.iolargereadumask=0x61,event=0x109df_ioms_reqb.node4.iolargereadumask=0x81,event=0x109df_ioms_reqb.node5.iolargereadumask=0xA1,event=0x109df_ioms_reqb.node6.iolargereadumask=0xC1,event=0x109df_ioms_reqb.node7.iolargereadumask=0xE1,event=0x109fpu_pipe_assignment.dualumask=0xf0,event=0Total number multi-pipe uOps assigned to all pipesThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipesfpu_pipe_assignment.dual3umask=0x80,event=0Total number multi-pipe uOps assigned to pipe 3The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3fpu_pipe_assignment.dual2umask=0x40,event=0Total number multi-pipe uOps assigned to pipe 2The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2fpu_pipe_assignment.dual1umask=0x20,event=0Total number multi-pipe uOps assigned to pipe 1The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1fpu_pipe_assignment.dual0umask=0x10,event=0Total number multi-pipe uOps assigned to pipe 0The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0fpu_pipe_assignment.totalumask=0xf,event=0Total number uOps assigned to all fpu pipesThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipesfpu_pipe_assignment.total3umask=0x8,event=0Total number of fp uOps on pipe 3The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3fpu_pipe_assignment.total2Total number of fp uOps on pipe 2The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2fpu_pipe_assignment.total1Total number of fp uOps on pipe 1The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1fpu_pipe_assignment.total0umask=0x1,event=0Total number of fp uOps  on pipe 0The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0fp_sched_emptyThis is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the schedulerfp_retx87_fp_ops.allumask=0x7,event=0x2All OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8fp_retx87_fp_ops.div_sqr_r_opsDivide and square root OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Opsfp_retx87_fp_ops.mul_opsumask=0x2,event=0x2Multiply OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Opsfp_retx87_fp_ops.add_sub_opsAdd/subtract OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Opsfp_ret_sse_avx_ops.allumask=0xff,event=0x3All FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.dp_mult_add_flopsumask=0x80,event=0x3Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSfp_ret_sse_avx_ops.dp_div_flopsumask=0x40,event=0x3Double precision divide/square root FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPSfp_ret_sse_avx_ops.dp_mult_flopsumask=0x20,event=0x3Double precision multiply FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPSfp_ret_sse_avx_ops.dp_add_sub_flopsumask=0x10,event=0x3Double precision add/subtract FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPSfp_ret_sse_avx_ops.sp_mult_add_flopsumask=0x8,event=0x3Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSfp_ret_sse_avx_ops.sp_div_flopsumask=0x4,event=0x3Single-precision divide/square root FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPSfp_ret_sse_avx_ops.sp_mult_flopsumask=0x2,event=0x3Single-precision multiply FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPSfp_ret_sse_avx_ops.sp_add_sub_flopsumask=0x1,event=0x3Single-precision add/subtract FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPSfp_num_mov_elim_scal_op.optimizedumask=0x8,event=0x4Number of Scalar Ops optimizedThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimizedfp_num_mov_elim_scal_op.opt_potentialNumber of Ops that are candidates for optimization (have Z-bit either set or pass)This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass)fp_num_mov_elim_scal_op.sse_mov_ops_elimNumber of SSE Move Ops eliminatedThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminatedfp_num_mov_elim_scal_op.sse_mov_opsNumber of SSE Move OpsThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Opsfp_retired_ser_ops.x87_ctrl_retumask=0x8,event=0x5x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsThe number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsfp_retired_ser_ops.x87_bot_retumask=0x4,event=0x5x87 bottom-executing uOps retiredThe number of serializing Ops retired. x87 bottom-executing uOps retiredfp_retired_ser_ops.sse_ctrl_retumask=0x2,event=0x5SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsThe number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsfp_retired_ser_ops.sse_bot_retumask=0x1,event=0x5SSE bottom-executing uOps retiredThe number of serializing Ops retired. SSE bottom-executing uOps retiredl3_request_g1.t0.s0.wrsizedncl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x1L3 Cache Performance Monitor Counters L3 Cache Accesses l3cachel3_request_g1.t1.s0.wrsizedncl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x1L3 Cache Performance Monitor Counters L3 Cache Accessesl3_request_g1.t2.s0.wrsizedncl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t3.s0.wrsizedncl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t4.s0.wrsizedncl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t5.s0.wrsizedncl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t6.s0.wrsizedncl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t7.s0.wrsizedncl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x1l3_request_g1.t0.s1.wrsizedncl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t1.s1.wrsizedncl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t2.s1.wrsizedncl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t3.s1.wrsizedncl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t4.s1.wrsizedncl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t5.s1.wrsizedncl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t6.s1.wrsizedncl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t7.s1.wrsizedncl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x1l3_request_g1.t0.s2.wrsizedncl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t1.s2.wrsizedncl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t2.s2.wrsizedncl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t3.s2.wrsizedncl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t4.s2.wrsizedncl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t5.s2.wrsizedncl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t6.s2.wrsizedncl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t7.s2.wrsizedncl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x1l3_request_g1.t0.s3.wrsizedncl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t1.s3.wrsizedncl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t2.s3.wrsizedncl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t3.s3.wrsizedncl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t4.s3.wrsizedncl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t5.s3.wrsizedncl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t6.s3.wrsizedncl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t7.s3.wrsizedncl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x1l3_request_g1.t0.s0.wrsizedl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t1.s0.wrsizedl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t2.s0.wrsizedl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t3.s0.wrsizedl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t4.s0.wrsizedl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t5.s0.wrsizedl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t6.s0.wrsizedl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t7.s0.wrsizedl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x1l3_request_g1.t0.s1.wrsizedl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t1.s1.wrsizedl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t2.s1.wrsizedl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t3.s1.wrsizedl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t4.s1.wrsizedl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t5.s1.wrsizedl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t6.s1.wrsizedl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t7.s1.wrsizedl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x1l3_request_g1.t0.s2.wrsizedl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t1.s2.wrsizedl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t2.s2.wrsizedl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t3.s2.wrsizedl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t4.s2.wrsizedl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t5.s2.wrsizedl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t6.s2.wrsizedl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t7.s2.wrsizedl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x1l3_request_g1.t0.s3.wrsizedl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t1.s3.wrsizedl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t2.s3.wrsizedl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t3.s3.wrsizedl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t4.s3.wrsizedl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t5.s3.wrsizedl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t6.s3.wrsizedl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t7.s3.wrsizedl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x1l3_request_g1.t0.s0.rdsizedncl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t1.s0.rdsizedncl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t2.s0.rdsizedncl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t3.s0.rdsizedncl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t4.s0.rdsizedncl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t5.s0.rdsizedncl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t6.s0.rdsizedncl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t7.s0.rdsizedncl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x1l3_request_g1.t0.s1.rdsizedncl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t1.s1.rdsizedncl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t2.s1.rdsizedncl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t3.s1.rdsizedncl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t4.s1.rdsizedncl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t5.s1.rdsizedncl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t6.s1.rdsizedncl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t7.s1.rdsizedncl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x1l3_request_g1.t0.s2.rdsizedncl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t1.s2.rdsizedncl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t2.s2.rdsizedncl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t3.s2.rdsizedncl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t4.s2.rdsizedncl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t5.s2.rdsizedncl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t6.s2.rdsizedncl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t7.s2.rdsizedncl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x1l3_request_g1.t0.s3.rdsizedncl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t1.s3.rdsizedncl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t2.s3.rdsizedncl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t3.s3.rdsizedncl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t4.s3.rdsizedncl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t5.s3.rdsizedncl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t6.s3.rdsizedncl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t7.s3.rdsizedncl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x1l3_request_g1.t0.s0.rdsizedl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t1.s0.rdsizedl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t2.s0.rdsizedl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t3.s0.rdsizedl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t4.s0.rdsizedl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t5.s0.rdsizedl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t6.s0.rdsizedl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t7.s0.rdsizedl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x1l3_request_g1.t0.s1.rdsizedl3_request_g1.t1.s1.rdsizedl3_request_g1.t2.s1.rdsizedl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t3.s1.rdsizedl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t4.s1.rdsizedl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t5.s1.rdsizedl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t6.s1.rdsizedl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t7.s1.rdsizedl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x1l3_request_g1.t0.s2.rdsizedl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t1.s2.rdsizedl3_request_g1.t2.s2.rdsizedl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t3.s2.rdsizedl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t4.s2.rdsizedl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t5.s2.rdsizedl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t6.s2.rdsizedl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t7.s2.rdsizedl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x1l3_request_g1.t0.s3.rdsizedl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t1.s3.rdsizedl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t2.s3.rdsizedl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t3.s3.rdsizedl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t4.s3.rdsizedl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t5.s3.rdsizedl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t6.s3.rdsizedl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t7.s3.rdsizedl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x1l3_request_g1.t0.s0.cachingl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t1.s0.cachingl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t2.s0.cachingl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t3.s0.cachingl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t4.s0.cachingl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t5.s0.cachingl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t6.s0.cachingl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t7.s0.cachingl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x1l3_request_g1.t0.s1.cachingl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t1.s1.cachingl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t2.s1.cachingl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t3.s1.cachingl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t4.s1.cachingl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t5.s1.cachingl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t6.s1.cachingl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t7.s1.cachingl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x1l3_request_g1.t0.s2.cachingl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t1.s2.cachingl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t2.s2.cachingl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t3.s2.cachingl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t4.s2.cachingl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t5.s2.cachingl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t6.s2.cachingl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t7.s2.cachingl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x1l3_request_g1.t0.s3.cachingl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t1.s3.cachingl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t2.s3.cachingl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t3.s3.cachingl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t4.s3.cachingl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t5.s3.cachingl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t6.s3.cachingl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x1l3_request_g1.t7.s3.cachingl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x1l3fillvicreq.t0.s0.vicblkl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x3L3 Cache Performance Monitor Counters L3 cache access typesl3fillvicreq.t1.s0.vicblkl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t2.s0.vicblkl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t3.s0.vicblkl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t4.s0.vicblkl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t5.s0.vicblkl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t6.s0.vicblkl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t7.s0.vicblkl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x3l3fillvicreq.t0.s1.vicblkl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t1.s1.vicblkl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t2.s1.vicblkl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t3.s1.vicblkl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t4.s1.vicblkl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t5.s1.vicblkl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t6.s1.vicblkl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t7.s1.vicblkl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x3l3fillvicreq.t0.s2.vicblkl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t1.s2.vicblkl3fillvicreq.t2.s2.vicblkl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t3.s2.vicblkl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t4.s2.vicblkl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t5.s2.vicblkl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t6.s2.vicblkl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t7.s2.vicblkl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x3l3fillvicreq.t0.s3.vicblkl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t1.s3.vicblkl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t2.s3.vicblkl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t3.s3.vicblkl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t4.s3.vicblkl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t5.s3.vicblkl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t6.s3.vicblkl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t7.s3.vicblkl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x3l3fillvicreq.t0.s0.chgtoxl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t1.s0.chgtoxl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t2.s0.chgtoxl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t3.s0.chgtoxl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t4.s0.chgtoxl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t5.s0.chgtoxl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t6.s0.chgtoxl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t7.s0.chgtoxl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x3l3fillvicreq.t0.s1.chgtoxl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t1.s1.chgtoxl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t2.s1.chgtoxl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t3.s1.chgtoxl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t4.s1.chgtoxl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t5.s1.chgtoxl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t6.s1.chgtoxl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t7.s1.chgtoxl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x3l3fillvicreq.t0.s2.chgtoxl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t1.s2.chgtoxl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t2.s2.chgtoxl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t3.s2.chgtoxl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t4.s2.chgtoxl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t5.s2.chgtoxl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t6.s2.chgtoxl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t7.s2.chgtoxl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x3l3fillvicreq.t0.s3.chgtoxl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t1.s3.chgtoxl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t2.s3.chgtoxl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t3.s3.chgtoxl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t4.s3.chgtoxl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t5.s3.chgtoxl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t6.s3.chgtoxl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t7.s3.chgtoxl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x3l3fillvicreq.t0.s0.rdblkc_s_vicl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t1.s0.rdblkc_s_vicl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t2.s0.rdblkc_s_vicl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t3.s0.rdblkc_s_vicl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t4.s0.rdblkc_s_vicl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t5.s0.rdblkc_s_vicl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t6.s0.rdblkc_s_vicl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t7.s0.rdblkc_s_vicl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x3l3fillvicreq.t0.s1.rdblkc_s_vicl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t1.s1.rdblkc_s_vicl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t2.s1.rdblkc_s_vicl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t3.s1.rdblkc_s_vicl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t4.s1.rdblkc_s_vicl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t5.s1.rdblkc_s_vicl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t6.s1.rdblkc_s_vicl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t7.s1.rdblkc_s_vicl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x3l3fillvicreq.t0.s2.rdblkc_s_vicl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t1.s2.rdblkc_s_vicl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t2.s2.rdblkc_s_vicl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t3.s2.rdblkc_s_vicl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t4.s2.rdblkc_s_vicl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t5.s2.rdblkc_s_vicl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t6.s2.rdblkc_s_vicl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t7.s2.rdblkc_s_vicl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x3l3fillvicreq.t0.s3.rdblkc_s_vicl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t1.s3.rdblkc_s_vicl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t2.s3.rdblkc_s_vicl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t3.s3.rdblkc_s_vicl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t4.s3.rdblkc_s_vicl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t5.s3.rdblkc_s_vicl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t6.s3.rdblkc_s_vicl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t7.s3.rdblkc_s_vicl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x3l3fillvicreq.t0.s0.rdblkc_sl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t1.s0.rdblkc_sl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t2.s0.rdblkc_sl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t3.s0.rdblkc_sl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t4.s0.rdblkc_sl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t5.s0.rdblkc_sl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t6.s0.rdblkc_sl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t7.s0.rdblkc_sl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x3l3fillvicreq.t0.s1.rdblkc_sl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t1.s1.rdblkc_sl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t2.s1.rdblkc_sl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t3.s1.rdblkc_sl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t4.s1.rdblkc_sl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t5.s1.rdblkc_sl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t6.s1.rdblkc_sl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t7.s1.rdblkc_sl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x3l3fillvicreq.t0.s2.rdblkc_sl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t1.s2.rdblkc_sl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t2.s2.rdblkc_sl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t3.s2.rdblkc_sl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t4.s2.rdblkc_sl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t5.s2.rdblkc_sl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t6.s2.rdblkc_sl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t7.s2.rdblkc_sl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x3l3fillvicreq.t0.s3.rdblkc_sl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t1.s3.rdblkc_sl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t2.s3.rdblkc_sl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t3.s3.rdblkc_sl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t4.s3.rdblkc_sl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t5.s3.rdblkc_sl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t6.s3.rdblkc_sl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t7.s3.rdblkc_sl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x3l3fillvicreq.t0.s0.rdblkx_vicl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t1.s0.rdblkx_vicl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t2.s0.rdblkx_vicl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t3.s0.rdblkx_vicl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t4.s0.rdblkx_vicl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t5.s0.rdblkx_vicl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t6.s0.rdblkx_vicl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t7.s0.rdblkx_vicl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x3l3fillvicreq.t0.s1.rdblkx_vicl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t1.s1.rdblkx_vicl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t2.s1.rdblkx_vicl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t3.s1.rdblkx_vicl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t4.s1.rdblkx_vicl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t5.s1.rdblkx_vicl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t6.s1.rdblkx_vicl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t7.s1.rdblkx_vicl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x3l3fillvicreq.t0.s2.rdblkx_vicl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t1.s2.rdblkx_vicl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t2.s2.rdblkx_vicl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t3.s2.rdblkx_vicl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t4.s2.rdblkx_vicl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t5.s2.rdblkx_vicl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t6.s2.rdblkx_vicl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t7.s2.rdblkx_vicl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x3l3fillvicreq.t0.s3.rdblkx_vicl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t1.s3.rdblkx_vicl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t2.s3.rdblkx_vicl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t3.s3.rdblkx_vicl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t4.s3.rdblkx_vicl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t5.s3.rdblkx_vicl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t6.s3.rdblkx_vicl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t7.s3.rdblkx_vicl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x10,event=0x3l3fillvicreq.t0.s0.rdblkxl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t1.s0.rdblkxl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t2.s0.rdblkxl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t3.s0.rdblkxl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t4.s0.rdblkxl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t5.s0.rdblkxl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t6.s0.rdblkxl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t7.s0.rdblkxl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x3l3fillvicreq.t0.s1.rdblkxl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t1.s1.rdblkxl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t2.s1.rdblkxl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t3.s1.rdblkxl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t4.s1.rdblkxl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t5.s1.rdblkxl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t6.s1.rdblkxl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t7.s1.rdblkxl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x3l3fillvicreq.t0.s2.rdblkxl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t1.s2.rdblkxl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t2.s2.rdblkxl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t3.s2.rdblkxl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t4.s2.rdblkxl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t5.s2.rdblkxl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t6.s2.rdblkxl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t7.s2.rdblkxl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x3l3fillvicreq.t0.s3.rdblkxl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t1.s3.rdblkxl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t2.s3.rdblkxl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t3.s3.rdblkxl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t4.s3.rdblkxl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t5.s3.rdblkxl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t6.s3.rdblkxl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t7.s3.rdblkxl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x3l3fillvicreq.t0.s0.rdblkl_vicl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t1.s0.rdblkl_vicl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t2.s0.rdblkl_vicl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t3.s0.rdblkl_vicl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t4.s0.rdblkl_vicl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t5.s0.rdblkl_vicl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t6.s0.rdblkl_vicl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t7.s0.rdblkl_vicl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x3l3fillvicreq.t0.s1.rdblkl_vicl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t1.s1.rdblkl_vicl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t2.s1.rdblkl_vicl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t3.s1.rdblkl_vicl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t4.s1.rdblkl_vicl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t5.s1.rdblkl_vicl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t6.s1.rdblkl_vicl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t7.s1.rdblkl_vicl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x3l3fillvicreq.t0.s2.rdblkl_vicl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t1.s2.rdblkl_vicl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t2.s2.rdblkl_vicl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t3.s2.rdblkl_vicl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t4.s2.rdblkl_vicl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t5.s2.rdblkl_vicl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t6.s2.rdblkl_vicl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t7.s2.rdblkl_vicl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x3l3fillvicreq.t0.s3.rdblkl_vicl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t1.s3.rdblkl_vicl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t2.s3.rdblkl_vicl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t3.s3.rdblkl_vicl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t4.s3.rdblkl_vicl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t5.s3.rdblkl_vicl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t6.s3.rdblkl_vicl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t7.s3.rdblkl_vicl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x3l3fillvicreq.t0.s0.rdblkll3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t1.s0.rdblkll3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t2.s0.rdblkll3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t3.s0.rdblkll3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t4.s0.rdblkll3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t5.s0.rdblkll3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t6.s0.rdblkll3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t7.s0.rdblkll3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x3l3fillvicreq.t0.s1.rdblkll3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t1.s1.rdblkll3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t2.s1.rdblkll3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t3.s1.rdblkll3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t4.s1.rdblkll3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t5.s1.rdblkll3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t6.s1.rdblkll3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t7.s1.rdblkll3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x3l3fillvicreq.t0.s2.rdblkll3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t1.s2.rdblkll3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t2.s2.rdblkll3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t3.s2.rdblkll3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t4.s2.rdblkll3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t5.s2.rdblkll3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t6.s2.rdblkll3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t7.s2.rdblkll3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x3l3fillvicreq.t0.s3.rdblkll3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t1.s3.rdblkll3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t2.s3.rdblkll3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t3.s3.rdblkll3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t4.s3.rdblkll3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t5.s3.rdblkll3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t6.s3.rdblkll3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x3l3fillvicreq.t7.s3.rdblkll3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x3l3combclstrstateL3 Cache Performance Monitor Counters RequestMiss: L3 missl3victimstate.t0.s0.nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x9L3 Cache Performance Monitor Counters L3 Victim Statel3victimstate.t1.s0.nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t2.s0.nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t3.s0.nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t4.s0.nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t5.s0.nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t6.s0.nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t7.s0.nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x9l3victimstate.t0.s1.nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t1.s1.nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t2.s1.nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t3.s1.nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t4.s1.nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t5.s1.nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t6.s1.nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t7.s1.nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x9l3victimstate.t0.s2.nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t1.s2.nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t2.s2.nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t3.s2.nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t4.s2.nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t5.s2.nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t6.s2.nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t7.s2.nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x9l3victimstate.t0.s3.nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t1.s3.nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t2.s3.nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t3.s3.nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t4.s3.nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t5.s3.nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t6.s3.nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t7.s3.nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x9l3victimstate.t0.s0.none_nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t1.s0.none_nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t2.s0.none_nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t3.s0.none_nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t4.s0.none_nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t5.s0.none_nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t6.s0.none_nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t7.s0.none_nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x9l3victimstate.t0.s1.none_nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t1.s1.none_nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t2.s1.none_nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t3.s1.none_nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t4.s1.none_nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t5.s1.none_nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t6.s1.none_nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t7.s1.none_nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x9l3victimstate.t0.s2.none_nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t1.s2.none_nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t2.s2.none_nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t3.s2.none_nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t4.s2.none_nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t5.s2.none_nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t6.s2.none_nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t7.s2.none_nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x9l3victimstate.t0.s3.none_nol3victimlinel3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t1.s3.none_nol3victimlinel3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t2.s3.none_nol3victimlinel3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t3.s3.none_nol3victimlinel3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t4.s3.none_nol3victimlinel3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t5.s3.none_nol3victimlinel3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t6.s3.none_nol3victimlinel3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t7.s3.none_nol3victimlinel3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x9l3victimstate.t0.s0.f_sl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t1.s0.f_sl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t2.s0.f_sl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t3.s0.f_sl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t4.s0.f_sl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t5.s0.f_sl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t6.s0.f_sl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t7.s0.f_sl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x9l3victimstate.t0.s1.f_sl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t1.s1.f_sl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t2.s1.f_sl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t3.s1.f_sl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t4.s1.f_sl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t5.s1.f_sl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t6.s1.f_sl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t7.s1.f_sl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x9l3victimstate.t0.s2.f_sl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t1.s2.f_sl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t2.s2.f_sl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t3.s2.f_sl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t4.s2.f_sl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t5.s2.f_sl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t6.s2.f_sl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t7.s2.f_sl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x9l3victimstate.t0.s3.f_sl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t1.s3.f_sl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t2.s3.f_sl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t3.s3.f_sl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t4.s3.f_sl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t5.s3.f_sl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t6.s3.f_sl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t7.s3.f_sl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x9l3victimstate.t0.s0.ol3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t1.s0.ol3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t2.s0.ol3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t3.s0.ol3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t4.s0.ol3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t5.s0.ol3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t6.s0.ol3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t7.s0.ol3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x9l3victimstate.t0.s1.ol3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t1.s1.ol3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t2.s1.ol3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t3.s1.ol3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t4.s1.ol3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t5.s1.ol3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t6.s1.ol3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t7.s1.ol3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x9l3victimstate.t0.s2.ol3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t1.s2.ol3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t2.s2.ol3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t3.s2.ol3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t4.s2.ol3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t5.s2.ol3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t6.s2.ol3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t7.s2.ol3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x9l3victimstate.t0.s3.ol3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t1.s3.ol3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t2.s3.ol3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t3.s3.ol3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t4.s3.ol3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t5.s3.ol3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t6.s3.ol3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t7.s3.ol3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x9l3victimstate.t0.s0.e_fel3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t1.s0.e_fel3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t2.s0.e_fel3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t3.s0.e_fel3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t4.s0.e_fel3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t5.s0.e_fel3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t6.s0.e_fel3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t7.s0.e_fel3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x9l3victimstate.t0.s1.e_fel3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t1.s1.e_fel3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t2.s1.e_fel3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t3.s1.e_fel3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t4.s1.e_fel3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t5.s1.e_fel3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t6.s1.e_fel3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t7.s1.e_fel3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x9l3victimstate.t0.s2.e_fel3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t1.s2.e_fel3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t2.s2.e_fel3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t3.s2.e_fel3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t4.s2.e_fel3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t5.s2.e_fel3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t6.s2.e_fel3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t7.s2.e_fel3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x9l3victimstate.t0.s3.e_fel3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t1.s3.e_fel3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t2.s3.e_fel3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t3.s3.e_fel3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t4.s3.e_fel3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t5.s3.e_fel3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t6.s3.e_fel3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x9l3victimstate.t7.s3.e_fel3_thread_mask=0x80,l3_slice_mask=0x08,event=0x9l3victimstate.t0.s0.ml3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t1.s0.ml3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t2.s0.ml3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t3.s0.ml3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t4.s0.ml3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t5.s0.ml3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t6.s0.ml3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t7.s0.ml3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x9l3victimstate.t0.s1.ml3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t1.s1.ml3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t2.s1.ml3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t3.s1.ml3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t4.s1.ml3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t5.s1.ml3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t6.s1.ml3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t7.s1.ml3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x9l3victimstate.t0.s2.ml3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t1.s2.ml3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t2.s2.ml3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t3.s2.ml3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t4.s2.ml3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t5.s2.ml3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t6.s2.ml3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t7.s2.ml3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x9l3victimstate.t0.s3.ml3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t1.s3.ml3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t2.s3.ml3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t3.s3.ml3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t4.s3.ml3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t5.s3.ml3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t6.s3.ml3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t7.s3.ml3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x9l3victimstate.t0.s0.dl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t1.s0.dl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t2.s0.dl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t3.s0.dl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t4.s0.dl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t5.s0.dl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t6.s0.dl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t7.s0.dl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x9l3victimstate.t0.s1.dl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t1.s1.dl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t2.s1.dl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t3.s1.dl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t4.s1.dl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t5.s1.dl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t6.s1.dl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t7.s1.dl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x9l3victimstate.t0.s2.dl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t1.s2.dl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t2.s2.dl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t3.s2.dl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t4.s2.dl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t5.s2.dl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t6.s2.dl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t7.s2.dl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x9l3victimstate.t0.s3.dl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t1.s3.dl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t2.s3.dl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t3.s3.dl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t4.s3.dl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t5.s3.dl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t6.s3.dl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t7.s3.dl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x9l3victimstate.t0.s0.odl3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t1.s0.odl3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t2.s0.odl3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t3.s0.odl3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t4.s0.odl3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t5.s0.odl3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t6.s0.odl3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t7.s0.odl3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x9l3victimstate.t0.s1.odl3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t1.s1.odl3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t2.s1.odl3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t3.s1.odl3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t4.s1.odl3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t5.s1.odl3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t6.s1.odl3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t7.s1.odl3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x9l3victimstate.t0.s2.odl3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t1.s2.odl3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t2.s2.odl3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t3.s2.odl3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t4.s2.odl3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t5.s2.odl3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t6.s2.odl3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t7.s2.odl3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x9l3victimstate.t0.s3.odl3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t1.s3.odl3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t2.s3.odl3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t3.s3.odl3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t4.s3.odl3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t5.s3.odl3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t6.s3.odl3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x9l3victimstate.t7.s3.odl3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x9ls_locks.bus_lockumask=0x1,event=0x25Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory typels_dispatch.ld_st_dispatchumask=0x4,event=0x29Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Storesls_dispatch.store_dispatchumask=0x2,event=0x29Counts the number of stores dispatched to the LS unit. Unit Masks ADDedls_dispatch.ld_dispatchumask=0x1,event=0x29Counts the number of loads dispatched to the LS unit. Unit Masks ADDedls_stlfevent=0x35Number of STLF hitsls_dc_accessesevent=0x40The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative eventls_mab_alloc.dc_prefetcherumask=0x8,event=0x41LS MAB allocates by type - DC prefetcherls_mab_alloc.storesumask=0x2,event=0x41LS MAB allocates by type - storesls_mab_alloc.loadsumask=0x01,event=0x41LS MAB allocates by type - loadsls_l1_d_tlb_miss.allumask=0xff,event=0x45L1 DTLB Miss or Reload off all sizesls_l1_d_tlb_miss.tlb_reload_1g_l2_missumask=0x80,event=0x45L1 DTLB Miss of a page of 1G sizels_l1_d_tlb_miss.tlb_reload_2m_l2_missumask=0x40,event=0x45L1 DTLB Miss of a page of 2M sizels_l1_d_tlb_miss.tlb_reload_32k_l2_missumask=0x20,event=0x45L1 DTLB Miss of a page of 32K sizels_l1_d_tlb_miss.tlb_reload_4k_l2_missumask=0x10,event=0x45L1 DTLB Miss of a page of 4K sizels_l1_d_tlb_miss.tlb_reload_1g_l2_hitumask=0x8,event=0x45L1 DTLB Reload of a page of 1G sizels_l1_d_tlb_miss.tlb_reload_2m_l2_hitumask=0x4,event=0x45L1 DTLB Reload of a page of 2M sizels_l1_d_tlb_miss.tlb_reload_32k_l2_hitumask=0x2,event=0x45L1 DTLB Reload of a page of 32K sizels_l1_d_tlb_miss.tlb_reload_4k_l2_hitumask=0x1,event=0x45L1 DTLB Reload of a page of 4K sizels_tablewalker.isideumask=0xc,event=0x46Total Page Table Walks on I-sidels_tablewalker.ic_type1umask=0x8,event=0x46Total Page Table Walks IC Type 1ls_tablewalker.ic_type0umask=0x4,event=0x46Total Page Table Walks IC Type 0ls_tablewalker.dsideumask=0x3,event=0x46Total Page Table Walks on D-sidels_tablewalker.dc_type1umask=0x2,event=0x46Total Page Table Walks DC Type 1ls_tablewalker.dc_type0umask=0x1,event=0x46Total Page Table Walks DC Type 0ls_misal_accessesevent=0x47Misaligned loadsls_pref_instr_disp.prefetch_ntaumask=0x4,event=0x4bSoftware Prefetch Instructions (PREFETCHNTA instruction) Dispatchedls_pref_instr_disp.store_prefetch_wumask=0x2,event=0x4bSoftware Prefetch Instructions (3DNow PREFETCHW instruction) Dispatchedls_pref_instr_disp.load_prefetch_wumask=0x1,event=0x4bSoftware Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2ls_inef_sw_pref.mab_mch_cntumask=0x2,event=0x52The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request bufferls_inef_sw_pref.data_pipe_sw_pf_dc_hitumask=0x1,event=0x52The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hitls_not_halted_cycevent=0x76Cycles not in Haltic_oc_mode_switch.oc_ic_mode_switchumask=0x2,event=0x28aOC Mode Switch. OC to IC mode switchic_oc_mode_switch.ic_oc_mode_switchumask=0x1,event=0x28aOC Mode Switch. IC to OC mode switchde_dis_dispatch_token_stalls0.retire_token_stallumask=0x40,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailablede_dis_dispatch_token_stalls0.agsq_token_stallumask=0x20,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailablede_dis_dispatch_token_stalls0.alu_token_stallumask=0x10,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailablede_dis_dispatch_token_stalls0.alsq3_0_token_stallumask=0x8,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailablede_dis_dispatch_token_stalls0.alsq3_token_stallumask=0x4,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailablede_dis_dispatch_token_stalls0.alsq2_token_stallumask=0x2,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailablede_dis_dispatch_token_stalls0.alsq1_token_stallumask=0x1,event=0xafCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailableL1 Branch Prediction Overrides Existing Prediction (speculative)L2 Branch Prediction Overrides Existing Prediction (speculative)bp_l1_tlb_fetch_hitumask=0xFF,event=0x94The number of instruction fetches that hit in the L1 ITLBbp_l1_tlb_fetch_hit.if1gumask=0x4,event=0x94The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB pagebp_l1_tlb_fetch_hit.if2mumask=0x2,event=0x94The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB pagebp_l1_tlb_fetch_hit.if4kumask=0x1,event=0x94The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB pagel2_pf_hit_l2umask=0xff,event=0x70L2 prefetch hit in L2l2_pf_miss_l2_hit_l3umask=0xff,event=0x71L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3l2_pf_miss_l2_l3umask=0xff,event=0x72L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesbp_l1_tlb_miss_l2_tlb_missumask=0xff,event=0x85bp_l1_tlb_miss_l2_tlb_miss.if1gumask=0x4,event=0x85The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB pagebp_l1_tlb_miss_l2_tlb_miss.if2mumask=0x2,event=0x85The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB pagebp_l1_tlb_miss_l2_tlb_miss.if4kumask=0x1,event=0x85The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB pageThe number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8ex_ret_cond_mispevent=0xd2Retired Conditional Branch Instructions MispredictedRetired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8Total number of fp uOpsTotal number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPSTotal number uOps assigned to pipe 3Total number uOps assigned to pipe 2Total number uOps assigned to pipe 1All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.mac_flopsMultiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.div_flopsDivide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.mult_flopsMultiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.add_sub_flopsAdd/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesSSE bottom-executing uOps retired. The number of serializing Ops retiredx87 bottom-executing uOps retired. The number of serializing Ops retiredx87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retiredfp_disp_faults.ymm_spill_faultumask=0x8,event=0xeFloating Point Dispatch Faults. YMM spill faultfp_disp_faults.ymm_fill_faultumask=0x4,event=0xeFloating Point Dispatch Faults. YMM fill faultfp_disp_faults.xmm_fill_faultumask=0x2,event=0xeFloating Point Dispatch Faults. XMM fill faultfp_disp_faults.x87_fill_faultumask=0x1,event=0xeFloating Point Dispatch Faults. x87 fill faultls_bad_status2.stli_otherumask=0x2,event=0x24Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reasonStore-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element storesls_locks.spec_lock_hi_specumask=0x8,event=0x25Retired lock instructions. High speculative cacheable lock speculation succeededls_locks.spec_lock_lo_specumask=0x4,event=0x25Retired lock instructions. Low speculative cacheable lock speculation succeededls_locks.non_spec_lockumask=0x2,event=0x25Retired lock instructions. Non-speculative lock succeededRetired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lockls_ret_cl_flushNumber of retired CLFLUSH instructionsls_ret_cpuidNumber of retired CPUID instructionsDispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an addressNumber of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedNumber of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedls_smi_rxevent=0x2bNumber of SMIs receivedls_int_takenevent=0x2cNumber of interrupts takenls_rdtscevent=0x2dNumber of reads of the TSC (RDTSC instructions). The count is speculativels_st_commit_cancel2.st_commit_cancel_wcb_fullevent=0x37A non-cacheable store and the non-cacheable commit buffer is fullNumber of accesses to the dcache for load/store referencesLS MAB Allocates by Type. DC prefetcherLS MAB Allocates by Type. Storesumask=0x1,event=0x41LS MAB Allocates by Type. Loadsls_refills_from_sys.ls_mabresp_rmt_dramumask=0x40,event=0x43Demand Data Cache Fills by Data Source. DRAM or IO from different diels_refills_from_sys.ls_mabresp_rmt_cacheumask=0x10,event=0x43Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different diels_refills_from_sys.ls_mabresp_lcl_dramumask=0x8,event=0x43Demand Data Cache Fills by Data Source. DRAM or IO from this thread's diels_refills_from_sys.ls_mabresp_lcl_cacheumask=0x2,event=0x43Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's diels_refills_from_sys.ls_mabresp_lcl_l2umask=0x1,event=0x43Demand Data Cache Fills by Data Source. Local L2 hitAll L1 DTLB Misses or ReloadsL1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLBls_l1_d_tlb_miss.tlb_reload_coalesced_page_missL1 DTLB Miss. DTLB reload coalesced page missL1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLBL1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLBls_l1_d_tlb_miss.tlb_reload_coalesced_page_hitL1 DTLB Miss. DTLB reload hit a coalesced pageL1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLBls_pref_instr_dispumask=0xff,event=0x4bSoftware Prefetch Instructions Dispatched (Speculative)Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevells_pref_instr_disp.prefetch_wSoftware Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHWls_pref_instr_disp.prefetchSoftware Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevells_sw_pf_dc_fill.ls_mabresp_rmt_dramumask=0x40,event=0x59Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)ls_sw_pf_dc_fill.ls_mabresp_rmt_cacheumask=0x10,event=0x59Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote)ls_sw_pf_dc_fill.ls_mabresp_lcl_dramumask=0x8,event=0x59Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local)ls_sw_pf_dc_fill.ls_mabresp_lcl_cacheumask=0x2,event=0x59Software Prefetch Data Cache Fills by Data Source. From another cache (home node local)ls_sw_pf_dc_fill.ls_mabresp_lcl_l2umask=0x1,event=0x59Software Prefetch Data Cache Fills by Data Source. Local L2 hitls_hw_pf_dc_fill.ls_mabresp_rmt_dramumask=0x40,event=0x5aHardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)ls_hw_pf_dc_fill.ls_mabresp_rmt_cacheumask=0x10,event=0x5aHardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote)ls_hw_pf_dc_fill.ls_mabresp_lcl_dramumask=0x8,event=0x5aHardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local)ls_hw_pf_dc_fill.ls_mabresp_lcl_cacheumask=0x2,event=0x5aHardware Prefetch Data Cache Fills by Data Source. From another cache (home node local)ls_hw_pf_dc_fill.ls_mabresp_lcl_l2umask=0x1,event=0x5aHardware Prefetch Data Cache Fills by Data Source. Local L2 hitls_tlb_flushevent=0x78All TLB Flushesde_dis_uop_queue_empty_di0event=0xa9Cycles where the Micro-Op Queue is emptyde_dis_uops_from_decoderumask=0xff,event=0xaaOps dispatched from either the decoders, OpCache or bothde_dis_uops_from_decoder.opcache_dispatchedumask=0x2,event=0xaaCount of dispatched Ops from OpCachede_dis_uops_from_decoder.decoder_dispatchedumask=0x1,event=0xaaCount of dispatched Ops from Decoderde_dis_dispatch_token_stalls1.fp_misc_rsrc_stallumask=0x80,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP opsde_dis_dispatch_token_stalls1.fp_sch_rsrc_stallumask=0x40,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP schedulerde_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stallumask=0x20,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination registerde_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stallumask=0x10,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stallde_dis_dispatch_token_stalls1.int_sched_misc_token_stallumask=0x8,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stallde_dis_dispatch_token_stalls1.store_queue_token_stallumask=0x4,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semanticsde_dis_dispatch_token_stalls1.load_queue_token_stallumask=0x2,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semanticsde_dis_dispatch_token_stalls1.int_phy_reg_file_token_stallumask=0x1,event=0xaeCycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination registerde_dis_dispatch_token_stalls0.sc_agu_dispatch_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. 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pme_tremontxpme_haswellxpme_broadwellxpme_nehalemexpme_skylakexpme_cascadelakexpme_westmereex.debug_abbrev.textpme_silvermontpme_goldmont.commentpme_goldmontplus.debug_str.L.strpme_westmereep_sppme_nehalemeppme_westmereep_dppmu_events_map.rel.debug_infopme_ivytownpme_jaketownpme_haswellpme_broadwellpme_bonnell.note.GNU-stackpme_knightslanding.llvm_addrsig.debug_linepme_skylakepme_icelakepme_ivybridgepme_sandybridgepme_broadwelldelibpmc_events.c.strtab.symtab.rel.data.L.str.9999.L.str.18999.L.str.8999.L.str.17999.L.str.7999.L.str.16999.L.str.6999.L.str.15999.L.str.5999.L.str.14999.L.str.4999.L.str.13999.L.str.3999.L.str.12999.L.str.2999.L.str.11999.L.str.1999.L.str.10999.L.str.999.L.str.9899.L.str.18899.L.str.8899.L.str.17899.L.str.7899.L.str.16899.L.str.6899.L.str.15899.L.str.5899.L.str.14899.L.str.4899.L.str.13899.L.str.3899.L.str.12899.L.str.2899.L.str.11899.L.str.1899.L.str.10899.L.str.899.L.str.19799.L.str.9799.L.str.18799.L.str.8799.L.str.17799.L.str.7799.L.str.16799.L.str.6799.L.str.15799.L.str.5799.L.str.14799.L.str.4799.L.str.13799.L.str.3799.L.str.12799.L.str.2799.L.str.11799.L.str.1799.L.str.10799.L.str.799.L.str.19699.L.str.9699.L.str.18699.L.str.8699.L.str.17699.L.str.7699.L.str.16699.L.str.6699.L.str.15699.L.str.5699.L.str.14699.L.str.4699.L.str.13699.L.str.3699.L.str.12699.L.str.2699.L.str.11699.L.str.1699.L.str.10699.L.str.699.L.str.19599.L.str.9599.L.str.18599.L.str.8599.L.str.17599.L.str.7599.L.str.16599.L.str.6599.L.str.15599.L.str.5599.L.str.14599.L.str.4599.L.str.13599.L.str.3599.L.str.12599.L.str.2599.L.str.11599.L.str.1599.L.str.10599.L.str.599.L.str.19499.L.str.9499.L.str.18499.L.str.8499.L.str.17499.L.str.7499.L.str.16499.L.str.6499.L.str.15499.L.str.5499.L.str.14499.L.str.4499.L.str.13499.L.str.3499.L.str.12499.L.str.2499.L.str.11499.L.str.1499.L.str.10499.L.str.499.L.str.19399.L.str.9399.L.str.18399.L.str.8399.L.str.17399.L.str.7399.L.str.16399.L.str.6399.L.str.15399.L.str.5399.L.str.14399.L.str.4399.L.str.13399.L.str.3399.L.str.12399.L.str.2399.L.str.11399.L.str.1399.L.str.10399.L.str.399.L.str.19299.L.str.9299.L.str.18299.L.str.8299.L.str.17299.L.str.7299.L.str.16299.L.str.6299.L.str.15299.L.str.5299.L.str.14299.L.str.4299.L.str.13299.L.str.3299.L.str.12299.L.str.2299.L.str.11299.L.str.1299.L.str.10299.L.str.299.L.str.19199.L.str.9199.L.str.18199.L.str.8199.L.str.17199.L.str.7199.L.str.16199.L.str.6199.L.str.15199.L.str.5199.L.str.14199.L.str.4199.L.str.13199.L.str.3199.L.str.12199.L.str.2199.L.str.11199.L.str.1199.L.str.10199.L.str.199.L.str.19099.L.str.9099.L.str.18099.L.str.8099.L.str.17099.L.str.7099.L.str.16099.L.str.6099.L.str.15099.L.str.5099.L.str.14099.L.str.4099.L.str.13099.L.str.3099.L.str.12099.L.str.2099.L.str.11099.L.str.1099.L.str.10099.L.str.99.L.str.9989.L.str.18989.L.str.8989.L.str.17989.L.str.7989.L.str.16989.L.str.6989.L.str.15989.L.str.5989.L.str.14989.L.str.4989.L.str.13989.L.str.3989.L.str.12989.L.str.2989.L.str.11989.L.str.1989.L.str.10989.L.str.989.L.str.9889.L.str.18889.L.str.8889.L.str.17889.L.str.7889.L.str.16889.L.str.6889.L.str.15889.L.str.5889.L.str.14889.L.str.4889.L.str.13889.L.str.3889.L.str.12889.L.str.2889.L.str.11889.L.str.1889.L.str.10889.L.str.889.L.str.19789.L.str.9789.L.str.18789.L.str.8789.L.str.17789.L.str.7789.L.str.16789.L.str.6789.L.str.15789.L.str.5789.L.str.14789.L.str.4789.L.str.13789.L.str.3789.L.str.12789.L.str.2789.L.str.11789.L.str.1789.L.str.10789.L.str.789.L.str.19689.L.str.9689.L.str.18689.L.str.8689.L.str.17689.L.str.7689.L.str.16689.L.str.6689.L.str.15689.L.str.5689.L.str.14689.L.str.4689.L.str.13689.L.str.3689.L.str.12689.L.str.2689.L.str.11689.L.str.1689.L.str.10689.L.str.689.L.str.19589.L.str.9589.L.str.18589.L.str.8589.L.str.17589.L.str.7589.L.str.16589.L.str.6589.L.str.15589.L.str.5589.L.str.14589.L.str.4589.L.str.13589.L.str.3589.L.str.12589.L.str.2589.L.str.11589.L.str.1589.L.str.10589.L.str.589.L.str.19489.L.str.9489.L.str.18489.L.str.8489.L.str.17489.L.str.7489.L.str.16489.L.str.6489.L.str.15489.L.str.5489.L.str.14489.L.str.4489.L.str.13489.L.str.3489.L.str.12489.L.str.2489.L.str.11489.L.str.1489.L.str.10489.L.str.489.L.str.19389.L.str.9389.L.str.18389.L.str.8389.L.str.17389.L.str.7389.L.str.16389.L.str.6389.L.str.15389.L.str.5389.L.str.14389.L.str.4389.L.str.13389.L.str.3389.L.str.12389.L.str.2389.L.str.11389.L.str.1389.L.str.10389.L.str.389.L.str.19289.L.str.9289.L.str.18289.L.str.8289.L.str.17289.L.str.7289.L.str.16289.L.str.6289.L.str.15289.L.str.5289.L.str.14289.L.str.4289.L.str.13289.L.str.3289.L.str.12289.L.str.2289.L.str.11289.L.str.1289.L.str.10289.L.str.289.L.str.19189.L.str.9189.L.str.18189.L.str.8189.L.str.17189.L.str.7189.L.str.16189.L.str.6189.L.str.15189.L.str.5189.L.str.14189.L.str.4189.L.str.13189.L.str.3189.L.str.12189.L.str.2189.L.str.11189.L.str.1189.L.str.10189.L.str.189.L.str.19089.L.str.9089.L.str.18089.L.str.8089.L.str.17089.L.str.7089.L.str.16089.L.str.6089.L.str.15089.L.str.5089.L.str.14089.L.str.4089.L.str.13089.L.str.3089.L.str.12089.L.str.2089.L.str.11089.L.str.1089.L.str.10089.L.str.89.L.str.9979.L.str.18979.L.str.8979.L.str.17979.L.str.7979.L.str.16979.L.str.6979.L.str.15979.L.str.5979.L.str.14979.L.str.4979.L.str.13979.L.str.3979.L.str.12979.L.str.2979.L.str.11979.L.str.1979.L.str.10979.L.str.979.L.str.9879.L.str.18879.L.str.8879.L.str.17879.L.str.7879.L.str.16879.L.str.6879.L.str.15879.L.str.5879.L.str.14879.L.str.4879.L.str.13879.L.str.3879.L.str.12879.L.str.2879.L.str.11879.L.str.1879.L.str.10879.L.str.879.L.str.19779.L.str.9779.L.str.18779.L.str.8779.L.str.17779.L.str.7779.L.str.16779.L.str.6779.L.str.15779.L.str.5779.L.str.14779.L.str.4779.L.str.13779.L.str.3779.L.str.12779.L.str.2779.L.str.11779.L.str.1779.L.str.10779.L.str.779.L.str.19679.L.str.9679.L.str.18679.L.str.8679.L.str.17679.L.str.7679.L.str.16679.L.str.6679.L.str.15679.L.str.5679.L.str.14679.L.str.4679.L.str.13679.L.str.3679.L.str.12679.L.str.2679.L.str.11679.L.str.1679.L.str.10679.L.str.679.L.str.19579.L.str.9579.L.str.18579.L.str.8579.L.str.17579.L.str.7579.L.str.16579.L.str.6579.L.str.15579.L.str.5579.L.str.14579.L.str.4579.L.str.13579.L.str.3579.L.str.12579.L.str.2579.L.str.11579.L.str.1579.L.str.10579.L.str.579.L.str.19479.L.str.9479.L.str.18479.L.str.8479.L.str.17479.L.str.7479.L.str.16479.L.str.6479.L.str.15479.L.str.5479.L.str.14479.L.str.4479.L.str.13479.L.str.3479.L.str.12479.L.str.2479.L.str.11479.L.str.1479.L.str.10479.L.str.479.L.str.19379.L.str.9379.L.str.18379.L.str.8379.L.str.17379.L.str.7379.L.str.16379.L.str.6379.L.str.15379.L.str.5379.L.str.14379.L.str.4379.L.str.13379.L.str.3379.L.str.12379.L.str.2379.L.str.11379.L.str.1379.L.str.10379.L.str.379.L.str.19279.L.str.9279.L.str.18279.L.str.8279.L.str.17279.L.str.7279.L.str.16279.L.str.6279.L.str.15279.L.str.5279.L.str.14279.L.str.4279.L.str.13279.L.str.3279.L.str.12279.L.str.2279.L.str.11279.L.str.1279.L.str.10279.L.str.279.L.str.19179.L.str.9179.L.str.18179.L.str.8179.L.str.17179.L.str.7179.L.str.16179.L.str.6179.L.str.15179.L.str.5179.L.str.14179.L.str.4179.L.str.13179.L.str.3179.L.str.12179.L.str.2179.L.str.11179.L.str.1179.L.str.10179.L.str.179.L.str.19079.L.str.9079.L.str.18079.L.str.8079.L.str.17079.L.str.7079.L.str.16079.L.str.6079.L.str.15079.L.str.5079.L.str.14079.L.str.4079.L.str.13079.L.str.3079.L.str.12079.L.str.2079.L.str.11079.L.str.1079.L.str.10079.L.str.79.L.str.9969.L.str.18969.L.str.8969.L.str.17969.L.str.7969.L.str.16969.L.str.6969.L.str.15969.L.str.5969.L.str.14969.L.str.4969.L.str.13969.L.str.3969.L.str.12969.L.str.2969.L.str.11969.L.str.1969.L.str.10969.L.str.969.L.str.19869.L.str.9869.L.str.18869.L.str.8869.L.str.17869.L.str.7869.L.str.16869.L.str.6869.L.str.15869.L.str.5869.L.str.14869.L.str.4869.L.str.13869.L.str.3869.L.str.12869.L.str.2869.L.str.11869.L.str.1869.L.str.10869.L.str.869.L.str.19769.L.str.9769.L.str.18769.L.str.8769.L.str.17769.L.str.7769.L.str.16769.L.str.6769.L.str.15769.L.str.5769.L.str.14769.L.str.4769.L.str.13769.L.str.3769.L.str.12769.L.str.2769.L.str.11769.L.str.1769.L.str.10769.L.str.769.L.str.19669.L.str.9669.L.str.18669.L.str.8669.L.str.17669.L.str.7669.L.str.16669.L.str.6669.L.str.15669.L.str.5669.L.str.14669.L.str.4669.L.str.13669.L.str.3669.L.str.12669.L.str.2669.L.str.11669.L.str.1669.L.str.10669.L.str.669.L.str.19569.L.str.9569.L.str.18569.L.str.8569.L.str.17569.L.str.7569.L.str.16569.L.str.6569.L.str.15569.L.str.5569.L.str.14569.L.str.4569.L.str.13569.L.str.3569.L.str.12569.L.str.2569.L.str.11569.L.str.1569.L.str.10569.L.str.569.L.str.19469.L.str.9469.L.str.18469.L.str.8469.L.str.17469.L.str.7469.L.str.16469.L.str.6469.L.str.15469.L.str.5469.L.str.14469.L.str.4469.L.str.13469.L.str.3469.L.str.12469.L.str.2469.L.str.11469.L.str.1469.L.str.10469.L.str.469.L.str.19369.L.str.9369.L.str.18369.L.str.8369.L.str.17369.L.str.7369.L.str.16369.L.str.6369.L.str.15369.L.str.5369.L.str.14369.L.str.4369.L.str.13369.L.str.3369.L.str.12369.L.str.2369.L.str.11369.L.str.1369.L.str.10369.L.str.369.L.str.19269.L.str.9269.L.str.18269.L.str.8269.L.str.17269.L.str.7269.L.str.16269.L.str.6269.L.str.15269.L.str.5269.L.str.14269.L.str.4269.L.str.13269.L.str.3269.L.str.12269.L.str.2269.L.str.11269.L.str.1269.L.str.10269.L.str.269.L.str.19169.L.str.9169.L.str.18169.L.str.8169.L.str.17169.L.str.7169.L.str.16169.L.str.6169.L.str.15169.L.str.5169.L.str.14169.L.str.4169.L.str.13169.L.str.3169.L.str.12169.L.str.2169.L.str.11169.L.str.1169.L.str.10169.L.str.169.L.str.19069.L.str.9069.L.str.18069.L.str.8069.L.str.17069.L.str.7069.L.str.16069.L.str.6069.L.str.15069.L.str.5069.L.str.14069.L.str.4069.L.str.13069.L.str.3069.L.str.12069.L.str.2069.L.str.11069.L.str.1069.L.str.10069.L.str.69.L.str.9959.L.str.18959.L.str.8959.L.str.17959.L.str.7959.L.str.16959.L.str.6959.L.str.15959.L.str.5959.L.str.14959.L.str.4959.L.str.13959.L.str.3959.L.str.12959.L.str.2959.L.str.11959.L.str.1959.L.str.10959.L.str.959.L.str.19859.L.str.9859.L.str.18859.L.str.8859.L.str.17859.L.str.7859.L.str.16859.L.str.6859.L.str.15859.L.str.5859.L.str.14859.L.str.4859.L.str.13859.L.str.3859.L.str.12859.L.str.2859.L.str.11859.L.str.1859.L.str.10859.L.str.859.L.str.19759.L.str.9759.L.str.18759.L.str.8759.L.str.17759.L.str.7759.L.str.16759.L.str.6759.L.str.15759.L.str.5759.L.str.14759.L.str.4759.L.str.13759.L.str.3759.L.str.12759.L.str.2759.L.str.11759.L.str.1759.L.str.10759.L.str.759.L.str.19659.L.str.9659.L.str.18659.L.str.8659.L.str.17659.L.str.7659.L.str.16659.L.str.6659.L.str.15659.L.str.5659.L.str.14659.L.str.4659.L.str.13659.L.str.3659.L.str.12659.L.str.2659.L.str.11659.L.str.1659.L.str.10659.L.str.659.L.str.19559.L.str.9559.L.str.18559.L.str.8559.L.str.17559.L.str.7559.L.str.16559.L.str.6559.L.str.15559.L.str.5559.L.str.14559.L.str.4559.L.str.13559.L.str.3559.L.str.12559.L.str.2559.L.str.11559.L.str.1559.L.str.10559.L.str.559.L.str.19459.L.str.9459.L.str.18459.L.str.8459.L.str.17459.L.str.7459.L.str.16459.L.str.6459.L.str.15459.L.str.5459.L.str.14459.L.str.4459.L.str.13459.L.str.3459.L.str.12459.L.str.2459.L.str.11459.L.str.1459.L.str.10459.L.str.459.L.str.19359.L.str.9359.L.str.18359.L.str.8359.L.str.17359.L.str.7359.L.str.16359.L.str.6359.L.str.15359.L.str.5359.L.str.14359.L.str.4359.L.str.13359.L.str.3359.L.str.12359.L.str.2359.L.str.11359.L.str.1359.L.str.10359.L.str.359.L.str.19259.L.str.9259.L.str.18259.L.str.8259.L.str.17259.L.str.7259.L.str.16259.L.str.6259.L.str.15259.L.str.5259.L.str.14259.L.str.4259.L.str.13259.L.str.3259.L.str.12259.L.str.2259.L.str.11259.L.str.1259.L.str.10259.L.str.259.L.str.19159.L.str.9159.L.str.18159.L.str.8159.L.str.17159.L.str.7159.L.str.16159.L.str.6159.L.str.15159.L.str.5159.L.str.14159.L.str.4159.L.str.13159.L.str.3159.L.str.12159.L.str.2159.L.str.11159.L.str.1159.L.str.10159.L.str.159.L.str.19059.L.str.9059.L.str.18059.L.str.8059.L.str.17059.L.str.7059.L.str.16059.L.str.6059.L.str.15059.L.str.5059.L.str.14059.L.str.4059.L.str.13059.L.str.3059.L.str.12059.L.str.2059.L.str.11059.L.str.1059.L.str.10059.L.str.59.L.str.9949.L.str.18949.L.str.8949.L.str.17949.L.str.7949.L.str.16949.L.str.6949.L.str.15949.L.str.5949.L.str.14949.L.str.4949.L.str.13949.L.str.3949.L.str.12949.L.str.2949.L.str.11949.L.str.1949.L.str.10949.L.str.949.L.str.19849.L.str.9849.L.str.18849.L.str.8849.L.str.17849.L.str.7849.L.str.16849.L.str.6849.L.str.15849.L.str.5849.L.str.14849.L.str.4849.L.str.13849.L.str.3849.L.str.12849.L.str.2849.L.str.11849.L.str.1849.L.str.10849.L.str.849.L.str.19749.L.str.9749.L.str.18749.L.str.8749.L.str.17749.L.str.7749.L.str.16749.L.str.6749.L.str.15749.L.str.5749.L.str.14749.L.str.4749.L.str.13749.L.str.3749.L.str.12749.L.str.2749.L.str.11749.L.str.1749.L.str.10749.L.str.749.L.str.19649.L.str.9649.L.str.18649.L.str.8649.L.str.17649.L.str.7649.L.str.16649.L.str.6649.L.str.15649.L.str.5649.L.str.14649.L.str.4649.L.str.13649.L.str.3649.L.str.12649.L.str.2649.L.str.11649.L.str.1649.L.str.10649.L.str.649.L.str.19549.L.str.9549.L.str.18549.L.str.8549.L.str.17549.L.str.7549.L.str.16549.L.str.6549.L.str.15549.L.str.5549.L.str.14549.L.str.4549.L.str.13549.L.str.3549.L.str.12549.L.str.2549.L.str.11549.L.str.1549.L.str.10549.L.str.549.L.str.19449.L.str.9449.L.str.18449.L.str.8449.L.str.17449.L.str.7449.L.str.16449.L.str.6449.L.str.15449.L.str.5449.L.str.14449.L.str.4449.L.str.13449.L.str.3449.L.str.12449.L.str.2449.L.str.11449.L.str.1449.L.str.10449.L.str.449.L.str.19349.L.str.9349.L.str.18349.L.str.8349.L.str.17349.L.str.7349.L.str.16349.L.str.6349.L.str.15349.L.str.5349.L.str.14349.L.str.4349.L.str.13349.L.str.3349.L.str.12349.L.str.2349.L.str.11349.L.str.1349.L.str.10349.L.str.349.L.str.19249.L.str.9249.L.str.18249.L.str.8249.L.str.17249.L.str.7249.L.str.16249.L.str.6249.L.str.15249.L.str.5249.L.str.14249.L.str.4249.L.str.13249.L.str.3249.L.str.12249.L.str.2249.L.str.11249.L.str.1249.L.str.10249.L.str.249.L.str.19149.L.str.9149.L.str.18149.L.str.8149.L.str.17149.L.str.7149.L.str.16149.L.str.6149.L.str.15149.L.str.5149.L.str.14149.L.str.4149.L.str.13149.L.str.3149.L.str.12149.L.str.2149.L.str.11149.L.str.1149.L.str.10149.L.str.149.L.str.19049.L.str.9049.L.str.18049.L.str.8049.L.str.17049.L.str.7049.L.str.16049.L.str.6049.L.str.15049.L.str.5049.L.str.14049.L.str.4049.L.str.13049.L.str.3049.L.str.12049.L.str.2049.L.str.11049.L.str.1049.L.str.10049.L.str.49.L.str.9939.L.str.18939.L.str.8939.L.str.17939.L.str.7939.L.str.16939.L.str.6939.L.str.15939.L.str.5939.L.str.14939.L.str.4939.L.str.13939.L.str.3939.L.str.12939.L.str.2939.L.str.11939.L.str.1939.L.str.10939.L.str.939.L.str.19839.L.str.9839.L.str.18839.L.str.8839.L.str.17839.L.str.7839.L.str.16839.L.str.6839.L.str.15839.L.str.5839.L.str.14839.L.str.4839.L.str.13839.L.str.3839.L.str.12839.L.str.2839.L.str.11839.L.str.1839.L.str.10839.L.str.839.L.str.19739.L.str.9739.L.str.18739.L.str.8739.L.str.17739.L.str.7739.L.str.16739.L.str.6739.L.str.15739.L.str.5739.L.str.14739.L.str.4739.L.str.13739.L.str.3739.L.str.12739.L.str.2739.L.str.11739.L.str.1739.L.str.10739.L.str.739.L.str.19639.L.str.9639.L.str.18639.L.str.8639.L.str.17639.L.str.7639.L.str.16639.L.str.6639.L.str.15639.L.str.5639.L.str.14639.L.str.4639.L.str.13639.L.str.3639.L.str.12639.L.str.2639.L.str.11639.L.str.1639.L.str.10639.L.str.639.L.str.19539.L.str.9539.L.str.18539.L.str.8539.L.str.17539.L.str.7539.L.str.16539.L.str.6539.L.str.15539.L.str.5539.L.str.14539.L.str.4539.L.str.13539.L.str.3539.L.str.12539.L.str.2539.L.str.11539.L.str.1539.L.str.10539.L.str.539.L.str.19439.L.str.9439.L.str.18439.L.str.8439.L.str.17439.L.str.7439.L.str.16439.L.str.6439.L.str.15439.L.str.5439.L.str.14439.L.str.4439.L.str.13439.L.str.3439.L.str.12439.L.str.2439.L.str.11439.L.str.1439.L.str.10439.L.str.439.L.str.19339.L.str.9339.L.str.18339.L.str.8339.L.str.17339.L.str.7339.L.str.16339.L.str.6339.L.str.15339.L.str.5339.L.str.14339.L.str.4339.L.str.13339.L.str.3339.L.str.12339.L.str.2339.L.str.11339.L.str.1339.L.str.10339.L.str.339.L.str.19239.L.str.9239.L.str.18239.L.str.8239.L.str.17239.L.str.7239.L.str.16239.L.str.6239.L.str.15239.L.str.5239.L.str.14239.L.str.4239.L.str.13239.L.str.3239.L.str.12239.L.str.2239.L.str.11239.L.str.1239.L.str.10239.L.str.239.L.str.19139.L.str.9139.L.str.18139.L.str.8139.L.str.17139.L.str.7139.L.str.16139.L.str.6139.L.str.15139.L.str.5139.L.str.14139.L.str.4139.L.str.13139.L.str.3139.L.str.12139.L.str.2139.L.str.11139.L.str.1139.L.str.10139.L.str.139.L.str.19039.L.str.9039.L.str.18039.L.str.8039.L.str.17039.L.str.7039.L.str.16039.L.str.6039.L.str.15039.L.str.5039.L.str.14039.L.str.4039.L.str.13039.L.str.3039.L.str.12039.L.str.2039.L.str.11039.L.str.1039.L.str.10039.L.str.39.L.str.9929.L.str.18929.L.str.8929.L.str.17929.L.str.7929.L.str.16929.L.str.6929.L.str.15929.L.str.5929.L.str.14929.L.str.4929.L.str.13929.L.str.3929.L.str.12929.L.str.2929.L.str.11929.L.str.1929.L.str.10929.L.str.929.L.str.19829.L.str.9829.L.str.18829.L.str.8829.L.str.17829.L.str.7829.L.str.16829.L.str.6829.L.str.15829.L.str.5829.L.str.14829.L.str.4829.L.str.13829.L.str.3829.L.str.12829.L.str.2829.L.str.11829.L.str.1829.L.str.10829.L.str.829.L.str.19729.L.str.9729.L.str.18729.L.str.8729.L.str.17729.L.str.7729.L.str.16729.L.str.6729.L.str.15729.L.str.5729.L.str.14729.L.str.4729.L.str.13729.L.str.3729.L.str.12729.L.str.2729.L.str.11729.L.str.1729.L.str.10729.L.str.729.L.str.19629.L.str.9629.L.str.18629.L.str.8629.L.str.17629.L.str.7629.L.str.16629.L.str.6629.L.str.15629.L.str.5629.L.str.14629.L.str.4629.L.str.13629.L.str.3629.L.str.12629.L.str.2629.L.str.11629.L.str.1629.L.str.10629.L.str.629.L.str.19529.L.str.9529.L.str.18529.L.str.8529.L.str.17529.L.str.7529.L.str.16529.L.str.6529.L.str.15529.L.str.5529.L.str.14529.L.str.4529.L.str.13529.L.str.3529.L.str.12529.L.str.2529.L.str.11529.L.str.1529.L.str.10529.L.str.529.L.str.19429.L.str.9429.L.str.18429.L.str.8429.L.str.17429.L.str.7429.L.str.16429.L.str.6429.L.str.15429.L.str.5429.L.str.14429.L.str.4429.L.str.13429.L.str.3429.L.str.12429.L.str.2429.L.str.11429.L.str.1429.L.str.10429.L.str.429.L.str.19329.L.str.9329.L.str.18329.L.str.8329.L.str.17329.L.str.7329.L.str.16329.L.str.6329.L.str.15329.L.str.5329.L.str.14329.L.str.4329.L.str.13329.L.str.3329.L.str.12329.L.str.2329.L.str.11329.L.str.1329.L.str.10329.L.str.329.L.str.19229.L.str.9229.L.str.18229.L.str.8229.L.str.17229.L.str.7229.L.str.16229.L.str.6229.L.str.15229.L.str.5229.L.str.14229.L.str.4229.L.str.13229.L.str.3229.L.str.12229.L.str.2229.L.str.11229.L.str.1229.L.str.10229.L.str.229.L.str.19129.L.str.9129.L.str.18129.L.str.8129.L.str.17129.L.str.7129.L.str.16129.L.str.6129.L.str.15129.L.str.5129.L.str.14129.L.str.4129.L.str.13129.L.str.3129.L.str.12129.L.str.2129.L.str.11129.L.str.1129.L.str.10129.L.str.129.L.str.19029.L.str.9029.L.str.18029.L.str.8029.L.str.17029.L.str.7029.L.str.16029.L.str.6029.L.str.15029.L.str.5029.L.str.14029.L.str.4029.L.str.13029.L.str.3029.L.str.12029.L.str.2029.L.str.11029.L.str.1029.L.str.10029.L.str.29.L.str.9919.L.str.18919.L.str.8919.L.str.17919.L.str.7919.L.str.16919.L.str.6919.L.str.15919.L.str.5919.L.str.14919.L.str.4919.L.str.13919.L.str.3919.L.str.12919.L.str.2919.L.str.11919.L.str.1919.L.str.10919.L.str.919.L.str.19819.L.str.9819.L.str.18819.L.str.8819.L.str.17819.L.str.7819.L.str.16819.L.str.6819.L.str.15819.L.str.5819.L.str.14819.L.str.4819.L.str.13819.L.str.3819.L.str.12819.L.str.2819.L.str.11819.L.str.1819.L.str.10819.L.str.819.L.str.19719.L.str.9719.L.str.18719.L.str.8719.L.str.17719.L.str.7719.L.str.16719.L.str.6719.L.str.15719.L.str.5719.L.str.14719.L.str.4719.L.str.13719.L.str.3719.L.str.12719.L.str.2719.L.str.11719.L.str.1719.L.str.10719.L.str.719.L.str.19619.L.str.9619.L.str.18619.L.str.8619.L.str.17619.L.str.7619.L.str.16619.L.str.6619.L.str.15619.L.str.5619.L.str.14619.L.str.4619.L.str.13619.L.str.3619.L.str.12619.L.str.2619.L.str.11619.L.str.1619.L.str.10619.L.str.619.L.str.19519.L.str.9519.L.str.18519.L.str.8519.L.str.17519.L.str.7519.L.str.16519.L.str.6519.L.str.15519.L.str.5519.L.str.14519.L.str.4519.L.str.13519.L.str.3519.L.str.12519.L.str.2519.L.str.11519.L.str.1519.L.str.10519.L.str.519.L.str.19419.L.str.9419.L.str.18419.L.str.8419.L.str.17419.L.str.7419.L.str.16419.L.str.6419.L.str.15419.L.str.5419.L.str.14419.L.str.4419.L.str.13419.L.str.3419.L.str.12419.L.str.2419.L.str.11419.L.str.1419.L.str.10419.L.str.419.L.str.19319.L.str.9319.L.str.18319.L.str.8319.L.str.17319.L.str.7319.L.str.16319.L.str.6319.L.str.15319.L.str.5319.L.str.14319.L.str.4319.L.str.13319.L.str.3319.L.str.12319.L.str.2319.L.str.11319.L.str.1319.L.str.10319.L.str.319.L.str.19219.L.str.9219.L.str.18219.L.str.8219.L.str.17219.L.str.7219.L.str.16219.L.str.6219.L.str.15219.L.str.5219.L.str.14219.L.str.4219.L.str.13219.L.str.3219.L.str.12219.L.str.2219.L.str.11219.L.str.1219.L.str.10219.L.str.219.L.str.19119.L.str.9119.L.str.18119.L.str.8119.L.str.17119.L.str.7119.L.str.16119.L.str.6119.L.str.15119.L.str.5119.L.str.14119.L.str.4119.L.str.13119.L.str.3119.L.str.12119.L.str.2119.L.str.11119.L.str.1119.L.str.10119.L.str.119.L.str.19019.L.str.9019.L.str.18019.L.str.8019.L.str.17019.L.str.7019.L.str.16019.L.str.6019.L.str.15019.L.str.5019.L.str.14019.L.str.4019.L.str.13019.L.str.3019.L.str.12019.L.str.2019.L.str.11019.L.str.1019.L.str.10019.L.str.19.L.str.9909.L.str.18909.L.str.8909.L.str.17909.L.str.7909.L.str.16909.L.str.6909.L.str.15909.L.str.5909.L.str.14909.L.str.4909.L.str.13909.L.str.3909.L.str.12909.L.str.2909.L.str.11909.L.str.1909.L.str.10909.L.str.909.L.str.19809.L.str.9809.L.str.18809.L.str.8809.L.str.17809.L.str.7809.L.str.16809.L.str.6809.L.str.15809.L.str.5809.L.str.14809.L.str.4809.L.str.13809.L.str.3809.L.str.12809.L.str.2809.L.str.11809.L.str.1809.L.str.10809.L.str.809.L.str.19709.L.str.9709.L.str.18709.L.str.8709.L.str.17709.L.str.7709.L.str.16709.L.str.6709.L.str.15709.L.str.5709.L.str.14709.L.str.4709.L.str.13709.L.str.3709.L.str.12709.L.str.2709.L.str.11709.L.str.1709.L.str.10709.L.str.709.L.str.19609.L.str.9609.L.str.18609.L.str.8609.L.str.17609.L.str.7609.L.str.16609.L.str.6609.L.str.15609.L.str.5609.L.str.14609.L.str.4609.L.str.13609.L.str.3609.L.str.12609.L.str.2609.L.str.11609.L.str.1609.L.str.10609.L.str.609.L.str.19509.L.str.9509.L.str.18509.L.str.8509.L.str.17509.L.str.7509.L.str.16509.L.str.6509.L.str.15509.L.str.5509.L.str.14509.L.str.4509.L.str.13509.L.str.3509.L.str.12509.L.str.2509.L.str.11509.L.str.1509.L.str.10509.L.str.509.L.str.19409.L.str.9409.L.str.18409.L.str.8409.L.str.17409.L.str.7409.L.str.16409.L.str.6409.L.str.15409.L.str.5409.L.str.14409.L.str.4409.L.str.13409.L.str.3409.L.str.12409.L.str.2409.L.str.11409.L.str.1409.L.str.10409.L.str.409.L.str.19309.L.str.9309.L.str.18309.L.str.8309.L.str.17309.L.str.7309.L.str.16309.L.str.6309.L.str.15309.L.str.5309.L.str.14309.L.str.4309.L.str.13309.L.str.3309.L.str.12309.L.str.2309.L.str.11309.L.str.1309.L.str.10309.L.str.309.L.str.19209.L.str.9209.L.str.18209.L.str.8209.L.str.17209.L.str.7209.L.str.16209.L.str.6209.L.str.15209.L.str.5209.L.str.14209.L.str.4209.L.str.13209.L.str.3209.L.str.12209.L.str.2209.L.str.11209.L.str.1209.L.str.10209.L.str.209.L.str.19109.L.str.9109.L.str.18109.L.str.8109.L.str.17109.L.str.7109.L.str.16109.L.str.6109.L.str.15109.L.str.5109.L.str.14109.L.str.4109.L.str.13109.L.str.3109.L.str.12109.L.str.2109.L.str.11109.L.str.1109.L.str.10109.L.str.109.L.str.19009.L.str.9009.L.str.18009.L.str.8009.L.str.17009.L.str.7009.L.str.16009.L.str.6009.L.str.15009.L.str.5009.L.str.14009.L.str.4009.L.str.13009.L.str.3009.L.str.12009.L.str.2009.L.str.11009.L.str.1009.L.str.10009.L.str.9.L.str.9998.L.str.18998.L.str.8998.L.str.17998.L.str.7998.L.str.16998.L.str.6998.L.str.15998.L.str.5998.L.str.14998.L.str.4998.L.str.13998.L.str.3998.L.str.12998.L.str.2998.L.str.11998.L.str.1998.L.str.10998.L.str.998.L.str.9898.L.str.18898.L.str.8898.L.str.17898.L.str.7898.L.str.16898.L.str.6898.L.str.15898.L.str.5898.L.str.14898.L.str.4898.L.str.13898.L.str.3898.L.str.12898.L.str.2898.L.str.11898.L.str.1898.L.str.10898.L.str.898.L.str.19798.L.str.9798.L.str.18798.L.str.8798.L.str.17798.L.str.7798.L.str.16798.L.str.6798.L.str.15798.L.str.5798.L.str.14798.L.str.4798.L.str.13798.L.str.3798.L.str.12798.L.str.2798.L.str.11798.L.str.1798.L.str.10798.L.str.798.L.str.19698.L.str.9698.L.str.18698.L.str.8698.L.str.17698.L.str.7698.L.str.16698.L.str.6698.L.str.15698.L.str.5698.L.str.14698.L.str.4698.L.str.13698.L.str.3698.L.str.12698.L.str.2698.L.str.11698.L.str.1698.L.str.10698.L.str.698.L.str.19598.L.str.9598.L.str.18598.L.str.8598.L.str.17598.L.str.7598.L.str.16598.L.str.6598.L.str.15598.L.str.5598.L.str.14598.L.str.4598.L.str.13598.L.str.3598.L.str.12598.L.str.2598.L.str.11598.L.str.1598.L.str.10598.L.str.598.L.str.19498.L.str.9498.L.str.18498.L.str.8498.L.str.17498.L.str.7498.L.str.16498.L.str.6498.L.str.15498.L.str.5498.L.str.14498.L.str.4498.L.str.13498.L.str.3498.L.str.12498.L.str.2498.L.str.11498.L.str.1498.L.str.10498.L.str.498.L.str.19398.L.str.9398.L.str.18398.L.str.8398.L.str.17398.L.str.7398.L.str.16398.L.str.6398.L.str.15398.L.str.5398.L.str.14398.L.str.4398.L.str.13398.L.str.3398.L.str.12398.L.str.2398.L.str.11398.L.str.1398.L.str.10398.L.str.398.L.str.19298.L.str.9298.L.str.18298.L.str.8298.L.str.17298.L.str.7298.L.str.16298.L.str.6298.L.str.15298.L.str.5298.L.str.14298.L.str.4298.L.str.13298.L.str.3298.L.str.12298.L.str.2298.L.str.11298.L.str.1298.L.str.10298.L.str.298.L.str.19198.L.str.9198.L.str.18198.L.str.8198.L.str.17198.L.str.7198.L.str.16198.L.str.6198.L.str.15198.L.str.5198.L.str.14198.L.str.4198.L.str.13198.L.str.3198.L.str.12198.L.str.2198.L.str.11198.L.str.1198.L.str.10198.L.str.198.L.str.19098.L.str.9098.L.str.18098.L.str.8098.L.str.17098.L.str.7098.L.str.16098.L.str.6098.L.str.15098.L.str.5098.L.str.14098.L.str.4098.L.str.13098.L.str.3098.L.str.12098.L.str.2098.L.str.11098.L.str.1098.L.str.10098.L.str.98.L.str.9988.L.str.18988.L.str.8988.L.str.17988.L.str.7988.L.str.16988.L.str.6988.L.str.15988.L.str.5988.L.str.14988.L.str.4988.L.str.13988.L.str.3988.L.str.12988.L.str.2988.L.str.11988.L.str.1988.L.str.10988.L.str.988.L.str.9888.L.str.18888.L.str.8888.L.str.17888.L.str.7888.L.str.16888.L.str.6888.L.str.15888.L.str.5888.L.str.14888.L.str.4888.L.str.13888.L.str.3888.L.str.12888.L.str.2888.L.str.11888.L.str.1888.L.str.10888.L.str.888.L.str.19788.L.str.9788.L.str.18788.L.str.8788.L.str.17788.L.str.7788.L.str.16788.L.str.6788.L.str.15788.L.str.5788.L.str.14788.L.str.4788.L.str.13788.L.str.3788.L.str.12788.L.str.2788.L.str.11788.L.str.1788.L.str.10788.L.str.788.L.str.19688.L.str.9688.L.str.18688.L.str.8688.L.str.17688.L.str.7688.L.str.16688.L.str.6688.L.str.15688.L.str.5688.L.str.14688.L.str.4688.L.str.13688.L.str.3688.L.str.12688.L.str.2688.L.str.11688.L.str.1688.L.str.10688.L.str.688.L.str.19588.L.str.9588.L.str.18588.L.str.8588.L.str.17588.L.str.7588.L.str.16588.L.str.6588.L.str.15588.L.str.5588.L.str.14588.L.str.4588.L.str.13588.L.str.3588.L.str.12588.L.str.2588.L.str.11588.L.str.1588.L.str.10588.L.str.588.L.str.19488.L.str.9488.L.str.18488.L.str.8488.L.str.17488.L.str.7488.L.str.16488.L.str.6488.L.str.15488.L.str.5488.L.str.14488.L.str.4488.L.str.13488.L.str.3488.L.str.12488.L.str.2488.L.str.11488.L.str.1488.L.str.10488.L.str.488.L.str.19388.L.str.9388.L.str.18388.L.str.8388.L.str.17388.L.str.7388.L.str.16388.L.str.6388.L.str.15388.L.str.5388.L.str.14388.L.str.4388.L.str.13388.L.str.3388.L.str.12388.L.str.2388.L.str.11388.L.str.1388.L.str.10388.L.str.388.L.str.19288.L.str.9288.L.str.18288.L.str.8288.L.str.17288.L.str.7288.L.str.16288.L.str.6288.L.str.15288.L.str.5288.L.str.14288.L.str.4288.L.str.13288.L.str.3288.L.str.12288.L.str.2288.L.str.11288.L.str.1288.L.str.10288.L.str.288.L.str.19188.L.str.9188.L.str.18188.L.str.8188.L.str.17188.L.str.7188.L.str.16188.L.str.6188.L.str.15188.L.str.5188.L.str.14188.L.str.4188.L.str.13188.L.str.3188.L.str.12188.L.str.2188.L.str.11188.L.str.1188.L.str.10188.L.str.188.L.str.19088.L.str.9088.L.str.18088.L.str.8088.L.str.17088.L.str.7088.L.str.16088.L.str.6088.L.str.15088.L.str.5088.L.str.14088.L.str.4088.L.str.13088.L.str.3088.L.str.12088.L.str.2088.L.str.11088.L.str.1088.L.str.10088.L.str.88.L.str.9978.L.str.18978.L.str.8978.L.str.17978.L.str.7978.L.str.16978.L.str.6978.L.str.15978.L.str.5978.L.str.14978.L.str.4978.L.str.13978.L.str.3978.L.str.12978.L.str.2978.L.str.11978.L.str.1978.L.str.10978.L.str.978.L.str.9878.L.str.18878.L.str.8878.L.str.17878.L.str.7878.L.str.16878.L.str.6878.L.str.15878.L.str.5878.L.str.14878.L.str.4878.L.str.13878.L.str.3878.L.str.12878.L.str.2878.L.str.11878.L.str.1878.L.str.10878.L.str.878.L.str.19778.L.str.9778.L.str.18778.L.str.8778.L.str.17778.L.str.7778.L.str.16778.L.str.6778.L.str.15778.L.str.5778.L.str.14778.L.str.4778.L.str.13778.L.str.3778.L.str.12778.L.str.2778.L.str.11778.L.str.1778.L.str.10778.L.str.778.L.str.19678.L.str.9678.L.str.18678.L.str.8678.L.str.17678.L.str.7678.L.str.16678.L.str.6678.L.str.15678.L.str.5678.L.str.14678.L.str.4678.L.str.13678.L.str.3678.L.str.12678.L.str.2678.L.str.11678.L.str.1678.L.str.10678.L.str.678.L.str.19578.L.str.9578.L.str.18578.L.str.8578.L.str.17578.L.str.7578.L.str.16578.L.str.6578.L.str.15578.L.str.5578.L.str.14578.L.str.4578.L.str.13578.L.str.3578.L.str.12578.L.str.2578.L.str.11578.L.str.1578.L.str.10578.L.str.578.L.str.19478.L.str.9478.L.str.18478.L.str.8478.L.str.17478.L.str.7478.L.str.16478.L.str.6478.L.str.15478.L.str.5478.L.str.14478.L.str.4478.L.str.13478.L.str.3478.L.str.12478.L.str.2478.L.str.11478.L.str.1478.L.str.10478.L.str.478.L.str.19378.L.str.9378.L.str.18378.L.str.8378.L.str.17378.L.str.7378.L.str.16378.L.str.6378.L.str.15378.L.str.5378.L.str.14378.L.str.4378.L.str.13378.L.str.3378.L.str.12378.L.str.2378.L.str.11378.L.str.1378.L.str.10378.L.str.378.L.str.19278.L.str.9278.L.str.18278.L.str.8278.L.str.17278.L.str.7278.L.str.16278.L.str.6278.L.str.15278.L.str.5278.L.str.14278.L.str.4278.L.str.13278.L.str.3278.L.str.12278.L.str.2278.L.str.11278.L.str.1278.L.str.10278.L.str.278.L.str.19178.L.str.9178.L.str.18178.L.str.8178.L.str.17178.L.str.7178.L.str.16178.L.str.6178.L.str.15178.L.str.5178.L.str.14178.L.str.4178.L.str.13178.L.str.3178.L.str.12178.L.str.2178.L.str.11178.L.str.1178.L.str.10178.L.str.178.L.str.19078.L.str.9078.L.str.18078.L.str.8078.L.str.17078.L.str.7078.L.str.16078.L.str.6078.L.str.15078.L.str.5078.L.str.14078.L.str.4078.L.str.13078.L.str.3078.L.str.12078.L.str.2078.L.str.11078.L.str.1078.L.str.10078.L.str.78.L.str.9968.L.str.18968.L.str.8968.L.str.17968.L.str.7968.L.str.16968.L.str.6968.L.str.15968.L.str.5968.L.str.14968.L.str.4968.L.str.13968.L.str.3968.L.str.12968.L.str.2968.L.str.11968.L.str.1968.L.str.10968.L.str.968.L.str.19868.L.str.9868.L.str.18868.L.str.8868.L.str.17868.L.str.7868.L.str.16868.L.str.6868.L.str.15868.L.str.5868.L.str.14868.L.str.4868.L.str.13868.L.str.3868.L.str.12868.L.str.2868.L.str.11868.L.str.1868.L.str.10868.L.str.868.L.str.19768.L.str.9768.L.str.18768.L.str.8768.L.str.17768.L.str.7768.L.str.16768.L.str.6768.L.str.15768.L.str.5768.L.str.14768.L.str.4768.L.str.13768.L.str.3768.L.str.12768.L.str.2768.L.str.11768.L.str.1768.L.str.10768.L.str.768.L.str.19668.L.str.9668.L.str.18668.L.str.8668.L.str.17668.L.str.7668.L.str.16668.L.str.6668.L.str.15668.L.str.5668.L.str.14668.L.str.4668.L.str.13668.L.str.3668.L.str.12668.L.str.2668.L.str.11668.L.str.1668.L.str.10668.L.str.668.L.str.19568.L.str.9568.L.str.18568.L.str.8568.L.str.17568.L.str.7568.L.str.16568.L.str.6568.L.str.15568.L.str.5568.L.str.14568.L.str.4568.L.str.13568.L.str.3568.L.str.12568.L.str.2568.L.str.11568.L.str.1568.L.str.10568.L.str.568.L.str.19468.L.str.9468.L.str.18468.L.str.8468.L.str.17468.L.str.7468.L.str.16468.L.str.6468.L.str.15468.L.str.5468.L.str.14468.L.str.4468.L.str.13468.L.str.3468.L.str.12468.L.str.2468.L.str.11468.L.str.1468.L.str.10468.L.str.468.L.str.19368.L.str.9368.L.str.18368.L.str.8368.L.str.17368.L.str.7368.L.str.16368.L.str.6368.L.str.15368.L.str.5368.L.str.14368.L.str.4368.L.str.13368.L.str.3368.L.str.12368.L.str.2368.L.str.11368.L.str.1368.L.str.10368.L.str.368.L.str.19268.L.str.9268.L.str.18268.L.str.8268.L.str.17268.L.str.7268.L.str.16268.L.str.6268.L.str.15268.L.str.5268.L.str.14268.L.str.4268.L.str.13268.L.str.3268.L.str.12268.L.str.2268.L.str.11268.L.str.1268.L.str.10268.L.str.268.L.str.19168.L.str.9168.L.str.18168.L.str.8168.L.str.17168.L.str.7168.L.str.16168.L.str.6168.L.str.15168.L.str.5168.L.str.14168.L.str.4168.L.str.13168.L.str.3168.L.str.12168.L.str.2168.L.str.11168.L.str.1168.L.str.10168.L.str.168.L.str.19068.L.str.9068.L.str.18068.L.str.8068.L.str.17068.L.str.7068.L.str.16068.L.str.6068.L.str.15068.L.str.5068.L.str.14068.L.str.4068.L.str.13068.L.str.3068.L.str.12068.L.str.2068.L.str.11068.L.str.1068.L.str.10068.L.str.68.L.str.9958.L.str.18958.L.str.8958.L.str.17958.L.str.7958.L.str.16958.L.str.6958.L.str.15958.L.str.5958.L.str.14958.L.str.4958.L.str.13958.L.str.3958.L.str.12958.L.str.2958.L.str.11958.L.str.1958.L.str.10958.L.str.958.L.str.19858.L.str.9858.L.str.18858.L.str.8858.L.str.17858.L.str.7858.L.str.16858.L.str.6858.L.str.15858.L.str.5858.L.str.14858.L.str.4858.L.str.13858.L.str.3858.L.str.12858.L.str.2858.L.str.11858.L.str.1858.L.str.10858.L.str.858.L.str.19758.L.str.9758.L.str.18758.L.str.8758.L.str.17758.L.str.7758.L.str.16758.L.str.6758.L.str.15758.L.str.5758.L.str.14758.L.str.4758.L.str.13758.L.str.3758.L.str.12758.L.str.2758.L.str.11758.L.str.1758.L.str.10758.L.str.758.L.str.19658.L.str.9658.L.str.18658.L.str.8658.L.str.17658.L.str.7658.L.str.16658.L.str.6658.L.str.15658.L.str.5658.L.str.14658.L.str.4658.L.str.13658.L.str.3658.L.str.12658.L.str.2658.L.str.11658.L.str.1658.L.str.10658.L.str.658.L.str.19558.L.str.9558.L.str.18558.L.str.8558.L.str.17558.L.str.7558.L.str.16558.L.str.6558.L.str.15558.L.str.5558.L.str.14558.L.str.4558.L.str.13558.L.str.3558.L.str.12558.L.str.2558.L.str.11558.L.str.1558.L.str.10558.L.str.558.L.str.19458.L.str.9458.L.str.18458.L.str.8458.L.str.17458.L.str.7458.L.str.16458.L.str.6458.L.str.15458.L.str.5458.L.str.14458.L.str.4458.L.str.13458.L.str.3458.L.str.12458.L.str.2458.L.str.11458.L.str.1458.L.str.10458.L.str.458.L.str.19358.L.str.9358.L.str.18358.L.str.8358.L.str.17358.L.str.7358.L.str.16358.L.str.6358.L.str.15358.L.str.5358.L.str.14358.L.str.4358.L.str.13358.L.str.3358.L.str.12358.L.str.2358.L.str.11358.L.str.1358.L.str.10358.L.str.358.L.str.19258.L.str.9258.L.str.18258.L.str.8258.L.str.17258.L.str.7258.L.str.16258.L.str.6258.L.str.15258.L.str.5258.L.str.14258.L.str.4258.L.str.13258.L.str.3258.L.str.12258.L.str.2258.L.str.11258.L.str.1258.L.str.10258.L.str.258.L.str.19158.L.str.9158.L.str.18158.L.str.8158.L.str.17158.L.str.7158.L.str.16158.L.str.6158.L.str.15158.L.str.5158.L.str.14158.L.str.4158.L.str.13158.L.str.3158.L.str.12158.L.str.2158.L.str.11158.L.str.1158.L.str.10158.L.str.158.L.str.19058.L.str.9058.L.str.18058.L.str.8058.L.str.17058.L.str.7058.L.str.16058.L.str.6058.L.str.15058.L.str.5058.L.str.14058.L.str.4058.L.str.13058.L.str.3058.L.str.12058.L.str.2058.L.str.11058.L.str.1058.L.str.10058.L.str.58.L.str.9948.L.str.18948.L.str.8948.L.str.17948.L.str.7948.L.str.16948.L.str.6948.L.str.15948.L.str.5948.L.str.14948.L.str.4948.L.str.13948.L.str.3948.L.str.12948.L.str.2948.L.str.11948.L.str.1948.L.str.10948.L.str.948.L.str.19848.L.str.9848.L.str.18848.L.str.8848.L.str.17848.L.str.7848.L.str.16848.L.str.6848.L.str.15848.L.str.5848.L.str.14848.L.str.4848.L.str.13848.L.str.3848.L.str.12848.L.str.2848.L.str.11848.L.str.1848.L.str.10848.L.str.848.L.str.19748.L.str.9748.L.str.18748.L.str.8748.L.str.17748.L.str.7748.L.str.16748.L.str.6748.L.str.15748.L.str.5748.L.str.14748.L.str.4748.L.str.13748.L.str.3748.L.str.12748.L.str.2748.L.str.11748.L.str.1748.L.str.10748.L.str.748.L.str.19648.L.str.9648.L.str.18648.L.str.8648.L.str.17648.L.str.7648.L.str.16648.L.str.6648.L.str.15648.L.str.5648.L.str.14648.L.str.4648.L.str.13648.L.str.3648.L.str.12648.L.str.2648.L.str.11648.L.str.1648.L.str.10648.L.str.648.L.str.19548.L.str.9548.L.str.18548.L.str.8548.L.str.17548.L.str.7548.L.str.16548.L.str.6548.L.str.15548.L.str.5548.L.str.14548.L.str.4548.L.str.13548.L.str.3548.L.str.12548.L.str.2548.L.str.11548.L.str.1548.L.str.10548.L.str.548.L.str.19448.L.str.9448.L.str.18448.L.str.8448.L.str.17448.L.str.7448.L.str.16448.L.str.6448.L.str.15448.L.str.5448.L.str.14448.L.str.4448.L.str.13448.L.str.3448.L.str.12448.L.str.2448.L.str.11448.L.str.1448.L.str.10448.L.str.448.L.str.19348.L.str.9348.L.str.18348.L.str.8348.L.str.17348.L.str.7348.L.str.16348.L.str.6348.L.str.15348.L.str.5348.L.str.14348.L.str.4348.L.str.13348.L.str.3348.L.str.12348.L.str.2348.L.str.11348.L.str.1348.L.str.10348.L.str.348.L.str.19248.L.str.9248.L.str.18248.L.str.8248.L.str.17248.L.str.7248.L.str.16248.L.str.6248.L.str.15248.L.str.5248.L.str.14248.L.str.4248.L.str.13248.L.str.3248.L.str.12248.L.str.2248.L.str.11248.L.str.1248.L.str.10248.L.str.248.L.str.19148.L.str.9148.L.str.18148.L.str.8148.L.str.17148.L.str.7148.L.str.16148.L.str.6148.L.str.15148.L.str.5148.L.str.14148.L.str.4148.L.str.13148.L.str.3148.L.str.12148.L.str.2148.L.str.11148.L.str.1148.L.str.10148.L.str.148.L.str.19048.L.str.9048.L.str.18048.L.str.8048.L.str.17048.L.str.7048.L.str.16048.L.str.6048.L.str.15048.L.str.5048.L.str.14048.L.str.4048.L.str.13048.L.str.3048.L.str.12048.L.str.2048.L.str.11048.L.str.1048.L.str.10048.L.str.48.L.str.9938.L.str.18938.L.str.8938.L.str.17938.L.str.7938.L.str.16938.L.str.6938.L.str.15938.L.str.5938.L.str.14938.L.str.4938.L.str.13938.L.str.3938.L.str.12938.L.str.2938.L.str.11938.L.str.1938.L.str.10938.L.str.938.L.str.19838.L.str.9838.L.str.18838.L.str.8838.L.str.17838.L.str.7838.L.str.16838.L.str.6838.L.str.15838.L.str.5838.L.str.14838.L.str.4838.L.str.13838.L.str.3838.L.str.12838.L.str.2838.L.str.11838.L.str.1838.L.str.10838.L.str.838.L.str.19738.L.str.9738.L.str.18738.L.str.8738.L.str.17738.L.str.7738.L.str.16738.L.str.6738.L.str.15738.L.str.5738.L.str.14738.L.str.4738.L.str.13738.L.str.3738.L.str.12738.L.str.2738.L.str.11738.L.str.1738.L.str.10738.L.str.738.L.str.19638.L.str.9638.L.str.18638.L.str.8638.L.str.17638.L.str.7638.L.str.16638.L.str.6638.L.str.15638.L.str.5638.L.str.14638.L.str.4638.L.str.13638.L.str.3638.L.str.12638.L.str.2638.L.str.11638.L.str.1638.L.str.10638.L.str.638.L.str.19538.L.str.9538.L.str.18538.L.str.8538.L.str.17538.L.str.7538.L.str.16538.L.str.6538.L.str.15538.L.str.5538.L.str.14538.L.str.4538.L.str.13538.L.str.3538.L.str.12538.L.str.2538.L.str.11538.L.str.1538.L.str.10538.L.str.538.L.str.19438.L.str.9438.L.str.18438.L.str.8438.L.str.17438.L.str.7438.L.str.16438.L.str.6438.L.str.15438.L.str.5438.L.str.14438.L.str.4438.L.str.13438.L.str.3438.L.str.12438.L.str.2438.L.str.11438.L.str.1438.L.str.10438.L.str.438.L.str.19338.L.str.9338.L.str.18338.L.str.8338.L.str.17338.L.str.7338.L.str.16338.L.str.6338.L.str.15338.L.str.5338.L.str.14338.L.str.4338.L.str.13338.L.str.3338.L.str.12338.L.str.2338.L.str.11338.L.str.1338.L.str.10338.L.str.338.L.str.19238.L.str.9238.L.str.18238.L.str.8238.L.str.17238.L.str.7238.L.str.16238.L.str.6238.L.str.15238.L.str.5238.L.str.14238.L.str.4238.L.str.13238.L.str.3238.L.str.12238.L.str.2238.L.str.11238.L.str.1238.L.str.10238.L.str.238.L.str.19138.L.str.9138.L.str.18138.L.str.8138.L.str.17138.L.str.7138.L.str.16138.L.str.6138.L.str.15138.L.str.5138.L.str.14138.L.str.4138.L.str.13138.L.str.3138.L.str.12138.L.str.2138.L.str.11138.L.str.1138.L.str.10138.L.str.138.L.str.19038.L.str.9038.L.str.18038.L.str.8038.L.str.17038.L.str.7038.L.str.16038.L.str.6038.L.str.15038.L.str.5038.L.str.14038.L.str.4038.L.str.13038.L.str.3038.L.str.12038.L.str.2038.L.str.11038.L.str.1038.L.str.10038.L.str.38.L.str.9928.L.str.18928.L.str.8928.L.str.17928.L.str.7928.L.str.16928.L.str.6928.L.str.15928.L.str.5928.L.str.14928.L.str.4928.L.str.13928.L.str.3928.L.str.12928.L.str.2928.L.str.11928.L.str.1928.L.str.10928.L.str.928.L.str.19828.L.str.9828.L.str.18828.L.str.8828.L.str.17828.L.str.7828.L.str.16828.L.str.6828.L.str.15828.L.str.5828.L.str.14828.L.str.4828.L.str.13828.L.str.3828.L.str.12828.L.str.2828.L.str.11828.L.str.1828.L.str.10828.L.str.828.L.str.19728.L.str.9728.L.str.18728.L.str.8728.L.str.17728.L.str.7728.L.str.16728.L.str.6728.L.str.15728.L.str.5728.L.str.14728.L.str.4728.L.str.13728.L.str.3728.L.str.12728.L.str.2728.L.str.11728.L.str.1728.L.str.10728.L.str.728.L.str.19628.L.str.9628.L.str.18628.L.str.8628.L.str.17628.L.str.7628.L.str.16628.L.str.6628.L.str.15628.L.str.5628.L.str.14628.L.str.4628.L.str.13628.L.str.3628.L.str.12628.L.str.2628.L.str.11628.L.str.1628.L.str.10628.L.str.628.L.str.19528.L.str.9528.L.str.18528.L.str.8528.L.str.17528.L.str.7528.L.str.16528.L.str.6528.L.str.15528.L.str.5528.L.str.14528.L.str.4528.L.str.13528.L.str.3528.L.str.12528.L.str.2528.L.str.11528.L.str.1528.L.str.10528.L.str.528.L.str.19428.L.str.9428.L.str.18428.L.str.8428.L.str.17428.L.str.7428.L.str.16428.L.str.6428.L.str.15428.L.str.5428.L.str.14428.L.str.4428.L.str.13428.L.str.3428.L.str.12428.L.str.2428.L.str.11428.L.str.1428.L.str.10428.L.str.428.L.str.19328.L.str.9328.L.str.18328.L.str.8328.L.str.17328.L.str.7328.L.str.16328.L.str.6328.L.str.15328.L.str.5328.L.str.14328.L.str.4328.L.str.13328.L.str.3328.L.str.12328.L.str.2328.L.str.11328.L.str.1328.L.str.10328.L.str.328.L.str.19228.L.str.9228.L.str.18228.L.str.8228.L.str.17228.L.str.7228.L.str.16228.L.str.6228.L.str.15228.L.str.5228.L.str.14228.L.str.4228.L.str.13228.L.str.3228.L.str.12228.L.str.2228.L.str.11228.L.str.1228.L.str.10228.L.str.228.L.str.19128.L.str.9128.L.str.18128.L.str.8128.L.str.17128.L.str.7128.L.str.16128.L.str.6128.L.str.15128.L.str.5128.L.str.14128.L.str.4128.L.str.13128.L.str.3128.L.str.12128.L.str.2128.L.str.11128.L.str.1128.L.str.10128.L.str.128.L.str.19028.L.str.9028.L.str.18028.L.str.8028.L.str.17028.L.str.7028.L.str.16028.L.str.6028.L.str.15028.L.str.5028.L.str.14028.L.str.4028.L.str.13028.L.str.3028.L.str.12028.L.str.2028.L.str.11028.L.str.1028.L.str.10028.L.str.28.L.str.9918.L.str.18918.L.str.8918.L.str.17918.L.str.7918.L.str.16918.L.str.6918.L.str.15918.L.str.5918.L.str.14918.L.str.4918.L.str.13918.L.str.3918.L.str.12918.L.str.2918.L.str.11918.L.str.1918.L.str.10918.L.str.918.L.str.19818.L.str.9818.L.str.18818.L.str.8818.L.str.17818.L.str.7818.L.str.16818.L.str.6818.L.str.15818.L.str.5818.L.str.14818.L.str.4818.L.str.13818.L.str.3818.L.str.12818.L.str.2818.L.str.11818.L.str.1818.L.str.10818.L.str.818.L.str.19718.L.str.9718.L.str.18718.L.str.8718.L.str.17718.L.str.7718.L.str.16718.L.str.6718.L.str.15718.L.str.5718.L.str.14718.L.str.4718.L.str.13718.L.str.3718.L.str.12718.L.str.2718.L.str.11718.L.str.1718.L.str.10718.L.str.718.L.str.19618.L.str.9618.L.str.18618.L.str.8618.L.str.17618.L.str.7618.L.str.16618.L.str.6618.L.str.15618.L.str.5618.L.str.14618.L.str.4618.L.str.13618.L.str.3618.L.str.12618.L.str.2618.L.str.11618.L.str.1618.L.str.10618.L.str.618.L.str.19518.L.str.9518.L.str.18518.L.str.8518.L.str.17518.L.str.7518.L.str.16518.L.str.6518.L.str.15518.L.str.5518.L.str.14518.L.str.4518.L.str.13518.L.str.3518.L.str.12518.L.str.2518.L.str.11518.L.str.1518.L.str.10518.L.str.518.L.str.19418.L.str.9418.L.str.18418.L.str.8418.L.str.17418.L.str.7418.L.str.16418.L.str.6418.L.str.15418.L.str.5418.L.str.14418.L.str.4418.L.str.13418.L.str.3418.L.str.12418.L.str.2418.L.str.11418.L.str.1418.L.str.10418.L.str.418.L.str.19318.L.str.9318.L.str.18318.L.str.8318.L.str.17318.L.str.7318.L.str.16318.L.str.6318.L.str.15318.L.str.5318.L.str.14318.L.str.4318.L.str.13318.L.str.3318.L.str.12318.L.str.2318.L.str.11318.L.str.1318.L.str.10318.L.str.318.L.str.19218.L.str.9218.L.str.18218.L.str.8218.L.str.17218.L.str.7218.L.str.16218.L.str.6218.L.str.15218.L.str.5218.L.str.14218.L.str.4218.L.str.13218.L.str.3218.L.str.12218.L.str.2218.L.str.11218.L.str.1218.L.str.10218.L.str.218.L.str.19118.L.str.9118.L.str.18118.L.str.8118.L.str.17118.L.str.7118.L.str.16118.L.str.6118.L.str.15118.L.str.5118.L.str.14118.L.str.4118.L.str.13118.L.str.3118.L.str.12118.L.str.2118.L.str.11118.L.str.1118.L.str.10118.L.str.118.L.str.19018.L.str.9018.L.str.18018.L.str.8018.L.str.17018.L.str.7018.L.str.16018.L.str.6018.L.str.15018.L.str.5018.L.str.14018.L.str.4018.L.str.13018.L.str.3018.L.str.12018.L.str.2018.L.str.11018.L.str.1018.L.str.10018.L.str.18.L.str.9908.L.str.18908.L.str.8908.L.str.17908.L.str.7908.L.str.16908.L.str.6908.L.str.15908.L.str.5908.L.str.14908.L.str.4908.L.str.13908.L.str.3908.L.str.12908.L.str.2908.L.str.11908.L.str.1908.L.str.10908.L.str.908.L.str.19808.L.str.9808.L.str.18808.L.str.8808.L.str.17808.L.str.7808.L.str.16808.L.str.6808.L.str.15808.L.str.5808.L.str.14808.L.str.4808.L.str.13808.L.str.3808.L.str.12808.L.str.2808.L.str.11808.L.str.1808.L.str.10808.L.str.808.L.str.19708.L.str.9708.L.str.18708.L.str.8708.L.str.17708.L.str.7708.L.str.16708.L.str.6708.L.str.15708.L.str.5708.L.str.14708.L.str.4708.L.str.13708.L.str.3708.L.str.12708.L.str.2708.L.str.11708.L.str.1708.L.str.10708.L.str.708.L.str.19608.L.str.9608.L.str.18608.L.str.8608.L.str.17608.L.str.7608.L.str.16608.L.str.6608.L.str.15608.L.str.5608.L.str.14608.L.str.4608.L.str.13608.L.str.3608.L.str.12608.L.str.2608.L.str.11608.L.str.1608.L.str.10608.L.str.608.L.str.19508.L.str.9508.L.str.18508.L.str.8508.L.str.17508.L.str.7508.L.str.16508.L.str.6508.L.str.15508.L.str.5508.L.str.14508.L.str.4508.L.str.13508.L.str.3508.L.str.12508.L.str.2508.L.str.11508.L.str.1508.L.str.10508.L.str.508.L.str.19408.L.str.9408.L.str.18408.L.str.8408.L.str.17408.L.str.7408.L.str.16408.L.str.6408.L.str.15408.L.str.5408.L.str.14408.L.str.4408.L.str.13408.L.str.3408.L.str.12408.L.str.2408.L.str.11408.L.str.1408.L.str.10408.L.str.408.L.str.19308.L.str.9308.L.str.18308.L.str.8308.L.str.17308.L.str.7308.L.str.16308.L.str.6308.L.str.15308.L.str.5308.L.str.14308.L.str.4308.L.str.13308.L.str.3308.L.str.12308.L.str.2308.L.str.11308.L.str.1308.L.str.10308.L.str.308.L.str.19208.L.str.9208.L.str.18208.L.str.8208.L.str.17208.L.str.7208.L.str.16208.L.str.6208.L.str.15208.L.str.5208.L.str.14208.L.str.4208.L.str.13208.L.str.3208.L.str.12208.L.str.2208.L.str.11208.L.str.1208.L.str.10208.L.str.208.L.str.19108.L.str.9108.L.str.18108.L.str.8108.L.str.17108.L.str.7108.L.str.16108.L.str.6108.L.str.15108.L.str.5108.L.str.14108.L.str.4108.L.str.13108.L.str.3108.L.str.12108.L.str.2108.L.str.11108.L.str.1108.L.str.10108.L.str.108.L.str.19008.L.str.9008.L.str.18008.L.str.8008.L.str.17008.L.str.7008.L.str.16008.L.str.6008.L.str.15008.L.str.5008.L.str.14008.L.str.4008.L.str.13008.L.str.3008.L.str.12008.L.str.2008.L.str.11008.L.str.1008.L.str.10008.L.str.8.L.str.9997.L.str.18997.L.str.8997.L.str.17997.L.str.7997.L.str.16997.L.str.6997.L.str.15997.L.str.5997.L.str.14997.L.str.4997.L.str.13997.L.str.3997.L.str.12997.L.str.2997.L.str.11997.L.str.1997.L.str.10997.L.str.997.L.str.9897.L.str.18897.L.str.8897.L.str.17897.L.str.7897.L.str.16897.L.str.6897.L.str.15897.L.str.5897.L.str.14897.L.str.4897.L.str.13897.L.str.3897.L.str.12897.L.str.2897.L.str.11897.L.str.1897.L.str.10897.L.str.897.L.str.19797.L.str.9797.L.str.18797.L.str.8797.L.str.17797.L.str.7797.L.str.16797.L.str.6797.L.str.15797.L.str.5797.L.str.14797.L.str.4797.L.str.13797.L.str.3797.L.str.12797.L.str.2797.L.str.11797.L.str.1797.L.str.10797.L.str.797.L.str.19697.L.str.9697.L.str.18697.L.str.8697.L.str.17697.L.str.7697.L.str.16697.L.str.6697.L.str.15697.L.str.5697.L.str.14697.L.str.4697.L.str.13697.L.str.3697.L.str.12697.L.str.2697.L.str.11697.L.str.1697.L.str.10697.L.str.697.L.str.19597.L.str.9597.L.str.18597.L.str.8597.L.str.17597.L.str.7597.L.str.16597.L.str.6597.L.str.15597.L.str.5597.L.str.14597.L.str.4597.L.str.13597.L.str.3597.L.str.12597.L.str.2597.L.str.11597.L.str.1597.L.str.10597.L.str.597.L.str.19497.L.str.9497.L.str.18497.L.str.8497.L.str.17497.L.str.7497.L.str.16497.L.str.6497.L.str.15497.L.str.5497.L.str.14497.L.str.4497.L.str.13497.L.str.3497.L.str.12497.L.str.2497.L.str.11497.L.str.1497.L.str.10497.L.str.497.L.str.19397.L.str.9397.L.str.18397.L.str.8397.L.str.17397.L.str.7397.L.str.16397.L.str.6397.L.str.15397.L.str.5397.L.str.14397.L.str.4397.L.str.13397.L.str.3397.L.str.12397.L.str.2397.L.str.11397.L.str.1397.L.str.10397.L.str.397.L.str.19297.L.str.9297.L.str.18297.L.str.8297.L.str.17297.L.str.7297.L.str.16297.L.str.6297.L.str.15297.L.str.5297.L.str.14297.L.str.4297.L.str.13297.L.str.3297.L.str.12297.L.str.2297.L.str.11297.L.str.1297.L.str.10297.L.str.297.L.str.19197.L.str.9197.L.str.18197.L.str.8197.L.str.17197.L.str.7197.L.str.16197.L.str.6197.L.str.15197.L.str.5197.L.str.14197.L.str.4197.L.str.13197.L.str.3197.L.str.12197.L.str.2197.L.str.11197.L.str.1197.L.str.10197.L.str.197.L.str.19097.L.str.9097.L.str.18097.L.str.8097.L.str.17097.L.str.7097.L.str.16097.L.str.6097.L.str.15097.L.str.5097.L.str.14097.L.str.4097.L.str.13097.L.str.3097.L.str.12097.L.str.2097.L.str.11097.L.str.1097.L.str.10097.L.str.97.L.str.9987.L.str.18987.L.str.8987.L.str.17987.L.str.7987.L.str.16987.L.str.6987.L.str.15987.L.str.5987.L.str.14987.L.str.4987.L.str.13987.L.str.3987.L.str.12987.L.str.2987.L.str.11987.L.str.1987.L.str.10987.L.str.987.L.str.9887.L.str.18887.L.str.8887.L.str.17887.L.str.7887.L.str.16887.L.str.6887.L.str.15887.L.str.5887.L.str.14887.L.str.4887.L.str.13887.L.str.3887.L.str.12887.L.str.2887.L.str.11887.L.str.1887.L.str.10887.L.str.887.L.str.19787.L.str.9787.L.str.18787.L.str.8787.L.str.17787.L.str.7787.L.str.16787.L.str.6787.L.str.15787.L.str.5787.L.str.14787.L.str.4787.L.str.13787.L.str.3787.L.str.12787.L.str.2787.L.str.11787.L.str.1787.L.str.10787.L.str.787.L.str.19687.L.str.9687.L.str.18687.L.str.8687.L.str.17687.L.str.7687.L.str.16687.L.str.6687.L.str.15687.L.str.5687.L.str.14687.L.str.4687.L.str.13687.L.str.3687.L.str.12687.L.str.2687.L.str.11687.L.str.1687.L.str.10687.L.str.687.L.str.19587.L.str.9587.L.str.18587.L.str.8587.L.str.17587.L.str.7587.L.str.16587.L.str.6587.L.str.15587.L.str.5587.L.str.14587.L.str.4587.L.str.13587.L.str.3587.L.str.12587.L.str.2587.L.str.11587.L.str.1587.L.str.10587.L.str.587.L.str.19487.L.str.9487.L.str.18487.L.str.8487.L.str.17487.L.str.7487.L.str.16487.L.str.6487.L.str.15487.L.str.5487.L.str.14487.L.str.4487.L.str.13487.L.str.3487.L.str.12487.L.str.2487.L.str.11487.L.str.1487.L.str.10487.L.str.487.L.str.19387.L.str.9387.L.str.18387.L.str.8387.L.str.17387.L.str.7387.L.str.16387.L.str.6387.L.str.15387.L.str.5387.L.str.14387.L.str.4387.L.str.13387.L.str.3387.L.str.12387.L.str.2387.L.str.11387.L.str.1387.L.str.10387.L.str.387.L.str.19287.L.str.9287.L.str.18287.L.str.8287.L.str.17287.L.str.7287.L.str.16287.L.str.6287.L.str.15287.L.str.5287.L.str.14287.L.str.4287.L.str.13287.L.str.3287.L.str.12287.L.str.2287.L.str.11287.L.str.1287.L.str.10287.L.str.287.L.str.19187.L.str.9187.L.str.18187.L.str.8187.L.str.17187.L.str.7187.L.str.16187.L.str.6187.L.str.15187.L.str.5187.L.str.14187.L.str.4187.L.str.13187.L.str.3187.L.str.12187.L.str.2187.L.str.11187.L.str.1187.L.str.10187.L.str.187.L.str.19087.L.str.9087.L.str.18087.L.str.8087.L.str.17087.L.str.7087.L.str.16087.L.str.6087.L.str.15087.L.str.5087.L.str.14087.L.str.4087.L.str.13087.L.str.3087.L.str.12087.L.str.2087.L.str.11087.L.str.1087.L.str.10087.L.str.87.L.str.9977.L.str.18977.L.str.8977.L.str.17977.L.str.7977.L.str.16977.L.str.6977.L.str.15977.L.str.5977.L.str.14977.L.str.4977.L.str.13977.L.str.3977.L.str.12977.L.str.2977.L.str.11977.L.str.1977.L.str.10977.L.str.977.L.str.9877.L.str.18877.L.str.8877.L.str.17877.L.str.7877.L.str.16877.L.str.6877.L.str.15877.L.str.5877.L.str.14877.L.str.4877.L.str.13877.L.str.3877.L.str.12877.L.str.2877.L.str.11877.L.str.1877.L.str.10877.L.str.877.L.str.19777.L.str.9777.L.str.18777.L.str.8777.L.str.17777.L.str.7777.L.str.16777.L.str.6777.L.str.15777.L.str.5777.L.str.14777.L.str.4777.L.str.13777.L.str.3777.L.str.12777.L.str.2777.L.str.11777.L.str.1777.L.str.10777.L.str.777.L.str.19677.L.str.9677.L.str.18677.L.str.8677.L.str.17677.L.str.7677.L.str.16677.L.str.6677.L.str.15677.L.str.5677.L.str.14677.L.str.4677.L.str.13677.L.str.3677.L.str.12677.L.str.2677.L.str.11677.L.str.1677.L.str.10677.L.str.677.L.str.19577.L.str.9577.L.str.18577.L.str.8577.L.str.17577.L.str.7577.L.str.16577.L.str.6577.L.str.15577.L.str.5577.L.str.14577.L.str.4577.L.str.13577.L.str.3577.L.str.12577.L.str.2577.L.str.11577.L.str.1577.L.str.10577.L.str.577.L.str.19477.L.str.9477.L.str.18477.L.str.8477.L.str.17477.L.str.7477.L.str.16477.L.str.6477.L.str.15477.L.str.5477.L.str.14477.L.str.4477.L.str.13477.L.str.3477.L.str.12477.L.str.2477.L.str.11477.L.str.1477.L.str.10477.L.str.477.L.str.19377.L.str.9377.L.str.18377.L.str.8377.L.str.17377.L.str.7377.L.str.16377.L.str.6377.L.str.15377.L.str.5377.L.str.14377.L.str.4377.L.str.13377.L.str.3377.L.str.12377.L.str.2377.L.str.11377.L.str.1377.L.str.10377.L.str.377.L.str.19277.L.str.9277.L.str.18277.L.str.8277.L.str.17277.L.str.7277.L.str.16277.L.str.6277.L.str.15277.L.str.5277.L.str.14277.L.str.4277.L.str.13277.L.str.3277.L.str.12277.L.str.2277.L.str.11277.L.str.1277.L.str.10277.L.str.277.L.str.19177.L.str.9177.L.str.18177.L.str.8177.L.str.17177.L.str.7177.L.str.16177.L.str.6177.L.str.15177.L.str.5177.L.str.14177.L.str.4177.L.str.13177.L.str.3177.L.str.12177.L.str.2177.L.str.11177.L.str.1177.L.str.10177.L.str.177.L.str.19077.L.str.9077.L.str.18077.L.str.8077.L.str.17077.L.str.7077.L.str.16077.L.str.6077.L.str.15077.L.str.5077.L.str.14077.L.str.4077.L.str.13077.L.str.3077.L.str.12077.L.str.2077.L.str.11077.L.str.1077.L.str.10077.L.str.77.L.str.9967.L.str.18967.L.str.8967.L.str.17967.L.str.7967.L.str.16967.L.str.6967.L.str.15967.L.str.5967.L.str.14967.L.str.4967.L.str.13967.L.str.3967.L.str.12967.L.str.2967.L.str.11967.L.str.1967.L.str.10967.L.str.967.L.str.19867.L.str.9867.L.str.18867.L.str.8867.L.str.17867.L.str.7867.L.str.16867.L.str.6867.L.str.15867.L.str.5867.L.str.14867.L.str.4867.L.str.13867.L.str.3867.L.str.12867.L.str.2867.L.str.11867.L.str.1867.L.str.10867.L.str.867.L.str.19767.L.str.9767.L.str.18767.L.str.8767.L.str.17767.L.str.7767.L.str.16767.L.str.6767.L.str.15767.L.str.5767.L.str.14767.L.str.4767.L.str.13767.L.str.3767.L.str.12767.L.str.2767.L.str.11767.L.str.1767.L.str.10767.L.str.767.L.str.19667.L.str.9667.L.str.18667.L.str.8667.L.str.17667.L.str.7667.L.str.16667.L.str.6667.L.str.15667.L.str.5667.L.str.14667.L.str.4667.L.str.13667.L.str.3667.L.str.12667.L.str.2667.L.str.11667.L.str.1667.L.str.10667.L.str.667.L.str.19567.L.str.9567.L.str.18567.L.str.8567.L.str.17567.L.str.7567.L.str.16567.L.str.6567.L.str.15567.L.str.5567.L.str.14567.L.str.4567.L.str.13567.L.str.3567.L.str.12567.L.str.2567.L.str.11567.L.str.1567.L.str.10567.L.str.567.L.str.19467.L.str.9467.L.str.18467.L.str.8467.L.str.17467.L.str.7467.L.str.16467.L.str.6467.L.str.15467.L.str.5467.L.str.14467.L.str.4467.L.str.13467.L.str.3467.L.str.12467.L.str.2467.L.str.11467.L.str.1467.L.str.10467.L.str.467.L.str.19367.L.str.9367.L.str.18367.L.str.8367.L.str.17367.L.str.7367.L.str.16367.L.str.6367.L.str.15367.L.str.5367.L.str.14367.L.str.4367.L.str.13367.L.str.3367.L.str.12367.L.str.2367.L.str.11367.L.str.1367.L.str.10367.L.str.367.L.str.19267.L.str.9267.L.str.18267.L.str.8267.L.str.17267.L.str.7267.L.str.16267.L.str.6267.L.str.15267.L.str.5267.L.str.14267.L.str.4267.L.str.13267.L.str.3267.L.str.12267.L.str.2267.L.str.11267.L.str.1267.L.str.10267.L.str.267.L.str.19167.L.str.9167.L.str.18167.L.str.8167.L.str.17167.L.str.7167.L.str.16167.L.str.6167.L.str.15167.L.str.5167.L.str.14167.L.str.4167.L.str.13167.L.str.3167.L.str.12167.L.str.2167.L.str.11167.L.str.1167.L.str.10167.L.str.167.L.str.19067.L.str.9067.L.str.18067.L.str.8067.L.str.17067.L.str.7067.L.str.16067.L.str.6067.L.str.15067.L.str.5067.L.str.14067.L.str.4067.L.str.13067.L.str.3067.L.str.12067.L.str.2067.L.str.11067.L.str.1067.L.str.10067.L.str.67.L.str.9957.L.str.18957.L.str.8957.L.str.17957.L.str.7957.L.str.16957.L.str.6957.L.str.15957.L.str.5957.L.str.14957.L.str.4957.L.str.13957.L.str.3957.L.str.12957.L.str.2957.L.str.11957.L.str.1957.L.str.10957.L.str.957.L.str.19857.L.str.9857.L.str.18857.L.str.8857.L.str.17857.L.str.7857.L.str.16857.L.str.6857.L.str.15857.L.str.5857.L.str.14857.L.str.4857.L.str.13857.L.str.3857.L.str.12857.L.str.2857.L.str.11857.L.str.1857.L.str.10857.L.str.857.L.str.19757.L.str.9757.L.str.18757.L.str.8757.L.str.17757.L.str.7757.L.str.16757.L.str.6757.L.str.15757.L.str.5757.L.str.14757.L.str.4757.L.str.13757.L.str.3757.L.str.12757.L.str.2757.L.str.11757.L.str.1757.L.str.10757.L.str.757.L.str.19657.L.str.9657.L.str.18657.L.str.8657.L.str.17657.L.str.7657.L.str.16657.L.str.6657.L.str.15657.L.str.5657.L.str.14657.L.str.4657.L.str.13657.L.str.3657.L.str.12657.L.str.2657.L.str.11657.L.str.1657.L.str.10657.L.str.657.L.str.19557.L.str.9557.L.str.18557.L.str.8557.L.str.17557.L.str.7557.L.str.16557.L.str.6557.L.str.15557.L.str.5557.L.str.14557.L.str.4557.L.str.13557.L.str.3557.L.str.12557.L.str.2557.L.str.11557.L.str.1557.L.str.10557.L.str.557.L.str.19457.L.str.9457.L.str.18457.L.str.8457.L.str.17457.L.str.7457.L.str.16457.L.str.6457.L.str.15457.L.str.5457.L.str.14457.L.str.4457.L.str.13457.L.str.3457.L.str.12457.L.str.2457.L.str.11457.L.str.1457.L.str.10457.L.str.457.L.str.19357.L.str.9357.L.str.18357.L.str.8357.L.str.17357.L.str.7357.L.str.16357.L.str.6357.L.str.15357.L.str.5357.L.str.14357.L.str.4357.L.str.13357.L.str.3357.L.str.12357.L.str.2357.L.str.11357.L.str.1357.L.str.10357.L.str.357.L.str.19257.L.str.9257.L.str.18257.L.str.8257.L.str.17257.L.str.7257.L.str.16257.L.str.6257.L.str.15257.L.str.5257.L.str.14257.L.str.4257.L.str.13257.L.str.3257.L.str.12257.L.str.2257.L.str.11257.L.str.1257.L.str.10257.L.str.257.L.str.19157.L.str.9157.L.str.18157.L.str.8157.L.str.17157.L.str.7157.L.str.16157.L.str.6157.L.str.15157.L.str.5157.L.str.14157.L.str.4157.L.str.13157.L.str.3157.L.str.12157.L.str.2157.L.str.11157.L.str.1157.L.str.10157.L.str.157.L.str.19057.L.str.9057.L.str.18057.L.str.8057.L.str.17057.L.str.7057.L.str.16057.L.str.6057.L.str.15057.L.str.5057.L.str.14057.L.str.4057.L.str.13057.L.str.3057.L.str.12057.L.str.2057.L.str.11057.L.str.1057.L.str.10057.L.str.57.L.str.9947.L.str.18947.L.str.8947.L.str.17947.L.str.7947.L.str.16947.L.str.6947.L.str.15947.L.str.5947.L.str.14947.L.str.4947.L.str.13947.L.str.3947.L.str.12947.L.str.2947.L.str.11947.L.str.1947.L.str.10947.L.str.947.L.str.19847.L.str.9847.L.str.18847.L.str.8847.L.str.17847.L.str.7847.L.str.16847.L.str.6847.L.str.15847.L.str.5847.L.str.14847.L.str.4847.L.str.13847.L.str.3847.L.str.12847.L.str.2847.L.str.11847.L.str.1847.L.str.10847.L.str.847.L.str.19747.L.str.9747.L.str.18747.L.str.8747.L.str.17747.L.str.7747.L.str.16747.L.str.6747.L.str.15747.L.str.5747.L.str.14747.L.str.4747.L.str.13747.L.str.3747.L.str.12747.L.str.2747.L.str.11747.L.str.1747.L.str.10747.L.str.747.L.str.19647.L.str.9647.L.str.18647.L.str.8647.L.str.17647.L.str.7647.L.str.16647.L.str.6647.L.str.15647.L.str.5647.L.str.14647.L.str.4647.L.str.13647.L.str.3647.L.str.12647.L.str.2647.L.str.11647.L.str.1647.L.str.10647.L.str.647.L.str.19547.L.str.9547.L.str.18547.L.str.8547.L.str.17547.L.str.7547.L.str.16547.L.str.6547.L.str.15547.L.str.5547.L.str.14547.L.str.4547.L.str.13547.L.str.3547.L.str.12547.L.str.2547.L.str.11547.L.str.1547.L.str.10547.L.str.547.L.str.19447.L.str.9447.L.str.18447.L.str.8447.L.str.17447.L.str.7447.L.str.16447.L.str.6447.L.str.15447.L.str.5447.L.str.14447.L.str.4447.L.str.13447.L.str.3447.L.str.12447.L.str.2447.L.str.11447.L.str.1447.L.str.10447.L.str.447.L.str.19347.L.str.9347.L.str.18347.L.str.8347.L.str.17347.L.str.7347.L.str.16347.L.str.6347.L.str.15347.L.str.5347.L.str.14347.L.str.4347.L.str.13347.L.str.3347.L.str.12347.L.str.2347.L.str.11347.L.str.1347.L.str.10347.L.str.347.L.str.19247.L.str.9247.L.str.18247.L.str.8247.L.str.17247.L.str.7247.L.str.16247.L.str.6247.L.str.15247.L.str.5247.L.str.14247.L.str.4247.L.str.13247.L.str.3247.L.str.12247.L.str.2247.L.str.11247.L.str.1247.L.str.10247.L.str.247.L.str.19147.L.str.9147.L.str.18147.L.str.8147.L.str.17147.L.str.7147.L.str.16147.L.str.6147.L.str.15147.L.str.5147.L.str.14147.L.str.4147.L.str.13147.L.str.3147.L.str.12147.L.str.2147.L.str.11147.L.str.1147.L.str.10147.L.str.147.L.str.19047.L.str.9047.L.str.18047.L.str.8047.L.str.17047.L.str.7047.L.str.16047.L.str.6047.L.str.15047.L.str.5047.L.str.14047.L.str.4047.L.str.13047.L.str.3047.L.str.12047.L.str.2047.L.str.11047.L.str.1047.L.str.10047.L.str.47.L.str.9937.L.str.18937.L.str.8937.L.str.17937.L.str.7937.L.str.16937.L.str.6937.L.str.15937.L.str.5937.L.str.14937.L.str.4937.L.str.13937.L.str.3937.L.str.12937.L.str.2937.L.str.11937.L.str.1937.L.str.10937.L.str.937.L.str.19837.L.str.9837.L.str.18837.L.str.8837.L.str.17837.L.str.7837.L.str.16837.L.str.6837.L.str.15837.L.str.5837.L.str.14837.L.str.4837.L.str.13837.L.str.3837.L.str.12837.L.str.2837.L.str.11837.L.str.1837.L.str.10837.L.str.837.L.str.19737.L.str.9737.L.str.18737.L.str.8737.L.str.17737.L.str.7737.L.str.16737.L.str.6737.L.str.15737.L.str.5737.L.str.14737.L.str.4737.L.str.13737.L.str.3737.L.str.12737.L.str.2737.L.str.11737.L.str.1737.L.str.10737.L.str.737.L.str.19637.L.str.9637.L.str.18637.L.str.8637.L.str.17637.L.str.7637.L.str.16637.L.str.6637.L.str.15637.L.str.5637.L.str.14637.L.str.4637.L.str.13637.L.str.3637.L.str.12637.L.str.2637.L.str.11637.L.str.1637.L.str.10637.L.str.637.L.str.19537.L.str.9537.L.str.18537.L.str.8537.L.str.17537.L.str.7537.L.str.16537.L.str.6537.L.str.15537.L.str.5537.L.str.14537.L.str.4537.L.str.13537.L.str.3537.L.str.12537.L.str.2537.L.str.11537.L.str.1537.L.str.10537.L.str.537.L.str.19437.L.str.9437.L.str.18437.L.str.8437.L.str.17437.L.str.7437.L.str.16437.L.str.6437.L.str.15437.L.str.5437.L.str.14437.L.str.4437.L.str.13437.L.str.3437.L.str.12437.L.str.2437.L.str.11437.L.str.1437.L.str.10437.L.str.437.L.str.19337.L.str.9337.L.str.18337.L.str.8337.L.str.17337.L.str.7337.L.str.16337.L.str.6337.L.str.15337.L.str.5337.L.str.14337.L.str.4337.L.str.13337.L.str.3337.L.str.12337.L.str.2337.L.str.11337.L.str.1337.L.str.10337.L.str.337.L.str.19237.L.str.9237.L.str.18237.L.str.8237.L.str.17237.L.str.7237.L.str.16237.L.str.6237.L.str.15237.L.str.5237.L.str.14237.L.str.4237.L.str.13237.L.str.3237.L.str.12237.L.str.2237.L.str.11237.L.str.1237.L.str.10237.L.str.237.L.str.19137.L.str.9137.L.str.18137.L.str.8137.L.str.17137.L.str.7137.L.str.16137.L.str.6137.L.str.15137.L.str.5137.L.str.14137.L.str.4137.L.str.13137.L.str.3137.L.str.12137.L.str.2137.L.str.11137.L.str.1137.L.str.10137.L.str.137.L.str.19037.L.str.9037.L.str.18037.L.str.8037.L.str.17037.L.str.7037.L.str.16037.L.str.6037.L.str.15037.L.str.5037.L.str.14037.L.str.4037.L.str.13037.L.str.3037.L.str.12037.L.str.2037.L.str.11037.L.str.1037.L.str.10037.L.str.37.L.str.9927.L.str.18927.L.str.8927.L.str.17927.L.str.7927.L.str.16927.L.str.6927.L.str.15927.L.str.5927.L.str.14927.L.str.4927.L.str.13927.L.str.3927.L.str.12927.L.str.2927.L.str.11927.L.str.1927.L.str.10927.L.str.927.L.str.19827.L.str.9827.L.str.18827.L.str.8827.L.str.17827.L.str.7827.L.str.16827.L.str.6827.L.str.15827.L.str.5827.L.str.14827.L.str.4827.L.str.13827.L.str.3827.L.str.12827.L.str.2827.L.str.11827.L.str.1827.L.str.10827.L.str.827.L.str.19727.L.str.9727.L.str.18727.L.str.8727.L.str.17727.L.str.7727.L.str.16727.L.str.6727.L.str.15727.L.str.5727.L.str.14727.L.str.4727.L.str.13727.L.str.3727.L.str.12727.L.str.2727.L.str.11727.L.str.1727.L.str.10727.L.str.727.L.str.19627.L.str.9627.L.str.18627.L.str.8627.L.str.17627.L.str.7627.L.str.16627.L.str.6627.L.str.15627.L.str.5627.L.str.14627.L.str.4627.L.str.13627.L.str.3627.L.str.12627.L.str.2627.L.str.11627.L.str.1627.L.str.10627.L.str.627.L.str.19527.L.str.9527.L.str.18527.L.str.8527.L.str.17527.L.str.7527.L.str.16527.L.str.6527.L.str.15527.L.str.5527.L.str.14527.L.str.4527.L.str.13527.L.str.3527.L.str.12527.L.str.2527.L.str.11527.L.str.1527.L.str.10527.L.str.527.L.str.19427.L.str.9427.L.str.18427.L.str.8427.L.str.17427.L.str.7427.L.str.16427.L.str.6427.L.str.15427.L.str.5427.L.str.14427.L.str.4427.L.str.13427.L.str.3427.L.str.12427.L.str.2427.L.str.11427.L.str.1427.L.str.10427.L.str.427.L.str.19327.L.str.9327.L.str.18327.L.str.8327.L.str.17327.L.str.7327.L.str.16327.L.str.6327.L.str.15327.L.str.5327.L.str.14327.L.str.4327.L.str.13327.L.str.3327.L.str.12327.L.str.2327.L.str.11327.L.str.1327.L.str.10327.L.str.327.L.str.19227.L.str.9227.L.str.18227.L.str.8227.L.str.17227.L.str.7227.L.str.16227.L.str.6227.L.str.15227.L.str.5227.L.str.14227.L.str.4227.L.str.13227.L.str.3227.L.str.12227.L.str.2227.L.str.11227.L.str.1227.L.str.10227.L.str.227.L.str.19127.L.str.9127.L.str.18127.L.str.8127.L.str.17127.L.str.7127.L.str.16127.L.str.6127.L.str.15127.L.str.5127.L.str.14127.L.str.4127.L.str.13127.L.str.3127.L.str.12127.L.str.2127.L.str.11127.L.str.1127.L.str.10127.L.str.127.L.str.19027.L.str.9027.L.str.18027.L.str.8027.L.str.17027.L.str.7027.L.str.16027.L.str.6027.L.str.15027.L.str.5027.L.str.14027.L.str.4027.L.str.13027.L.str.3027.L.str.12027.L.str.2027.L.str.11027.L.str.1027.L.str.10027.L.str.27.L.str.9917.L.str.18917.L.str.8917.L.str.17917.L.str.7917.L.str.16917.L.str.6917.L.str.15917.L.str.5917.L.str.14917.L.str.4917.L.str.13917.L.str.3917.L.str.12917.L.str.2917.L.str.11917.L.str.1917.L.str.10917.L.str.917.L.str.19817.L.str.9817.L.str.18817.L.str.8817.L.str.17817.L.str.7817.L.str.16817.L.str.6817.L.str.15817.L.str.5817.L.str.14817.L.str.4817.L.str.13817.L.str.3817.L.str.12817.L.str.2817.L.str.11817.L.str.1817.L.str.10817.L.str.817.L.str.19717.L.str.9717.L.str.18717.L.str.8717.L.str.17717.L.str.7717.L.str.16717.L.str.6717.L.str.15717.L.str.5717.L.str.14717.L.str.4717.L.str.13717.L.str.3717.L.str.12717.L.str.2717.L.str.11717.L.str.1717.L.str.10717.L.str.717.L.str.19617.L.str.9617.L.str.18617.L.str.8617.L.str.17617.L.str.7617.L.str.16617.L.str.6617.L.str.15617.L.str.5617.L.str.14617.L.str.4617.L.str.13617.L.str.3617.L.str.12617.L.str.2617.L.str.11617.L.str.1617.L.str.10617.L.str.617.L.str.19517.L.str.9517.L.str.18517.L.str.8517.L.str.17517.L.str.7517.L.str.16517.L.str.6517.L.str.15517.L.str.5517.L.str.14517.L.str.4517.L.str.13517.L.str.3517.L.str.12517.L.str.2517.L.str.11517.L.str.1517.L.str.10517.L.str.517.L.str.19417.L.str.9417.L.str.18417.L.str.8417.L.str.17417.L.str.7417.L.str.16417.L.str.6417.L.str.15417.L.str.5417.L.str.14417.L.str.4417.L.str.13417.L.str.3417.L.str.12417.L.str.2417.L.str.11417.L.str.1417.L.str.10417.L.str.417.L.str.19317.L.str.9317.L.str.18317.L.str.8317.L.str.17317.L.str.7317.L.str.16317.L.str.6317.L.str.15317.L.str.5317.L.str.14317.L.str.4317.L.str.13317.L.str.3317.L.str.12317.L.str.2317.L.str.11317.L.str.1317.L.str.10317.L.str.317.L.str.19217.L.str.9217.L.str.18217.L.str.8217.L.str.17217.L.str.7217.L.str.16217.L.str.6217.L.str.15217.L.str.5217.L.str.14217.L.str.4217.L.str.13217.L.str.3217.L.str.12217.L.str.2217.L.str.11217.L.str.1217.L.str.10217.L.str.217.L.str.19117.L.str.9117.L.str.18117.L.str.8117.L.str.17117.L.str.7117.L.str.16117.L.str.6117.L.str.15117.L.str.5117.L.str.14117.L.str.4117.L.str.13117.L.str.3117.L.str.12117.L.str.2117.L.str.11117.L.str.1117.L.str.10117.L.str.117.L.str.19017.L.str.9017.L.str.18017.L.str.8017.L.str.17017.L.str.7017.L.str.16017.L.str.6017.L.str.15017.L.str.5017.L.str.14017.L.str.4017.L.str.13017.L.str.3017.L.str.12017.L.str.2017.L.str.11017.L.str.1017.L.str.10017.L.str.17.L.str.9907.L.str.18907.L.str.8907.L.str.17907.L.str.7907.L.str.16907.L.str.6907.L.str.15907.L.str.5907.L.str.14907.L.str.4907.L.str.13907.L.str.3907.L.str.12907.L.str.2907.L.str.11907.L.str.1907.L.str.10907.L.str.907.L.str.19807.L.str.9807.L.str.18807.L.str.8807.L.str.17807.L.str.7807.L.str.16807.L.str.6807.L.str.15807.L.str.5807.L.str.14807.L.str.4807.L.str.13807.L.str.3807.L.str.12807.L.str.2807.L.str.11807.L.str.1807.L.str.10807.L.str.807.L.str.19707.L.str.9707.L.str.18707.L.str.8707.L.str.17707.L.str.7707.L.str.16707.L.str.6707.L.str.15707.L.str.5707.L.str.14707.L.str.4707.L.str.13707.L.str.3707.L.str.12707.L.str.2707.L.str.11707.L.str.1707.L.str.10707.L.str.707.L.str.19607.L.str.9607.L.str.18607.L.str.8607.L.str.17607.L.str.7607.L.str.16607.L.str.6607.L.str.15607.L.str.5607.L.str.14607.L.str.4607.L.str.13607.L.str.3607.L.str.12607.L.str.2607.L.str.11607.L.str.1607.L.str.10607.L.str.607.L.str.19507.L.str.9507.L.str.18507.L.str.8507.L.str.17507.L.str.7507.L.str.16507.L.str.6507.L.str.15507.L.str.5507.L.str.14507.L.str.4507.L.str.13507.L.str.3507.L.str.12507.L.str.2507.L.str.11507.L.str.1507.L.str.10507.L.str.507.L.str.19407.L.str.9407.L.str.18407.L.str.8407.L.str.17407.L.str.7407.L.str.16407.L.str.6407.L.str.15407.L.str.5407.L.str.14407.L.str.4407.L.str.13407.L.str.3407.L.str.12407.L.str.2407.L.str.11407.L.str.1407.L.str.10407.L.str.407.L.str.19307.L.str.9307.L.str.18307.L.str.8307.L.str.17307.L.str.7307.L.str.16307.L.str.6307.L.str.15307.L.str.5307.L.str.14307.L.str.4307.L.str.13307.L.str.3307.L.str.12307.L.str.2307.L.str.11307.L.str.1307.L.str.10307.L.str.307.L.str.19207.L.str.9207.L.str.18207.L.str.8207.L.str.17207.L.str.7207.L.str.16207.L.str.6207.L.str.15207.L.str.5207.L.str.14207.L.str.4207.L.str.13207.L.str.3207.L.str.12207.L.str.2207.L.str.11207.L.str.1207.L.str.10207.L.str.207.L.str.19107.L.str.9107.L.str.18107.L.str.8107.L.str.17107.L.str.7107.L.str.16107.L.str.6107.L.str.15107.L.str.5107.L.str.14107.L.str.4107.L.str.13107.L.str.3107.L.str.12107.L.str.2107.L.str.11107.L.str.1107.L.str.10107.L.str.107.L.str.19007.L.str.9007.L.str.18007.L.str.8007.L.str.17007.L.str.7007.L.str.16007.L.str.6007.L.str.15007.L.str.5007.L.str.14007.L.str.4007.L.str.13007.L.str.3007.L.str.12007.L.str.2007.L.str.11007.L.str.1007.L.str.10007.L.str.7.L.str.9996.L.str.18996.L.str.8996.L.str.17996.L.str.7996.L.str.16996.L.str.6996.L.str.15996.L.str.5996.L.str.14996.L.str.4996.L.str.13996.L.str.3996.L.str.12996.L.str.2996.L.str.11996.L.str.1996.L.str.10996.L.str.996.L.str.9896.L.str.18896.L.str.8896.L.str.17896.L.str.7896.L.str.16896.L.str.6896.L.str.15896.L.str.5896.L.str.14896.L.str.4896.L.str.13896.L.str.3896.L.str.12896.L.str.2896.L.str.11896.L.str.1896.L.str.10896.L.str.896.L.str.19796.L.str.9796.L.str.18796.L.str.8796.L.str.17796.L.str.7796.L.str.16796.L.str.6796.L.str.15796.L.str.5796.L.str.14796.L.str.4796.L.str.13796.L.str.3796.L.str.12796.L.str.2796.L.str.11796.L.str.1796.L.str.10796.L.str.796.L.str.19696.L.str.9696.L.str.18696.L.str.8696.L.str.17696.L.str.7696.L.str.16696.L.str.6696.L.str.15696.L.str.5696.L.str.14696.L.str.4696.L.str.13696.L.str.3696.L.str.12696.L.str.2696.L.str.11696.L.str.1696.L.str.10696.L.str.696.L.str.19596.L.str.9596.L.str.18596.L.str.8596.L.str.17596.L.str.7596.L.str.16596.L.str.6596.L.str.15596.L.str.5596.L.str.14596.L.str.4596.L.str.13596.L.str.3596.L.str.12596.L.str.2596.L.str.11596.L.str.1596.L.str.10596.L.str.596.L.str.19496.L.str.9496.L.str.18496.L.str.8496.L.str.17496.L.str.7496.L.str.16496.L.str.6496.L.str.15496.L.str.5496.L.str.14496.L.str.4496.L.str.13496.L.str.3496.L.str.12496.L.str.2496.L.str.11496.L.str.1496.L.str.10496.L.str.496.L.str.19396.L.str.9396.L.str.18396.L.str.8396.L.str.17396.L.str.7396.L.str.16396.L.str.6396.L.str.15396.L.str.5396.L.str.14396.L.str.4396.L.str.13396.L.str.3396.L.str.12396.L.str.2396.L.str.11396.L.str.1396.L.str.10396.L.str.396.L.str.19296.L.str.9296.L.str.18296.L.str.8296.L.str.17296.L.str.7296.L.str.16296.L.str.6296.L.str.15296.L.str.5296.L.str.14296.L.str.4296.L.str.13296.L.str.3296.L.str.12296.L.str.2296.L.str.11296.L.str.1296.L.str.10296.L.str.296.L.str.19196.L.str.9196.L.str.18196.L.str.8196.L.str.17196.L.str.7196.L.str.16196.L.str.6196.L.str.15196.L.str.5196.L.str.14196.L.str.4196.L.str.13196.L.str.3196.L.str.12196.L.str.2196.L.str.11196.L.str.1196.L.str.10196.L.str.196.L.str.19096.L.str.9096.L.str.18096.L.str.8096.L.str.17096.L.str.7096.L.str.16096.L.str.6096.L.str.15096.L.str.5096.L.str.14096.L.str.4096.L.str.13096.L.str.3096.L.str.12096.L.str.2096.L.str.11096.L.str.1096.L.str.10096.L.str.96.L.str.9986.L.str.18986.L.str.8986.L.str.17986.L.str.7986.L.str.16986.L.str.6986.L.str.15986.L.str.5986.L.str.14986.L.str.4986.L.str.13986.L.str.3986.L.str.12986.L.str.2986.L.str.11986.L.str.1986.L.str.10986.L.str.986.L.str.9886.L.str.18886.L.str.8886.L.str.17886.L.str.7886.L.str.16886.L.str.6886.L.str.15886.L.str.5886.L.str.14886.L.str.4886.L.str.13886.L.str.3886.L.str.12886.L.str.2886.L.str.11886.L.str.1886.L.str.10886.L.str.886.L.str.19786.L.str.9786.L.str.18786.L.str.8786.L.str.17786.L.str.7786.L.str.16786.L.str.6786.L.str.15786.L.str.5786.L.str.14786.L.str.4786.L.str.13786.L.str.3786.L.str.12786.L.str.2786.L.str.11786.L.str.1786.L.str.10786.L.str.786.L.str.19686.L.str.9686.L.str.18686.L.str.8686.L.str.17686.L.str.7686.L.str.16686.L.str.6686.L.str.15686.L.str.5686.L.str.14686.L.str.4686.L.str.13686.L.str.3686.L.str.12686.L.str.2686.L.str.11686.L.str.1686.L.str.10686.L.str.686.L.str.19586.L.str.9586.L.str.18586.L.str.8586.L.str.17586.L.str.7586.L.str.16586.L.str.6586.L.str.15586.L.str.5586.L.str.14586.L.str.4586.L.str.13586.L.str.3586.L.str.12586.L.str.2586.L.str.11586.L.str.1586.L.str.10586.L.str.586.L.str.19486.L.str.9486.L.str.18486.L.str.8486.L.str.17486.L.str.7486.L.str.16486.L.str.6486.L.str.15486.L.str.5486.L.str.14486.L.str.4486.L.str.13486.L.str.3486.L.str.12486.L.str.2486.L.str.11486.L.str.1486.L.str.10486.L.str.486.L.str.19386.L.str.9386.L.str.18386.L.str.8386.L.str.17386.L.str.7386.L.str.16386.L.str.6386.L.str.15386.L.str.5386.L.str.14386.L.str.4386.L.str.13386.L.str.3386.L.str.12386.L.str.2386.L.str.11386.L.str.1386.L.str.10386.L.str.386.L.str.19286.L.str.9286.L.str.18286.L.str.8286.L.str.17286.L.str.7286.L.str.16286.L.str.6286.L.str.15286.L.str.5286.L.str.14286.L.str.4286.L.str.13286.L.str.3286.L.str.12286.L.str.2286.L.str.11286.L.str.1286.L.str.10286.L.str.286.L.str.19186.L.str.9186.L.str.18186.L.str.8186.L.str.17186.L.str.7186.L.str.16186.L.str.6186.L.str.15186.L.str.5186.L.str.14186.L.str.4186.L.str.13186.L.str.3186.L.str.12186.L.str.2186.L.str.11186.L.str.1186.L.str.10186.L.str.186.L.str.19086.L.str.9086.L.str.18086.L.str.8086.L.str.17086.L.str.7086.L.str.16086.L.str.6086.L.str.15086.L.str.5086.L.str.14086.L.str.4086.L.str.13086.L.str.3086.L.str.12086.L.str.2086.L.str.11086.L.str.1086.L.str.10086.L.str.86.L.str.9976.L.str.18976.L.str.8976.L.str.17976.L.str.7976.L.str.16976.L.str.6976.L.str.15976.L.str.5976.L.str.14976.L.str.4976.L.str.13976.L.str.3976.L.str.12976.L.str.2976.L.str.11976.L.str.1976.L.str.10976.L.str.976.L.str.9876.L.str.18876.L.str.8876.L.str.17876.L.str.7876.L.str.16876.L.str.6876.L.str.15876.L.str.5876.L.str.14876.L.str.4876.L.str.13876.L.str.3876.L.str.12876.L.str.2876.L.str.11876.L.str.1876.L.str.10876.L.str.876.L.str.19776.L.str.9776.L.str.18776.L.str.8776.L.str.17776.L.str.7776.L.str.16776.L.str.6776.L.str.15776.L.str.5776.L.str.14776.L.str.4776.L.str.13776.L.str.3776.L.str.12776.L.str.2776.L.str.11776.L.str.1776.L.str.10776.L.str.776.L.str.19676.L.str.9676.L.str.18676.L.str.8676.L.str.17676.L.str.7676.L.str.16676.L.str.6676.L.str.15676.L.str.5676.L.str.14676.L.str.4676.L.str.13676.L.str.3676.L.str.12676.L.str.2676.L.str.11676.L.str.1676.L.str.10676.L.str.676.L.str.19576.L.str.9576.L.str.18576.L.str.8576.L.str.17576.L.str.7576.L.str.16576.L.str.6576.L.str.15576.L.str.5576.L.str.14576.L.str.4576.L.str.13576.L.str.3576.L.str.12576.L.str.2576.L.str.11576.L.str.1576.L.str.10576.L.str.576.L.str.19476.L.str.9476.L.str.18476.L.str.8476.L.str.17476.L.str.7476.L.str.16476.L.str.6476.L.str.15476.L.str.5476.L.str.14476.L.str.4476.L.str.13476.L.str.3476.L.str.12476.L.str.2476.L.str.11476.L.str.1476.L.str.10476.L.str.476.L.str.19376.L.str.9376.L.str.18376.L.str.8376.L.str.17376.L.str.7376.L.str.16376.L.str.6376.L.str.15376.L.str.5376.L.str.14376.L.str.4376.L.str.13376.L.str.3376.L.str.12376.L.str.2376.L.str.11376.L.str.1376.L.str.10376.L.str.376.L.str.19276.L.str.9276.L.str.18276.L.str.8276.L.str.17276.L.str.7276.L.str.16276.L.str.6276.L.str.15276.L.str.5276.L.str.14276.L.str.4276.L.str.13276.L.str.3276.L.str.12276.L.str.2276.L.str.11276.L.str.1276.L.str.10276.L.str.276.L.str.19176.L.str.9176.L.str.18176.L.str.8176.L.str.17176.L.str.7176.L.str.16176.L.str.6176.L.str.15176.L.str.5176.L.str.14176.L.str.4176.L.str.13176.L.str.3176.L.str.12176.L.str.2176.L.str.11176.L.str.1176.L.str.10176.L.str.176.L.str.19076.L.str.9076.L.str.18076.L.str.8076.L.str.17076.L.str.7076.L.str.16076.L.str.6076.L.str.15076.L.str.5076.L.str.14076.L.str.4076.L.str.13076.L.str.3076.L.str.12076.L.str.2076.L.str.11076.L.str.1076.L.str.10076.L.str.76.L.str.9966.L.str.18966.L.str.8966.L.str.17966.L.str.7966.L.str.16966.L.str.6966.L.str.15966.L.str.5966.L.str.14966.L.str.4966.L.str.13966.L.str.3966.L.str.12966.L.str.2966.L.str.11966.L.str.1966.L.str.10966.L.str.966.L.str.19866.L.str.9866.L.str.18866.L.str.8866.L.str.17866.L.str.7866.L.str.16866.L.str.6866.L.str.15866.L.str.5866.L.str.14866.L.str.4866.L.str.13866.L.str.3866.L.str.12866.L.str.2866.L.str.11866.L.str.1866.L.str.10866.L.str.866.L.str.19766.L.str.9766.L.str.18766.L.str.8766.L.str.17766.L.str.7766.L.str.16766.L.str.6766.L.str.15766.L.str.5766.L.str.14766.L.str.4766.L.str.13766.L.str.3766.L.str.12766.L.str.2766.L.str.11766.L.str.1766.L.str.10766.L.str.766.L.str.19666.L.str.9666.L.str.18666.L.str.8666.L.str.17666.L.str.7666.L.str.16666.L.str.6666.L.str.15666.L.str.5666.L.str.14666.L.str.4666.L.str.13666.L.str.3666.L.str.12666.L.str.2666.L.str.11666.L.str.1666.L.str.10666.L.str.666.L.str.19566.L.str.9566.L.str.18566.L.str.8566.L.str.17566.L.str.7566.L.str.16566.L.str.6566.L.str.15566.L.str.5566.L.str.14566.L.str.4566.L.str.13566.L.str.3566.L.str.12566.L.str.2566.L.str.11566.L.str.1566.L.str.10566.L.str.566.L.str.19466.L.str.9466.L.str.18466.L.str.8466.L.str.17466.L.str.7466.L.str.16466.L.str.6466.L.str.15466.L.str.5466.L.str.14466.L.str.4466.L.str.13466.L.str.3466.L.str.12466.L.str.2466.L.str.11466.L.str.1466.L.str.10466.L.str.466.L.str.19366.L.str.9366.L.str.18366.L.str.8366.L.str.17366.L.str.7366.L.str.16366.L.str.6366.L.str.15366.L.str.5366.L.str.14366.L.str.4366.L.str.13366.L.str.3366.L.str.12366.L.str.2366.L.str.11366.L.str.1366.L.str.10366.L.str.366.L.str.19266.L.str.9266.L.str.18266.L.str.8266.L.str.17266.L.str.7266.L.str.16266.L.str.6266.L.str.15266.L.str.5266.L.str.14266.L.str.4266.L.str.13266.L.str.3266.L.str.12266.L.str.2266.L.str.11266.L.str.1266.L.str.10266.L.str.266.L.str.19166.L.str.9166.L.str.18166.L.str.8166.L.str.17166.L.str.7166.L.str.16166.L.str.6166.L.str.15166.L.str.5166.L.str.14166.L.str.4166.L.str.13166.L.str.3166.L.str.12166.L.str.2166.L.str.11166.L.str.1166.L.str.10166.L.str.166.L.str.19066.L.str.9066.L.str.18066.L.str.8066.L.str.17066.L.str.7066.L.str.16066.L.str.6066.L.str.15066.L.str.5066.L.str.14066.L.str.4066.L.str.13066.L.str.3066.L.str.12066.L.str.2066.L.str.11066.L.str.1066.L.str.10066.L.str.66.L.str.9956.L.str.18956.L.str.8956.L.str.17956.L.str.7956.L.str.16956.L.str.6956.L.str.15956.L.str.5956.L.str.14956.L.str.4956.L.str.13956.L.str.3956.L.str.12956.L.str.2956.L.str.11956.L.str.1956.L.str.10956.L.str.956.L.str.19856.L.str.9856.L.str.18856.L.str.8856.L.str.17856.L.str.7856.L.str.16856.L.str.6856.L.str.15856.L.str.5856.L.str.14856.L.str.4856.L.str.13856.L.str.3856.L.str.12856.L.str.2856.L.str.11856.L.str.1856.L.str.10856.L.str.856.L.str.19756.L.str.9756.L.str.18756.L.str.8756.L.str.17756.L.str.7756.L.str.16756.L.str.6756.L.str.15756.L.str.5756.L.str.14756.L.str.4756.L.str.13756.L.str.3756.L.str.12756.L.str.2756.L.str.11756.L.str.1756.L.str.10756.L.str.756.L.str.19656.L.str.9656.L.str.18656.L.str.8656.L.str.17656.L.str.7656.L.str.16656.L.str.6656.L.str.15656.L.str.5656.L.str.14656.L.str.4656.L.str.13656.L.str.3656.L.str.12656.L.str.2656.L.str.11656.L.str.1656.L.str.10656.L.str.656.L.str.19556.L.str.9556.L.str.18556.L.str.8556.L.str.17556.L.str.7556.L.str.16556.L.str.6556.L.str.15556.L.str.5556.L.str.14556.L.str.4556.L.str.13556.L.str.3556.L.str.12556.L.str.2556.L.str.11556.L.str.1556.L.str.10556.L.str.556.L.str.19456.L.str.9456.L.str.18456.L.str.8456.L.str.17456.L.str.7456.L.str.16456.L.str.6456.L.str.15456.L.str.5456.L.str.14456.L.str.4456.L.str.13456.L.str.3456.L.str.12456.L.str.2456.L.str.11456.L.str.1456.L.str.10456.L.str.456.L.str.19356.L.str.9356.L.str.18356.L.str.8356.L.str.17356.L.str.7356.L.str.16356.L.str.6356.L.str.15356.L.str.5356.L.str.14356.L.str.4356.L.str.13356.L.str.3356.L.str.12356.L.str.2356.L.str.11356.L.str.1356.L.str.10356.L.str.356.L.str.19256.L.str.9256.L.str.18256.L.str.8256.L.str.17256.L.str.7256.L.str.16256.L.str.6256.L.str.15256.L.str.5256.L.str.14256.L.str.4256.L.str.13256.L.str.3256.L.str.12256.L.str.2256.L.str.11256.L.str.1256.L.str.10256.L.str.256.L.str.19156.L.str.9156.L.str.18156.L.str.8156.L.str.17156.L.str.7156.L.str.16156.L.str.6156.L.str.15156.L.str.5156.L.str.14156.L.str.4156.L.str.13156.L.str.3156.L.str.12156.L.str.2156.L.str.11156.L.str.1156.L.str.10156.L.str.156.L.str.19056.L.str.9056.L.str.18056.L.str.8056.L.str.17056.L.str.7056.L.str.16056.L.str.6056.L.str.15056.L.str.5056.L.str.14056.L.str.4056.L.str.13056.L.str.3056.L.str.12056.L.str.2056.L.str.11056.L.str.1056.L.str.10056.L.str.56.L.str.9946.L.str.18946.L.str.8946.L.str.17946.L.str.7946.L.str.16946.L.str.6946.L.str.15946.L.str.5946.L.str.14946.L.str.4946.L.str.13946.L.str.3946.L.str.12946.L.str.2946.L.str.11946.L.str.1946.L.str.10946.L.str.946.L.str.19846.L.str.9846.L.str.18846.L.str.8846.L.str.17846.L.str.7846.L.str.16846.L.str.6846.L.str.15846.L.str.5846.L.str.14846.L.str.4846.L.str.13846.L.str.3846.L.str.12846.L.str.2846.L.str.11846.L.str.1846.L.str.10846.L.str.846.L.str.19746.L.str.9746.L.str.18746.L.str.8746.L.str.17746.L.str.7746.L.str.16746.L.str.6746.L.str.15746.L.str.5746.L.str.14746.L.str.4746.L.str.13746.L.str.3746.L.str.12746.L.str.2746.L.str.11746.L.str.1746.L.str.10746.L.str.746.L.str.19646.L.str.9646.L.str.18646.L.str.8646.L.str.17646.L.str.7646.L.str.16646.L.str.6646.L.str.15646.L.str.5646.L.str.14646.L.str.4646.L.str.13646.L.str.3646.L.str.12646.L.str.2646.L.str.11646.L.str.1646.L.str.10646.L.str.646.L.str.19546.L.str.9546.L.str.18546.L.str.8546.L.str.17546.L.str.7546.L.str.16546.L.str.6546.L.str.15546.L.str.5546.L.str.14546.L.str.4546.L.str.13546.L.str.3546.L.str.12546.L.str.2546.L.str.11546.L.str.1546.L.str.10546.L.str.546.L.str.19446.L.str.9446.L.str.18446.L.str.8446.L.str.17446.L.str.7446.L.str.16446.L.str.6446.L.str.15446.L.str.5446.L.str.14446.L.str.4446.L.str.13446.L.str.3446.L.str.12446.L.str.2446.L.str.11446.L.str.1446.L.str.10446.L.str.446.L.str.19346.L.str.9346.L.str.18346.L.str.8346.L.str.17346.L.str.7346.L.str.16346.L.str.6346.L.str.15346.L.str.5346.L.str.14346.L.str.4346.L.str.13346.L.str.3346.L.str.12346.L.str.2346.L.str.11346.L.str.1346.L.str.10346.L.str.346.L.str.19246.L.str.9246.L.str.18246.L.str.8246.L.str.17246.L.str.7246.L.str.16246.L.str.6246.L.str.15246.L.str.5246.L.str.14246.L.str.4246.L.str.13246.L.str.3246.L.str.12246.L.str.2246.L.str.11246.L.str.1246.L.str.10246.L.str.246.L.str.19146.L.str.9146.L.str.18146.L.str.8146.L.str.17146.L.str.7146.L.str.16146.L.str.6146.L.str.15146.L.str.5146.L.str.14146.L.str.4146.L.str.13146.L.str.3146.L.str.12146.L.str.2146.L.str.11146.L.str.1146.L.str.10146.L.str.146.L.str.19046.L.str.9046.L.str.18046.L.str.8046.L.str.17046.L.str.7046.L.str.16046.L.str.6046.L.str.15046.L.str.5046.L.str.14046.L.str.4046.L.str.13046.L.str.3046.L.str.12046.L.str.2046.L.str.11046.L.str.1046.L.str.10046.L.str.46.L.str.9936.L.str.18936.L.str.8936.L.str.17936.L.str.7936.L.str.16936.L.str.6936.L.str.15936.L.str.5936.L.str.14936.L.str.4936.L.str.13936.L.str.3936.L.str.12936.L.str.2936.L.str.11936.L.str.1936.L.str.10936.L.str.936.L.str.19836.L.str.9836.L.str.18836.L.str.8836.L.str.17836.L.str.7836.L.str.16836.L.str.6836.L.str.15836.L.str.5836.L.str.14836.L.str.4836.L.str.13836.L.str.3836.L.str.12836.L.str.2836.L.str.11836.L.str.1836.L.str.10836.L.str.836.L.str.19736.L.str.9736.L.str.18736.L.str.8736.L.str.17736.L.str.7736.L.str.16736.L.str.6736.L.str.15736.L.str.5736.L.str.14736.L.str.4736.L.str.13736.L.str.3736.L.str.12736.L.str.2736.L.str.11736.L.str.1736.L.str.10736.L.str.736.L.str.19636.L.str.9636.L.str.18636.L.str.8636.L.str.17636.L.str.7636.L.str.16636.L.str.6636.L.str.15636.L.str.5636.L.str.14636.L.str.4636.L.str.13636.L.str.3636.L.str.12636.L.str.2636.L.str.11636.L.str.1636.L.str.10636.L.str.636.L.str.19536.L.str.9536.L.str.18536.L.str.8536.L.str.17536.L.str.7536.L.str.16536.L.str.6536.L.str.15536.L.str.5536.L.str.14536.L.str.4536.L.str.13536.L.str.3536.L.str.12536.L.str.2536.L.str.11536.L.str.1536.L.str.10536.L.str.536.L.str.19436.L.str.9436.L.str.18436.L.str.8436.L.str.17436.L.str.7436.L.str.16436.L.str.6436.L.str.15436.L.str.5436.L.str.14436.L.str.4436.L.str.13436.L.str.3436.L.str.12436.L.str.2436.L.str.11436.L.str.1436.L.str.10436.L.str.436.L.str.19336.L.str.9336.L.str.18336.L.str.8336.L.str.17336.L.str.7336.L.str.16336.L.str.6336.L.str.15336.L.str.5336.L.str.14336.L.str.4336.L.str.13336.L.str.3336.L.str.12336.L.str.2336.L.str.11336.L.str.1336.L.str.10336.L.str.336.L.str.19236.L.str.9236.L.str.18236.L.str.8236.L.str.17236.L.str.7236.L.str.16236.L.str.6236.L.str.15236.L.str.5236.L.str.14236.L.str.4236.L.str.13236.L.str.3236.L.str.12236.L.str.2236.L.str.11236.L.str.1236.L.str.10236.L.str.236.L.str.19136.L.str.9136.L.str.18136.L.str.8136.L.str.17136.L.str.7136.L.str.16136.L.str.6136.L.str.15136.L.str.5136.L.str.14136.L.str.4136.L.str.13136.L.str.3136.L.str.12136.L.str.2136.L.str.11136.L.str.1136.L.str.10136.L.str.136.L.str.19036.L.str.9036.L.str.18036.L.str.8036.L.str.17036.L.str.7036.L.str.16036.L.str.6036.L.str.15036.L.str.5036.L.str.14036.L.str.4036.L.str.13036.L.str.3036.L.str.12036.L.str.2036.L.str.11036.L.str.1036.L.str.10036.L.str.36.L.str.9926.L.str.18926.L.str.8926.L.str.17926.L.str.7926.L.str.16926.L.str.6926.L.str.15926.L.str.5926.L.str.14926.L.str.4926.L.str.13926.L.str.3926.L.str.12926.L.str.2926.L.str.11926.L.str.1926.L.str.10926.L.str.926.L.str.19826.L.str.9826.L.str.18826.L.str.8826.L.str.17826.L.str.7826.L.str.16826.L.str.6826.L.str.15826.L.str.5826.L.str.14826.L.str.4826.L.str.13826.L.str.3826.L.str.12826.L.str.2826.L.str.11826.L.str.1826.L.str.10826.L.str.826.L.str.19726.L.str.9726.L.str.18726.L.str.8726.L.str.17726.L.str.7726.L.str.16726.L.str.6726.L.str.15726.L.str.5726.L.str.14726.L.str.4726.L.str.13726.L.str.3726.L.str.12726.L.str.2726.L.str.11726.L.str.1726.L.str.10726.L.str.726.L.str.19626.L.str.9626.L.str.18626.L.str.8626.L.str.17626.L.str.7626.L.str.16626.L.str.6626.L.str.15626.L.str.5626.L.str.14626.L.str.4626.L.str.13626.L.str.3626.L.str.12626.L.str.2626.L.str.11626.L.str.1626.L.str.10626.L.str.626.L.str.19526.L.str.9526.L.str.18526.L.str.8526.L.str.17526.L.str.7526.L.str.16526.L.str.6526.L.str.15526.L.str.5526.L.str.14526.L.str.4526.L.str.13526.L.str.3526.L.str.12526.L.str.2526.L.str.11526.L.str.1526.L.str.10526.L.str.526.L.str.19426.L.str.9426.L.str.18426.L.str.8426.L.str.17426.L.str.7426.L.str.16426.L.str.6426.L.str.15426.L.str.5426.L.str.14426.L.str.4426.L.str.13426.L.str.3426.L.str.12426.L.str.2426.L.str.11426.L.str.1426.L.str.10426.L.str.426.L.str.19326.L.str.9326.L.str.18326.L.str.8326.L.str.17326.L.str.7326.L.str.16326.L.str.6326.L.str.15326.L.str.5326.L.str.14326.L.str.4326.L.str.13326.L.str.3326.L.str.12326.L.str.2326.L.str.11326.L.str.1326.L.str.10326.L.str.326.L.str.19226.L.str.9226.L.str.18226.L.str.8226.L.str.17226.L.str.7226.L.str.16226.L.str.6226.L.str.15226.L.str.5226.L.str.14226.L.str.4226.L.str.13226.L.str.3226.L.str.12226.L.str.2226.L.str.11226.L.str.1226.L.str.10226.L.str.226.L.str.19126.L.str.9126.L.str.18126.L.str.8126.L.str.17126.L.str.7126.L.str.16126.L.str.6126.L.str.15126.L.str.5126.L.str.14126.L.str.4126.L.str.13126.L.str.3126.L.str.12126.L.str.2126.L.str.11126.L.str.1126.L.str.10126.L.str.126.L.str.19026.L.str.9026.L.str.18026.L.str.8026.L.str.17026.L.str.7026.L.str.16026.L.str.6026.L.str.15026.L.str.5026.L.str.14026.L.str.4026.L.str.13026.L.str.3026.L.str.12026.L.str.2026.L.str.11026.L.str.1026.L.str.10026.L.str.26.L.str.9916.L.str.18916.L.str.8916.L.str.17916.L.str.7916.L.str.16916.L.str.6916.L.str.15916.L.str.5916.L.str.14916.L.str.4916.L.str.13916.L.str.3916.L.str.12916.L.str.2916.L.str.11916.L.str.1916.L.str.10916.L.str.916.L.str.19816.L.str.9816.L.str.18816.L.str.8816.L.str.17816.L.str.7816.L.str.16816.L.str.6816.L.str.15816.L.str.5816.L.str.14816.L.str.4816.L.str.13816.L.str.3816.L.str.12816.L.str.2816.L.str.11816.L.str.1816.L.str.10816.L.str.816.L.str.19716.L.str.9716.L.str.18716.L.str.8716.L.str.17716.L.str.7716.L.str.16716.L.str.6716.L.str.15716.L.str.5716.L.str.14716.L.str.4716.L.str.13716.L.str.3716.L.str.12716.L.str.2716.L.str.11716.L.str.1716.L.str.10716.L.str.716.L.str.19616.L.str.9616.L.str.18616.L.str.8616.L.str.17616.L.str.7616.L.str.16616.L.str.6616.L.str.15616.L.str.5616.L.str.14616.L.str.4616.L.str.13616.L.str.3616.L.str.12616.L.str.2616.L.str.11616.L.str.1616.L.str.10616.L.str.616.L.str.19516.L.str.9516.L.str.18516.L.str.8516.L.str.17516.L.str.7516.L.str.16516.L.str.6516.L.str.15516.L.str.5516.L.str.14516.L.str.4516.L.str.13516.L.str.3516.L.str.12516.L.str.2516.L.str.11516.L.str.1516.L.str.10516.L.str.516.L.str.19416.L.str.9416.L.str.18416.L.str.8416.L.str.17416.L.str.7416.L.str.16416.L.str.6416.L.str.15416.L.str.5416.L.str.14416.L.str.4416.L.str.13416.L.str.3416.L.str.12416.L.str.2416.L.str.11416.L.str.1416.L.str.10416.L.str.416.L.str.19316.L.str.9316.L.str.18316.L.str.8316.L.str.17316.L.str.7316.L.str.16316.L.str.6316.L.str.15316.L.str.5316.L.str.14316.L.str.4316.L.str.13316.L.str.3316.L.str.12316.L.str.2316.L.str.11316.L.str.1316.L.str.10316.L.str.316.L.str.19216.L.str.9216.L.str.18216.L.str.8216.L.str.17216.L.str.7216.L.str.16216.L.str.6216.L.str.15216.L.str.5216.L.str.14216.L.str.4216.L.str.13216.L.str.3216.L.str.12216.L.str.2216.L.str.11216.L.str.1216.L.str.10216.L.str.216.L.str.19116.L.str.9116.L.str.18116.L.str.8116.L.str.17116.L.str.7116.L.str.16116.L.str.6116.L.str.15116.L.str.5116.L.str.14116.L.str.4116.L.str.13116.L.str.3116.L.str.12116.L.str.2116.L.str.11116.L.str.1116.L.str.10116.L.str.116.L.str.19016.L.str.9016.L.str.18016.L.str.8016.L.str.17016.L.str.7016.L.str.16016.L.str.6016.L.str.15016.L.str.5016.L.str.14016.L.str.4016.L.str.13016.L.str.3016.L.str.12016.L.str.2016.L.str.11016.L.str.1016.L.str.10016.L.str.16.L.str.9906.L.str.18906.L.str.8906.L.str.17906.L.str.7906.L.str.16906.L.str.6906.L.str.15906.L.str.5906.L.str.14906.L.str.4906.L.str.13906.L.str.3906.L.str.12906.L.str.2906.L.str.11906.L.str.1906.L.str.10906.L.str.906.L.str.19806.L.str.9806.L.str.18806.L.str.8806.L.str.17806.L.str.7806.L.str.16806.L.str.6806.L.str.15806.L.str.5806.L.str.14806.L.str.4806.L.str.13806.L.str.3806.L.str.12806.L.str.2806.L.str.11806.L.str.1806.L.str.10806.L.str.806.L.str.19706.L.str.9706.L.str.18706.L.str.8706.L.str.17706.L.str.7706.L.str.16706.L.str.6706.L.str.15706.L.str.5706.L.str.14706.L.str.4706.L.str.13706.L.str.3706.L.str.12706.L.str.2706.L.str.11706.L.str.1706.L.str.10706.L.str.706.L.str.19606.L.str.9606.L.str.18606.L.str.8606.L.str.17606.L.str.7606.L.str.16606.L.str.6606.L.str.15606.L.str.5606.L.str.14606.L.str.4606.L.str.13606.L.str.3606.L.str.12606.L.str.2606.L.str.11606.L.str.1606.L.str.10606.L.str.606.L.str.19506.L.str.9506.L.str.18506.L.str.8506.L.str.17506.L.str.7506.L.str.16506.L.str.6506.L.str.15506.L.str.5506.L.str.14506.L.str.4506.L.str.13506.L.str.3506.L.str.12506.L.str.2506.L.str.11506.L.str.1506.L.str.10506.L.str.506.L.str.19406.L.str.9406.L.str.18406.L.str.8406.L.str.17406.L.str.7406.L.str.16406.L.str.6406.L.str.15406.L.str.5406.L.str.14406.L.str.4406.L.str.13406.L.str.3406.L.str.12406.L.str.2406.L.str.11406.L.str.1406.L.str.10406.L.str.406.L.str.19306.L.str.9306.L.str.18306.L.str.8306.L.str.17306.L.str.7306.L.str.16306.L.str.6306.L.str.15306.L.str.5306.L.str.14306.L.str.4306.L.str.13306.L.str.3306.L.str.12306.L.str.2306.L.str.11306.L.str.1306.L.str.10306.L.str.306.L.str.19206.L.str.9206.L.str.18206.L.str.8206.L.str.17206.L.str.7206.L.str.16206.L.str.6206.L.str.15206.L.str.5206.L.str.14206.L.str.4206.L.str.13206.L.str.3206.L.str.12206.L.str.2206.L.str.11206.L.str.1206.L.str.10206.L.str.206.L.str.19106.L.str.9106.L.str.18106.L.str.8106.L.str.17106.L.str.7106.L.str.16106.L.str.6106.L.str.15106.L.str.5106.L.str.14106.L.str.4106.L.str.13106.L.str.3106.L.str.12106.L.str.2106.L.str.11106.L.str.1106.L.str.10106.L.str.106.L.str.19006.L.str.9006.L.str.18006.L.str.8006.L.str.17006.L.str.7006.L.str.16006.L.str.6006.L.str.15006.L.str.5006.L.str.14006.L.str.4006.L.str.13006.L.str.3006.L.str.12006.L.str.2006.L.str.11006.L.str.1006.L.str.10006.L.str.6.L.str.9995.L.str.18995.L.str.8995.L.str.17995.L.str.7995.L.str.16995.L.str.6995.L.str.15995.L.str.5995.L.str.14995.L.str.4995.L.str.13995.L.str.3995.L.str.12995.L.str.2995.L.str.11995.L.str.1995.L.str.10995.L.str.995.L.str.9895.L.str.18895.L.str.8895.L.str.17895.L.str.7895.L.str.16895.L.str.6895.L.str.15895.L.str.5895.L.str.14895.L.str.4895.L.str.13895.L.str.3895.L.str.12895.L.str.2895.L.str.11895.L.str.1895.L.str.10895.L.str.895.L.str.19795.L.str.9795.L.str.18795.L.str.8795.L.str.17795.L.str.7795.L.str.16795.L.str.6795.L.str.15795.L.str.5795.L.str.14795.L.str.4795.L.str.13795.L.str.3795.L.str.12795.L.str.2795.L.str.11795.L.str.1795.L.str.10795.L.str.795.L.str.19695.L.str.9695.L.str.18695.L.str.8695.L.str.17695.L.str.7695.L.str.16695.L.str.6695.L.str.15695.L.str.5695.L.str.14695.L.str.4695.L.str.13695.L.str.3695.L.str.12695.L.str.2695.L.str.11695.L.str.1695.L.str.10695.L.str.695.L.str.19595.L.str.9595.L.str.18595.L.str.8595.L.str.17595.L.str.7595.L.str.16595.L.str.6595.L.str.15595.L.str.5595.L.str.14595.L.str.4595.L.str.13595.L.str.3595.L.str.12595.L.str.2595.L.str.11595.L.str.1595.L.str.10595.L.str.595.L.str.19495.L.str.9495.L.str.18495.L.str.8495.L.str.17495.L.str.7495.L.str.16495.L.str.6495.L.str.15495.L.str.5495.L.str.14495.L.str.4495.L.str.13495.L.str.3495.L.str.12495.L.str.2495.L.str.11495.L.str.1495.L.str.10495.L.str.495.L.str.19395.L.str.9395.L.str.18395.L.str.8395.L.str.17395.L.str.7395.L.str.16395.L.str.6395.L.str.15395.L.str.5395.L.str.14395.L.str.4395.L.str.13395.L.str.3395.L.str.12395.L.str.2395.L.str.11395.L.str.1395.L.str.10395.L.str.395.L.str.19295.L.str.9295.L.str.18295.L.str.8295.L.str.17295.L.str.7295.L.str.16295.L.str.6295.L.str.15295.L.str.5295.L.str.14295.L.str.4295.L.str.13295.L.str.3295.L.str.12295.L.str.2295.L.str.11295.L.str.1295.L.str.10295.L.str.295.L.str.19195.L.str.9195.L.str.18195.L.str.8195.L.str.17195.L.str.7195.L.str.16195.L.str.6195.L.str.15195.L.str.5195.L.str.14195.L.str.4195.L.str.13195.L.str.3195.L.str.12195.L.str.2195.L.str.11195.L.str.1195.L.str.10195.L.str.195.L.str.19095.L.str.9095.L.str.18095.L.str.8095.L.str.17095.L.str.7095.L.str.16095.L.str.6095.L.str.15095.L.str.5095.L.str.14095.L.str.4095.L.str.13095.L.str.3095.L.str.12095.L.str.2095.L.str.11095.L.str.1095.L.str.10095.L.str.95.L.str.9985.L.str.18985.L.str.8985.L.str.17985.L.str.7985.L.str.16985.L.str.6985.L.str.15985.L.str.5985.L.str.14985.L.str.4985.L.str.13985.L.str.3985.L.str.12985.L.str.2985.L.str.11985.L.str.1985.L.str.10985.L.str.985.L.str.9885.L.str.18885.L.str.8885.L.str.17885.L.str.7885.L.str.16885.L.str.6885.L.str.15885.L.str.5885.L.str.14885.L.str.4885.L.str.13885.L.str.3885.L.str.12885.L.str.2885.L.str.11885.L.str.1885.L.str.10885.L.str.885.L.str.19785.L.str.9785.L.str.18785.L.str.8785.L.str.17785.L.str.7785.L.str.16785.L.str.6785.L.str.15785.L.str.5785.L.str.14785.L.str.4785.L.str.13785.L.str.3785.L.str.12785.L.str.2785.L.str.11785.L.str.1785.L.str.10785.L.str.785.L.str.19685.L.str.9685.L.str.18685.L.str.8685.L.str.17685.L.str.7685.L.str.16685.L.str.6685.L.str.15685.L.str.5685.L.str.14685.L.str.4685.L.str.13685.L.str.3685.L.str.12685.L.str.2685.L.str.11685.L.str.1685.L.str.10685.L.str.685.L.str.19585.L.str.9585.L.str.18585.L.str.8585.L.str.17585.L.str.7585.L.str.16585.L.str.6585.L.str.15585.L.str.5585.L.str.14585.L.str.4585.L.str.13585.L.str.3585.L.str.12585.L.str.2585.L.str.11585.L.str.1585.L.str.10585.L.str.585.L.str.19485.L.str.9485.L.str.18485.L.str.8485.L.str.17485.L.str.7485.L.str.16485.L.str.6485.L.str.15485.L.str.5485.L.str.14485.L.str.4485.L.str.13485.L.str.3485.L.str.12485.L.str.2485.L.str.11485.L.str.1485.L.str.10485.L.str.485.L.str.19385.L.str.9385.L.str.18385.L.str.8385.L.str.17385.L.str.7385.L.str.16385.L.str.6385.L.str.15385.L.str.5385.L.str.14385.L.str.4385.L.str.13385.L.str.3385.L.str.12385.L.str.2385.L.str.11385.L.str.1385.L.str.10385.L.str.385.L.str.19285.L.str.9285.L.str.18285.L.str.8285.L.str.17285.L.str.7285.L.str.16285.L.str.6285.L.str.15285.L.str.5285.L.str.14285.L.str.4285.L.str.13285.L.str.3285.L.str.12285.L.str.2285.L.str.11285.L.str.1285.L.str.10285.L.str.285.L.str.19185.L.str.9185.L.str.18185.L.str.8185.L.str.17185.L.str.7185.L.str.16185.L.str.6185.L.str.15185.L.str.5185.L.str.14185.L.str.4185.L.str.13185.L.str.3185.L.str.12185.L.str.2185.L.str.11185.L.str.1185.L.str.10185.L.str.185.L.str.19085.L.str.9085.L.str.18085.L.str.8085.L.str.17085.L.str.7085.L.str.16085.L.str.6085.L.str.15085.L.str.5085.L.str.14085.L.str.4085.L.str.13085.L.str.3085.L.str.12085.L.str.2085.L.str.11085.L.str.1085.L.str.10085.L.str.85.L.str.9975.L.str.18975.L.str.8975.L.str.17975.L.str.7975.L.str.16975.L.str.6975.L.str.15975.L.str.5975.L.str.14975.L.str.4975.L.str.13975.L.str.3975.L.str.12975.L.str.2975.L.str.11975.L.str.1975.L.str.10975.L.str.975.L.str.9875.L.str.18875.L.str.8875.L.str.17875.L.str.7875.L.str.16875.L.str.6875.L.str.15875.L.str.5875.L.str.14875.L.str.4875.L.str.13875.L.str.3875.L.str.12875.L.str.2875.L.str.11875.L.str.1875.L.str.10875.L.str.875.L.str.19775.L.str.9775.L.str.18775.L.str.8775.L.str.17775.L.str.7775.L.str.16775.L.str.6775.L.str.15775.L.str.5775.L.str.14775.L.str.4775.L.str.13775.L.str.3775.L.str.12775.L.str.2775.L.str.11775.L.str.1775.L.str.10775.L.str.775.L.str.19675.L.str.9675.L.str.18675.L.str.8675.L.str.17675.L.str.7675.L.str.16675.L.str.6675.L.str.15675.L.str.5675.L.str.14675.L.str.4675.L.str.13675.L.str.3675.L.str.12675.L.str.2675.L.str.11675.L.str.1675.L.str.10675.L.str.675.L.str.19575.L.str.9575.L.str.18575.L.str.8575.L.str.17575.L.str.7575.L.str.16575.L.str.6575.L.str.15575.L.str.5575.L.str.14575.L.str.4575.L.str.13575.L.str.3575.L.str.12575.L.str.2575.L.str.11575.L.str.1575.L.str.10575.L.str.575.L.str.19475.L.str.9475.L.str.18475.L.str.8475.L.str.17475.L.str.7475.L.str.16475.L.str.6475.L.str.15475.L.str.5475.L.str.14475.L.str.4475.L.str.13475.L.str.3475.L.str.12475.L.str.2475.L.str.11475.L.str.1475.L.str.10475.L.str.475.L.str.19375.L.str.9375.L.str.18375.L.str.8375.L.str.17375.L.str.7375.L.str.16375.L.str.6375.L.str.15375.L.str.5375.L.str.14375.L.str.4375.L.str.13375.L.str.3375.L.str.12375.L.str.2375.L.str.11375.L.str.1375.L.str.10375.L.str.375.L.str.19275.L.str.9275.L.str.18275.L.str.8275.L.str.17275.L.str.7275.L.str.16275.L.str.6275.L.str.15275.L.str.5275.L.str.14275.L.str.4275.L.str.13275.L.str.3275.L.str.12275.L.str.2275.L.str.11275.L.str.1275.L.str.10275.L.str.275.L.str.19175.L.str.9175.L.str.18175.L.str.8175.L.str.17175.L.str.7175.L.str.16175.L.str.6175.L.str.15175.L.str.5175.L.str.14175.L.str.4175.L.str.13175.L.str.3175.L.str.12175.L.str.2175.L.str.11175.L.str.1175.L.str.10175.L.str.175.L.str.19075.L.str.9075.L.str.18075.L.str.8075.L.str.17075.L.str.7075.L.str.16075.L.str.6075.L.str.15075.L.str.5075.L.str.14075.L.str.4075.L.str.13075.L.str.3075.L.str.12075.L.str.2075.L.str.11075.L.str.1075.L.str.10075.L.str.75.L.str.9965.L.str.18965.L.str.8965.L.str.17965.L.str.7965.L.str.16965.L.str.6965.L.str.15965.L.str.5965.L.str.14965.L.str.4965.L.str.13965.L.str.3965.L.str.12965.L.str.2965.L.str.11965.L.str.1965.L.str.10965.L.str.965.L.str.19865.L.str.9865.L.str.18865.L.str.8865.L.str.17865.L.str.7865.L.str.16865.L.str.6865.L.str.15865.L.str.5865.L.str.14865.L.str.4865.L.str.13865.L.str.3865.L.str.12865.L.str.2865.L.str.11865.L.str.1865.L.str.10865.L.str.865.L.str.19765.L.str.9765.L.str.18765.L.str.8765.L.str.17765.L.str.7765.L.str.16765.L.str.6765.L.str.15765.L.str.5765.L.str.14765.L.str.4765.L.str.13765.L.str.3765.L.str.12765.L.str.2765.L.str.11765.L.str.1765.L.str.10765.L.str.765.L.str.19665.L.str.9665.L.str.18665.L.str.8665.L.str.17665.L.str.7665.L.str.16665.L.str.6665.L.str.15665.L.str.5665.L.str.14665.L.str.4665.L.str.13665.L.str.3665.L.str.12665.L.str.2665.L.str.11665.L.str.1665.L.str.10665.L.str.665.L.str.19565.L.str.9565.L.str.18565.L.str.8565.L.str.17565.L.str.7565.L.str.16565.L.str.6565.L.str.15565.L.str.5565.L.str.14565.L.str.4565.L.str.13565.L.str.3565.L.str.12565.L.str.2565.L.str.11565.L.str.1565.L.str.10565.L.str.565.L.str.19465.L.str.9465.L.str.18465.L.str.8465.L.str.17465.L.str.7465.L.str.16465.L.str.6465.L.str.15465.L.str.5465.L.str.14465.L.str.4465.L.str.13465.L.str.3465.L.str.12465.L.str.2465.L.str.11465.L.str.1465.L.str.10465.L.str.465.L.str.19365.L.str.9365.L.str.18365.L.str.8365.L.str.17365.L.str.7365.L.str.16365.L.str.6365.L.str.15365.L.str.5365.L.str.14365.L.str.4365.L.str.13365.L.str.3365.L.str.12365.L.str.2365.L.str.11365.L.str.1365.L.str.10365.L.str.365.L.str.19265.L.str.9265.L.str.18265.L.str.8265.L.str.17265.L.str.7265.L.str.16265.L.str.6265.L.str.15265.L.str.5265.L.str.14265.L.str.4265.L.str.13265.L.str.3265.L.str.12265.L.str.2265.L.str.11265.L.str.1265.L.str.10265.L.str.265.L.str.19165.L.str.9165.L.str.18165.L.str.8165.L.str.17165.L.str.7165.L.str.16165.L.str.6165.L.str.15165.L.str.5165.L.str.14165.L.str.4165.L.str.13165.L.str.3165.L.str.12165.L.str.2165.L.str.11165.L.str.1165.L.str.10165.L.str.165.L.str.19065.L.str.9065.L.str.18065.L.str.8065.L.str.17065.L.str.7065.L.str.16065.L.str.6065.L.str.15065.L.str.5065.L.str.14065.L.str.4065.L.str.13065.L.str.3065.L.str.12065.L.str.2065.L.str.11065.L.str.1065.L.str.10065.L.str.65.L.str.9955.L.str.18955.L.str.8955.L.str.17955.L.str.7955.L.str.16955.L.str.6955.L.str.15955.L.str.5955.L.str.14955.L.str.4955.L.str.13955.L.str.3955.L.str.12955.L.str.2955.L.str.11955.L.str.1955.L.str.10955.L.str.955.L.str.19855.L.str.9855.L.str.18855.L.str.8855.L.str.17855.L.str.7855.L.str.16855.L.str.6855.L.str.15855.L.str.5855.L.str.14855.L.str.4855.L.str.13855.L.str.3855.L.str.12855.L.str.2855.L.str.11855.L.str.1855.L.str.10855.L.str.855.L.str.19755.L.str.9755.L.str.18755.L.str.8755.L.str.17755.L.str.7755.L.str.16755.L.str.6755.L.str.15755.L.str.5755.L.str.14755.L.str.4755.L.str.13755.L.str.3755.L.str.12755.L.str.2755.L.str.11755.L.str.1755.L.str.10755.L.str.755.L.str.19655.L.str.9655.L.str.18655.L.str.8655.L.str.17655.L.str.7655.L.str.16655.L.str.6655.L.str.15655.L.str.5655.L.str.14655.L.str.4655.L.str.13655.L.str.3655.L.str.12655.L.str.2655.L.str.11655.L.str.1655.L.str.10655.L.str.655.L.str.19555.L.str.9555.L.str.18555.L.str.8555.L.str.17555.L.str.7555.L.str.16555.L.str.6555.L.str.15555.L.str.5555.L.str.14555.L.str.4555.L.str.13555.L.str.3555.L.str.12555.L.str.2555.L.str.11555.L.str.1555.L.str.10555.L.str.555.L.str.19455.L.str.9455.L.str.18455.L.str.8455.L.str.17455.L.str.7455.L.str.16455.L.str.6455.L.str.15455.L.str.5455.L.str.14455.L.str.4455.L.str.13455.L.str.3455.L.str.12455.L.str.2455.L.str.11455.L.str.1455.L.str.10455.L.str.455.L.str.19355.L.str.9355.L.str.18355.L.str.8355.L.str.17355.L.str.7355.L.str.16355.L.str.6355.L.str.15355.L.str.5355.L.str.14355.L.str.4355.L.str.13355.L.str.3355.L.str.12355.L.str.2355.L.str.11355.L.str.1355.L.str.10355.L.str.355.L.str.19255.L.str.9255.L.str.18255.L.str.8255.L.str.17255.L.str.7255.L.str.16255.L.str.6255.L.str.15255.L.str.5255.L.str.14255.L.str.4255.L.str.13255.L.str.3255.L.str.12255.L.str.2255.L.str.11255.L.str.1255.L.str.10255.L.str.255.L.str.19155.L.str.9155.L.str.18155.L.str.8155.L.str.17155.L.str.7155.L.str.16155.L.str.6155.L.str.15155.L.str.5155.L.str.14155.L.str.4155.L.str.13155.L.str.3155.L.str.12155.L.str.2155.L.str.11155.L.str.1155.L.str.10155.L.str.155.L.str.19055.L.str.9055.L.str.18055.L.str.8055.L.str.17055.L.str.7055.L.str.16055.L.str.6055.L.str.15055.L.str.5055.L.str.14055.L.str.4055.L.str.13055.L.str.3055.L.str.12055.L.str.2055.L.str.11055.L.str.1055.L.str.10055.L.str.55.L.str.9945.L.str.18945.L.str.8945.L.str.17945.L.str.7945.L.str.16945.L.str.6945.L.str.15945.L.str.5945.L.str.14945.L.str.4945.L.str.13945.L.str.3945.L.str.12945.L.str.2945.L.str.11945.L.str.1945.L.str.10945.L.str.945.L.str.19845.L.str.9845.L.str.18845.L.str.8845.L.str.17845.L.str.7845.L.str.16845.L.str.6845.L.str.15845.L.str.5845.L.str.14845.L.str.4845.L.str.13845.L.str.3845.L.str.12845.L.str.2845.L.str.11845.L.str.1845.L.str.10845.L.str.845.L.str.19745.L.str.9745.L.str.18745.L.str.8745.L.str.17745.L.str.7745.L.str.16745.L.str.6745.L.str.15745.L.str.5745.L.str.14745.L.str.4745.L.str.13745.L.str.3745.L.str.12745.L.str.2745.L.str.11745.L.str.1745.L.str.10745.L.str.745.L.str.19645.L.str.9645.L.str.18645.L.str.8645.L.str.17645.L.str.7645.L.str.16645.L.str.6645.L.str.15645.L.str.5645.L.str.14645.L.str.4645.L.str.13645.L.str.3645.L.str.12645.L.str.2645.L.str.11645.L.str.1645.L.str.10645.L.str.645.L.str.19545.L.str.9545.L.str.18545.L.str.8545.L.str.17545.L.str.7545.L.str.16545.L.str.6545.L.str.15545.L.str.5545.L.str.14545.L.str.4545.L.str.13545.L.str.3545.L.str.12545.L.str.2545.L.str.11545.L.str.1545.L.str.10545.L.str.545.L.str.19445.L.str.9445.L.str.18445.L.str.8445.L.str.17445.L.str.7445.L.str.16445.L.str.6445.L.str.15445.L.str.5445.L.str.14445.L.str.4445.L.str.13445.L.str.3445.L.str.12445.L.str.2445.L.str.11445.L.str.1445.L.str.10445.L.str.445.L.str.19345.L.str.9345.L.str.18345.L.str.8345.L.str.17345.L.str.7345.L.str.16345.L.str.6345.L.str.15345.L.str.5345.L.str.14345.L.str.4345.L.str.13345.L.str.3345.L.str.12345.L.str.2345.L.str.11345.L.str.1345.L.str.10345.L.str.345.L.str.19245.L.str.9245.L.str.18245.L.str.8245.L.str.17245.L.str.7245.L.str.16245.L.str.6245.L.str.15245.L.str.5245.L.str.14245.L.str.4245.L.str.13245.L.str.3245.L.str.12245.L.str.2245.L.str.11245.L.str.1245.L.str.10245.L.str.245.L.str.19145.L.str.9145.L.str.18145.L.str.8145.L.str.17145.L.str.7145.L.str.16145.L.str.6145.L.str.15145.L.str.5145.L.str.14145.L.str.4145.L.str.13145.L.str.3145.L.str.12145.L.str.2145.L.str.11145.L.str.1145.L.str.10145.L.str.145.L.str.19045.L.str.9045.L.str.18045.L.str.8045.L.str.17045.L.str.7045.L.str.16045.L.str.6045.L.str.15045.L.str.5045.L.str.14045.L.str.4045.L.str.13045.L.str.3045.L.str.12045.L.str.2045.L.str.11045.L.str.1045.L.str.10045.L.str.45.L.str.9935.L.str.18935.L.str.8935.L.str.17935.L.str.7935.L.str.16935.L.str.6935.L.str.15935.L.str.5935.L.str.14935.L.str.4935.L.str.13935.L.str.3935.L.str.12935.L.str.2935.L.str.11935.L.str.1935.L.str.10935.L.str.935.L.str.19835.L.str.9835.L.str.18835.L.str.8835.L.str.17835.L.str.7835.L.str.16835.L.str.6835.L.str.15835.L.str.5835.L.str.14835.L.str.4835.L.str.13835.L.str.3835.L.str.12835.L.str.2835.L.str.11835.L.str.1835.L.str.10835.L.str.835.L.str.19735.L.str.9735.L.str.18735.L.str.8735.L.str.17735.L.str.7735.L.str.16735.L.str.6735.L.str.15735.L.str.5735.L.str.14735.L.str.4735.L.str.13735.L.str.3735.L.str.12735.L.str.2735.L.str.11735.L.str.1735.L.str.10735.L.str.735.L.str.19635.L.str.9635.L.str.18635.L.str.8635.L.str.17635.L.str.7635.L.str.16635.L.str.6635.L.str.15635.L.str.5635.L.str.14635.L.str.4635.L.str.13635.L.str.3635.L.str.12635.L.str.2635.L.str.11635.L.str.1635.L.str.10635.L.str.635.L.str.19535.L.str.9535.L.str.18535.L.str.8535.L.str.17535.L.str.7535.L.str.16535.L.str.6535.L.str.15535.L.str.5535.L.str.14535.L.str.4535.L.str.13535.L.str.3535.L.str.12535.L.str.2535.L.str.11535.L.str.1535.L.str.10535.L.str.535.L.str.19435.L.str.9435.L.str.18435.L.str.8435.L.str.17435.L.str.7435.L.str.16435.L.str.6435.L.str.15435.L.str.5435.L.str.14435.L.str.4435.L.str.13435.L.str.3435.L.str.12435.L.str.2435.L.str.11435.L.str.1435.L.str.10435.L.str.435.L.str.19335.L.str.9335.L.str.18335.L.str.8335.L.str.17335.L.str.7335.L.str.16335.L.str.6335.L.str.15335.L.str.5335.L.str.14335.L.str.4335.L.str.13335.L.str.3335.L.str.12335.L.str.2335.L.str.11335.L.str.1335.L.str.10335.L.str.335.L.str.19235.L.str.9235.L.str.18235.L.str.8235.L.str.17235.L.str.7235.L.str.16235.L.str.6235.L.str.15235.L.str.5235.L.str.14235.L.str.4235.L.str.13235.L.str.3235.L.str.12235.L.str.2235.L.str.11235.L.str.1235.L.str.10235.L.str.235.L.str.19135.L.str.9135.L.str.18135.L.str.8135.L.str.17135.L.str.7135.L.str.16135.L.str.6135.L.str.15135.L.str.5135.L.str.14135.L.str.4135.L.str.13135.L.str.3135.L.str.12135.L.str.2135.L.str.11135.L.str.1135.L.str.10135.L.str.135.L.str.19035.L.str.9035.L.str.18035.L.str.8035.L.str.17035.L.str.7035.L.str.16035.L.str.6035.L.str.15035.L.str.5035.L.str.14035.L.str.4035.L.str.13035.L.str.3035.L.str.12035.L.str.2035.L.str.11035.L.str.1035.L.str.10035.L.str.35.L.str.9925.L.str.18925.L.str.8925.L.str.17925.L.str.7925.L.str.16925.L.str.6925.L.str.15925.L.str.5925.L.str.14925.L.str.4925.L.str.13925.L.str.3925.L.str.12925.L.str.2925.L.str.11925.L.str.1925.L.str.10925.L.str.925.L.str.19825.L.str.9825.L.str.18825.L.str.8825.L.str.17825.L.str.7825.L.str.16825.L.str.6825.L.str.15825.L.str.5825.L.str.14825.L.str.4825.L.str.13825.L.str.3825.L.str.12825.L.str.2825.L.str.11825.L.str.1825.L.str.10825.L.str.825.L.str.19725.L.str.9725.L.str.18725.L.str.8725.L.str.17725.L.str.7725.L.str.16725.L.str.6725.L.str.15725.L.str.5725.L.str.14725.L.str.4725.L.str.13725.L.str.3725.L.str.12725.L.str.2725.L.str.11725.L.str.1725.L.str.10725.L.str.725.L.str.19625.L.str.9625.L.str.18625.L.str.8625.L.str.17625.L.str.7625.L.str.16625.L.str.6625.L.str.15625.L.str.5625.L.str.14625.L.str.4625.L.str.13625.L.str.3625.L.str.12625.L.str.2625.L.str.11625.L.str.1625.L.str.10625.L.str.625.L.str.19525.L.str.9525.L.str.18525.L.str.8525.L.str.17525.L.str.7525.L.str.16525.L.str.6525.L.str.15525.L.str.5525.L.str.14525.L.str.4525.L.str.13525.L.str.3525.L.str.12525.L.str.2525.L.str.11525.L.str.1525.L.str.10525.L.str.525.L.str.19425.L.str.9425.L.str.18425.L.str.8425.L.str.17425.L.str.7425.L.str.16425.L.str.6425.L.str.15425.L.str.5425.L.str.14425.L.str.4425.L.str.13425.L.str.3425.L.str.12425.L.str.2425.L.str.11425.L.str.1425.L.str.10425.L.str.425.L.str.19325.L.str.9325.L.str.18325.L.str.8325.L.str.17325.L.str.7325.L.str.16325.L.str.6325.L.str.15325.L.str.5325.L.str.14325.L.str.4325.L.str.13325.L.str.3325.L.str.12325.L.str.2325.L.str.11325.L.str.1325.L.str.10325.L.str.325.L.str.19225.L.str.9225.L.str.18225.L.str.8225.L.str.17225.L.str.7225.L.str.16225.L.str.6225.L.str.15225.L.str.5225.L.str.14225.L.str.4225.L.str.13225.L.str.3225.L.str.12225.L.str.2225.L.str.11225.L.str.1225.L.str.10225.L.str.225.L.str.19125.L.str.9125.L.str.18125.L.str.8125.L.str.17125.L.str.7125.L.str.16125.L.str.6125.L.str.15125.L.str.5125.L.str.14125.L.str.4125.L.str.13125.L.str.3125.L.str.12125.L.str.2125.L.str.11125.L.str.1125.L.str.10125.L.str.125.L.str.19025.L.str.9025.L.str.18025.L.str.8025.L.str.17025.L.str.7025.L.str.16025.L.str.6025.L.str.15025.L.str.5025.L.str.14025.L.str.4025.L.str.13025.L.str.3025.L.str.12025.L.str.2025.L.str.11025.L.str.1025.L.str.10025.L.str.25.L.str.9915.L.str.18915.L.str.8915.L.str.17915.L.str.7915.L.str.16915.L.str.6915.L.str.15915.L.str.5915.L.str.14915.L.str.4915.L.str.13915.L.str.3915.L.str.12915.L.str.2915.L.str.11915.L.str.1915.L.str.10915.L.str.915.L.str.19815.L.str.9815.L.str.18815.L.str.8815.L.str.17815.L.str.7815.L.str.16815.L.str.6815.L.str.15815.L.str.5815.L.str.14815.L.str.4815.L.str.13815.L.str.3815.L.str.12815.L.str.2815.L.str.11815.L.str.1815.L.str.10815.L.str.815.L.str.19715.L.str.9715.L.str.18715.L.str.8715.L.str.17715.L.str.7715.L.str.16715.L.str.6715.L.str.15715.L.str.5715.L.str.14715.L.str.4715.L.str.13715.L.str.3715.L.str.12715.L.str.2715.L.str.11715.L.str.1715.L.str.10715.L.str.715.L.str.19615.L.str.9615.L.str.18615.L.str.8615.L.str.17615.L.str.7615.L.str.16615.L.str.6615.L.str.15615.L.str.5615.L.str.14615.L.str.4615.L.str.13615.L.str.3615.L.str.12615.L.str.2615.L.str.11615.L.str.1615.L.str.10615.L.str.615.L.str.19515.L.str.9515.L.str.18515.L.str.8515.L.str.17515.L.str.7515.L.str.16515.L.str.6515.L.str.15515.L.str.5515.L.str.14515.L.str.4515.L.str.13515.L.str.3515.L.str.12515.L.str.2515.L.str.11515.L.str.1515.L.str.10515.L.str.515.L.str.19415.L.str.9415.L.str.18415.L.str.8415.L.str.17415.L.str.7415.L.str.16415.L.str.6415.L.str.15415.L.str.5415.L.str.14415.L.str.4415.L.str.13415.L.str.3415.L.str.12415.L.str.2415.L.str.11415.L.str.1415.L.str.10415.L.str.415.L.str.19315.L.str.9315.L.str.18315.L.str.8315.L.str.17315.L.str.7315.L.str.16315.L.str.6315.L.str.15315.L.str.5315.L.str.14315.L.str.4315.L.str.13315.L.str.3315.L.str.12315.L.str.2315.L.str.11315.L.str.1315.L.str.10315.L.str.315.L.str.19215.L.str.9215.L.str.18215.L.str.8215.L.str.17215.L.str.7215.L.str.16215.L.str.6215.L.str.15215.L.str.5215.L.str.14215.L.str.4215.L.str.13215.L.str.3215.L.str.12215.L.str.2215.L.str.11215.L.str.1215.L.str.10215.L.str.215.L.str.19115.L.str.9115.L.str.18115.L.str.8115.L.str.17115.L.str.7115.L.str.16115.L.str.6115.L.str.15115.L.str.5115.L.str.14115.L.str.4115.L.str.13115.L.str.3115.L.str.12115.L.str.2115.L.str.11115.L.str.1115.L.str.10115.L.str.115.L.str.19015.L.str.9015.L.str.18015.L.str.8015.L.str.17015.L.str.7015.L.str.16015.L.str.6015.L.str.15015.L.str.5015.L.str.14015.L.str.4015.L.str.13015.L.str.3015.L.str.12015.L.str.2015.L.str.11015.L.str.1015.L.str.10015.L.str.15.L.str.9905.L.str.18905.L.str.8905.L.str.17905.L.str.7905.L.str.16905.L.str.6905.L.str.15905.L.str.5905.L.str.14905.L.str.4905.L.str.13905.L.str.3905.L.str.12905.L.str.2905.L.str.11905.L.str.1905.L.str.10905.L.str.905.L.str.19805.L.str.9805.L.str.18805.L.str.8805.L.str.17805.L.str.7805.L.str.16805.L.str.6805.L.str.15805.L.str.5805.L.str.14805.L.str.4805.L.str.13805.L.str.3805.L.str.12805.L.str.2805.L.str.11805.L.str.1805.L.str.10805.L.str.805.L.str.19705.L.str.9705.L.str.18705.L.str.8705.L.str.17705.L.str.7705.L.str.16705.L.str.6705.L.str.15705.L.str.5705.L.str.14705.L.str.4705.L.str.13705.L.str.3705.L.str.12705.L.str.2705.L.str.11705.L.str.1705.L.str.10705.L.str.705.L.str.19605.L.str.9605.L.str.18605.L.str.8605.L.str.17605.L.str.7605.L.str.16605.L.str.6605.L.str.15605.L.str.5605.L.str.14605.L.str.4605.L.str.13605.L.str.3605.L.str.12605.L.str.2605.L.str.11605.L.str.1605.L.str.10605.L.str.605.L.str.19505.L.str.9505.L.str.18505.L.str.8505.L.str.17505.L.str.7505.L.str.16505.L.str.6505.L.str.15505.L.str.5505.L.str.14505.L.str.4505.L.str.13505.L.str.3505.L.str.12505.L.str.2505.L.str.11505.L.str.1505.L.str.10505.L.str.505.L.str.19405.L.str.9405.L.str.18405.L.str.8405.L.str.17405.L.str.7405.L.str.16405.L.str.6405.L.str.15405.L.str.5405.L.str.14405.L.str.4405.L.str.13405.L.str.3405.L.str.12405.L.str.2405.L.str.11405.L.str.1405.L.str.10405.L.str.405.L.str.19305.L.str.9305.L.str.18305.L.str.8305.L.str.17305.L.str.7305.L.str.16305.L.str.6305.L.str.15305.L.str.5305.L.str.14305.L.str.4305.L.str.13305.L.str.3305.L.str.12305.L.str.2305.L.str.11305.L.str.1305.L.str.10305.L.str.305.L.str.19205.L.str.9205.L.str.18205.L.str.8205.L.str.17205.L.str.7205.L.str.16205.L.str.6205.L.str.15205.L.str.5205.L.str.14205.L.str.4205.L.str.13205.L.str.3205.L.str.12205.L.str.2205.L.str.11205.L.str.1205.L.str.10205.L.str.205.L.str.19105.L.str.9105.L.str.18105.L.str.8105.L.str.17105.L.str.7105.L.str.16105.L.str.6105.L.str.15105.L.str.5105.L.str.14105.L.str.4105.L.str.13105.L.str.3105.L.str.12105.L.str.2105.L.str.11105.L.str.1105.L.str.10105.L.str.105.L.str.19005.L.str.9005.L.str.18005.L.str.8005.L.str.17005.L.str.7005.L.str.16005.L.str.6005.L.str.15005.L.str.5005.L.str.14005.L.str.4005.L.str.13005.L.str.3005.L.str.12005.L.str.2005.L.str.11005.L.str.1005.L.str.10005.L.str.5.L.str.9994.L.str.18994.L.str.8994.L.str.17994.L.str.7994.L.str.16994.L.str.6994.L.str.15994.L.str.5994.L.str.14994.L.str.4994.L.str.13994.L.str.3994.L.str.12994.L.str.2994.L.str.11994.L.str.1994.L.str.10994.L.str.994.L.str.9894.L.str.18894.L.str.8894.L.str.17894.L.str.7894.L.str.16894.L.str.6894.L.str.15894.L.str.5894.L.str.14894.L.str.4894.L.str.13894.L.str.3894.L.str.12894.L.str.2894.L.str.11894.L.str.1894.L.str.10894.L.str.894.L.str.19794.L.str.9794.L.str.18794.L.str.8794.L.str.17794.L.str.7794.L.str.16794.L.str.6794.L.str.15794.L.str.5794.L.str.14794.L.str.4794.L.str.13794.L.str.3794.L.str.12794.L.str.2794.L.str.11794.L.str.1794.L.str.10794.L.str.794.L.str.19694.L.str.9694.L.str.18694.L.str.8694.L.str.17694.L.str.7694.L.str.16694.L.str.6694.L.str.15694.L.str.5694.L.str.14694.L.str.4694.L.str.13694.L.str.3694.L.str.12694.L.str.2694.L.str.11694.L.str.1694.L.str.10694.L.str.694.L.str.19594.L.str.9594.L.str.18594.L.str.8594.L.str.17594.L.str.7594.L.str.16594.L.str.6594.L.str.15594.L.str.5594.L.str.14594.L.str.4594.L.str.13594.L.str.3594.L.str.12594.L.str.2594.L.str.11594.L.str.1594.L.str.10594.L.str.594.L.str.19494.L.str.9494.L.str.18494.L.str.8494.L.str.17494.L.str.7494.L.str.16494.L.str.6494.L.str.15494.L.str.5494.L.str.14494.L.str.4494.L.str.13494.L.str.3494.L.str.12494.L.str.2494.L.str.11494.L.str.1494.L.str.10494.L.str.494.L.str.19394.L.str.9394.L.str.18394.L.str.8394.L.str.17394.L.str.7394.L.str.16394.L.str.6394.L.str.15394.L.str.5394.L.str.14394.L.str.4394.L.str.13394.L.str.3394.L.str.12394.L.str.2394.L.str.11394.L.str.1394.L.str.10394.L.str.394.L.str.19294.L.str.9294.L.str.18294.L.str.8294.L.str.17294.L.str.7294.L.str.16294.L.str.6294.L.str.15294.L.str.5294.L.str.14294.L.str.4294.L.str.13294.L.str.3294.L.str.12294.L.str.2294.L.str.11294.L.str.1294.L.str.10294.L.str.294.L.str.19194.L.str.9194.L.str.18194.L.str.8194.L.str.17194.L.str.7194.L.str.16194.L.str.6194.L.str.15194.L.str.5194.L.str.14194.L.str.4194.L.str.13194.L.str.3194.L.str.12194.L.str.2194.L.str.11194.L.str.1194.L.str.10194.L.str.194.L.str.19094.L.str.9094.L.str.18094.L.str.8094.L.str.17094.L.str.7094.L.str.16094.L.str.6094.L.str.15094.L.str.5094.L.str.14094.L.str.4094.L.str.13094.L.str.3094.L.str.12094.L.str.2094.L.str.11094.L.str.1094.L.str.10094.L.str.94.L.str.9984.L.str.18984.L.str.8984.L.str.17984.L.str.7984.L.str.16984.L.str.6984.L.str.15984.L.str.5984.L.str.14984.L.str.4984.L.str.13984.L.str.3984.L.str.12984.L.str.2984.L.str.11984.L.str.1984.L.str.10984.L.str.984.L.str.9884.L.str.18884.L.str.8884.L.str.17884.L.str.7884.L.str.16884.L.str.6884.L.str.15884.L.str.5884.L.str.14884.L.str.4884.L.str.13884.L.str.3884.L.str.12884.L.str.2884.L.str.11884.L.str.1884.L.str.10884.L.str.884.L.str.19784.L.str.9784.L.str.18784.L.str.8784.L.str.17784.L.str.7784.L.str.16784.L.str.6784.L.str.15784.L.str.5784.L.str.14784.L.str.4784.L.str.13784.L.str.3784.L.str.12784.L.str.2784.L.str.11784.L.str.1784.L.str.10784.L.str.784.L.str.19684.L.str.9684.L.str.18684.L.str.8684.L.str.17684.L.str.7684.L.str.16684.L.str.6684.L.str.15684.L.str.5684.L.str.14684.L.str.4684.L.str.13684.L.str.3684.L.str.12684.L.str.2684.L.str.11684.L.str.1684.L.str.10684.L.str.684.L.str.19584.L.str.9584.L.str.18584.L.str.8584.L.str.17584.L.str.7584.L.str.16584.L.str.6584.L.str.15584.L.str.5584.L.str.14584.L.str.4584.L.str.13584.L.str.3584.L.str.12584.L.str.2584.L.str.11584.L.str.1584.L.str.10584.L.str.584.L.str.19484.L.str.9484.L.str.18484.L.str.8484.L.str.17484.L.str.7484.L.str.16484.L.str.6484.L.str.15484.L.str.5484.L.str.14484.L.str.4484.L.str.13484.L.str.3484.L.str.12484.L.str.2484.L.str.11484.L.str.1484.L.str.10484.L.str.484.L.str.19384.L.str.9384.L.str.18384.L.str.8384.L.str.17384.L.str.7384.L.str.16384.L.str.6384.L.str.15384.L.str.5384.L.str.14384.L.str.4384.L.str.13384.L.str.3384.L.str.12384.L.str.2384.L.str.11384.L.str.1384.L.str.10384.L.str.384.L.str.19284.L.str.9284.L.str.18284.L.str.8284.L.str.17284.L.str.7284.L.str.16284.L.str.6284.L.str.15284.L.str.5284.L.str.14284.L.str.4284.L.str.13284.L.str.3284.L.str.12284.L.str.2284.L.str.11284.L.str.1284.L.str.10284.L.str.284.L.str.19184.L.str.9184.L.str.18184.L.str.8184.L.str.17184.L.str.7184.L.str.16184.L.str.6184.L.str.15184.L.str.5184.L.str.14184.L.str.4184.L.str.13184.L.str.3184.L.str.12184.L.str.2184.L.str.11184.L.str.1184.L.str.10184.L.str.184.L.str.19084.L.str.9084.L.str.18084.L.str.8084.L.str.17084.L.str.7084.L.str.16084.L.str.6084.L.str.15084.L.str.5084.L.str.14084.L.str.4084.L.str.13084.L.str.3084.L.str.12084.L.str.2084.L.str.11084.L.str.1084.L.str.10084.L.str.84.L.str.9974.L.str.18974.L.str.8974.L.str.17974.L.str.7974.L.str.16974.L.str.6974.L.str.15974.L.str.5974.L.str.14974.L.str.4974.L.str.13974.L.str.3974.L.str.12974.L.str.2974.L.str.11974.L.str.1974.L.str.10974.L.str.974.L.str.9874.L.str.18874.L.str.8874.L.str.17874.L.str.7874.L.str.16874.L.str.6874.L.str.15874.L.str.5874.L.str.14874.L.str.4874.L.str.13874.L.str.3874.L.str.12874.L.str.2874.L.str.11874.L.str.1874.L.str.10874.L.str.874.L.str.19774.L.str.9774.L.str.18774.L.str.8774.L.str.17774.L.str.7774.L.str.16774.L.str.6774.L.str.15774.L.str.5774.L.str.14774.L.str.4774.L.str.13774.L.str.3774.L.str.12774.L.str.2774.L.str.11774.L.str.1774.L.str.10774.L.str.774.L.str.19674.L.str.9674.L.str.18674.L.str.8674.L.str.17674.L.str.7674.L.str.16674.L.str.6674.L.str.15674.L.str.5674.L.str.14674.L.str.4674.L.str.13674.L.str.3674.L.str.12674.L.str.2674.L.str.11674.L.str.1674.L.str.10674.L.str.674.L.str.19574.L.str.9574.L.str.18574.L.str.8574.L.str.17574.L.str.7574.L.str.16574.L.str.6574.L.str.15574.L.str.5574.L.str.14574.L.str.4574.L.str.13574.L.str.3574.L.str.12574.L.str.2574.L.str.11574.L.str.1574.L.str.10574.L.str.574.L.str.19474.L.str.9474.L.str.18474.L.str.8474.L.str.17474.L.str.7474.L.str.16474.L.str.6474.L.str.15474.L.str.5474.L.str.14474.L.str.4474.L.str.13474.L.str.3474.L.str.12474.L.str.2474.L.str.11474.L.str.1474.L.str.10474.L.str.474.L.str.19374.L.str.9374.L.str.18374.L.str.8374.L.str.17374.L.str.7374.L.str.16374.L.str.6374.L.str.15374.L.str.5374.L.str.14374.L.str.4374.L.str.13374.L.str.3374.L.str.12374.L.str.2374.L.str.11374.L.str.1374.L.str.10374.L.str.374.L.str.19274.L.str.9274.L.str.18274.L.str.8274.L.str.17274.L.str.7274.L.str.16274.L.str.6274.L.str.15274.L.str.5274.L.str.14274.L.str.4274.L.str.13274.L.str.3274.L.str.12274.L.str.2274.L.str.11274.L.str.1274.L.str.10274.L.str.274.L.str.19174.L.str.9174.L.str.18174.L.str.8174.L.str.17174.L.str.7174.L.str.16174.L.str.6174.L.str.15174.L.str.5174.L.str.14174.L.str.4174.L.str.13174.L.str.3174.L.str.12174.L.str.2174.L.str.11174.L.str.1174.L.str.10174.L.str.174.L.str.19074.L.str.9074.L.str.18074.L.str.8074.L.str.17074.L.str.7074.L.str.16074.L.str.6074.L.str.15074.L.str.5074.L.str.14074.L.str.4074.L.str.13074.L.str.3074.L.str.12074.L.str.2074.L.str.11074.L.str.1074.L.str.10074.L.str.74.L.str.9964.L.str.18964.L.str.8964.L.str.17964.L.str.7964.L.str.16964.L.str.6964.L.str.15964.L.str.5964.L.str.14964.L.str.4964.L.str.13964.L.str.3964.L.str.12964.L.str.2964.L.str.11964.L.str.1964.L.str.10964.L.str.964.L.str.19864.L.str.9864.L.str.18864.L.str.8864.L.str.17864.L.str.7864.L.str.16864.L.str.6864.L.str.15864.L.str.5864.L.str.14864.L.str.4864.L.str.13864.L.str.3864.L.str.12864.L.str.2864.L.str.11864.L.str.1864.L.str.10864.L.str.864.L.str.19764.L.str.9764.L.str.18764.L.str.8764.L.str.17764.L.str.7764.L.str.16764.L.str.6764.L.str.15764.L.str.5764.L.str.14764.L.str.4764.L.str.13764.L.str.3764.L.str.12764.L.str.2764.L.str.11764.L.str.1764.L.str.10764.L.str.764.L.str.19664.L.str.9664.L.str.18664.L.str.8664.L.str.17664.L.str.7664.L.str.16664.L.str.6664.L.str.15664.L.str.5664.L.str.14664.L.str.4664.L.str.13664.L.str.3664.L.str.12664.L.str.2664.L.str.11664.L.str.1664.L.str.10664.L.str.664.L.str.19564.L.str.9564.L.str.18564.L.str.8564.L.str.17564.L.str.7564.L.str.16564.L.str.6564.L.str.15564.L.str.5564.L.str.14564.L.str.4564.L.str.13564.L.str.3564.L.str.12564.L.str.2564.L.str.11564.L.str.1564.L.str.10564.L.str.564.L.str.19464.L.str.9464.L.str.18464.L.str.8464.L.str.17464.L.str.7464.L.str.16464.L.str.6464.L.str.15464.L.str.5464.L.str.14464.L.str.4464.L.str.13464.L.str.3464.L.str.12464.L.str.2464.L.str.11464.L.str.1464.L.str.10464.L.str.464.L.str.19364.L.str.9364.L.str.18364.L.str.8364.L.str.17364.L.str.7364.L.str.16364.L.str.6364.L.str.15364.L.str.5364.L.str.14364.L.str.4364.L.str.13364.L.str.3364.L.str.12364.L.str.2364.L.str.11364.L.str.1364.L.str.10364.L.str.364.L.str.19264.L.str.9264.L.str.18264.L.str.8264.L.str.17264.L.str.7264.L.str.16264.L.str.6264.L.str.15264.L.str.5264.L.str.14264.L.str.4264.L.str.13264.L.str.3264.L.str.12264.L.str.2264.L.str.11264.L.str.1264.L.str.10264.L.str.264.L.str.19164.L.str.9164.L.str.18164.L.str.8164.L.str.17164.L.str.7164.L.str.16164.L.str.6164.L.str.15164.L.str.5164.L.str.14164.L.str.4164.L.str.13164.L.str.3164.L.str.12164.L.str.2164.L.str.11164.L.str.1164.L.str.10164.L.str.164.L.str.19064.L.str.9064.L.str.18064.L.str.8064.L.str.17064.L.str.7064.L.str.16064.L.str.6064.L.str.15064.L.str.5064.L.str.14064.L.str.4064.L.str.13064.L.str.3064.L.str.12064.L.str.2064.L.str.11064.L.str.1064.L.str.10064.L.str.64.L.str.9954.L.str.18954.L.str.8954.L.str.17954.L.str.7954.L.str.16954.L.str.6954.L.str.15954.L.str.5954.L.str.14954.L.str.4954.L.str.13954.L.str.3954.L.str.12954.L.str.2954.L.str.11954.L.str.1954.L.str.10954.L.str.954.L.str.19854.L.str.9854.L.str.18854.L.str.8854.L.str.17854.L.str.7854.L.str.16854.L.str.6854.L.str.15854.L.str.5854.L.str.14854.L.str.4854.L.str.13854.L.str.3854.L.str.12854.L.str.2854.L.str.11854.L.str.1854.L.str.10854.L.str.854.L.str.19754.L.str.9754.L.str.18754.L.str.8754.L.str.17754.L.str.7754.L.str.16754.L.str.6754.L.str.15754.L.str.5754.L.str.14754.L.str.4754.L.str.13754.L.str.3754.L.str.12754.L.str.2754.L.str.11754.L.str.1754.L.str.10754.L.str.754.L.str.19654.L.str.9654.L.str.18654.L.str.8654.L.str.17654.L.str.7654.L.str.16654.L.str.6654.L.str.15654.L.str.5654.L.str.14654.L.str.4654.L.str.13654.L.str.3654.L.str.12654.L.str.2654.L.str.11654.L.str.1654.L.str.10654.L.str.654.L.str.19554.L.str.9554.L.str.18554.L.str.8554.L.str.17554.L.str.7554.L.str.16554.L.str.6554.L.str.15554.L.str.5554.L.str.14554.L.str.4554.L.str.13554.L.str.3554.L.str.12554.L.str.2554.L.str.11554.L.str.1554.L.str.10554.L.str.554.L.str.19454.L.str.9454.L.str.18454.L.str.8454.L.str.17454.L.str.7454.L.str.16454.L.str.6454.L.str.15454.L.str.5454.L.str.14454.L.str.4454.L.str.13454.L.str.3454.L.str.12454.L.str.2454.L.str.11454.L.str.1454.L.str.10454.L.str.454.L.str.19354.L.str.9354.L.str.18354.L.str.8354.L.str.17354.L.str.7354.L.str.16354.L.str.6354.L.str.15354.L.str.5354.L.str.14354.L.str.4354.L.str.13354.L.str.3354.L.str.12354.L.str.2354.L.str.11354.L.str.1354.L.str.10354.L.str.354.L.str.19254.L.str.9254.L.str.18254.L.str.8254.L.str.17254.L.str.7254.L.str.16254.L.str.6254.L.str.15254.L.str.5254.L.str.14254.L.str.4254.L.str.13254.L.str.3254.L.str.12254.L.str.2254.L.str.11254.L.str.1254.L.str.10254.L.str.254.L.str.19154.L.str.9154.L.str.18154.L.str.8154.L.str.17154.L.str.7154.L.str.16154.L.str.6154.L.str.15154.L.str.5154.L.str.14154.L.str.4154.L.str.13154.L.str.3154.L.str.12154.L.str.2154.L.str.11154.L.str.1154.L.str.10154.L.str.154.L.str.19054.L.str.9054.L.str.18054.L.str.8054.L.str.17054.L.str.7054.L.str.16054.L.str.6054.L.str.15054.L.str.5054.L.str.14054.L.str.4054.L.str.13054.L.str.3054.L.str.12054.L.str.2054.L.str.11054.L.str.1054.L.str.10054.L.str.54.L.str.9944.L.str.18944.L.str.8944.L.str.17944.L.str.7944.L.str.16944.L.str.6944.L.str.15944.L.str.5944.L.str.14944.L.str.4944.L.str.13944.L.str.3944.L.str.12944.L.str.2944.L.str.11944.L.str.1944.L.str.10944.L.str.944.L.str.19844.L.str.9844.L.str.18844.L.str.8844.L.str.17844.L.str.7844.L.str.16844.L.str.6844.L.str.15844.L.str.5844.L.str.14844.L.str.4844.L.str.13844.L.str.3844.L.str.12844.L.str.2844.L.str.11844.L.str.1844.L.str.10844.L.str.844.L.str.19744.L.str.9744.L.str.18744.L.str.8744.L.str.17744.L.str.7744.L.str.16744.L.str.6744.L.str.15744.L.str.5744.L.str.14744.L.str.4744.L.str.13744.L.str.3744.L.str.12744.L.str.2744.L.str.11744.L.str.1744.L.str.10744.L.str.744.L.str.19644.L.str.9644.L.str.18644.L.str.8644.L.str.17644.L.str.7644.L.str.16644.L.str.6644.L.str.15644.L.str.5644.L.str.14644.L.str.4644.L.str.13644.L.str.3644.L.str.12644.L.str.2644.L.str.11644.L.str.1644.L.str.10644.L.str.644.L.str.19544.L.str.9544.L.str.18544.L.str.8544.L.str.17544.L.str.7544.L.str.16544.L.str.6544.L.str.15544.L.str.5544.L.str.14544.L.str.4544.L.str.13544.L.str.3544.L.str.12544.L.str.2544.L.str.11544.L.str.1544.L.str.10544.L.str.544.L.str.19444.L.str.9444.L.str.18444.L.str.8444.L.str.17444.L.str.7444.L.str.16444.L.str.6444.L.str.15444.L.str.5444.L.str.14444.L.str.4444.L.str.13444.L.str.3444.L.str.12444.L.str.2444.L.str.11444.L.str.1444.L.str.10444.L.str.444.L.str.19344.L.str.9344.L.str.18344.L.str.8344.L.str.17344.L.str.7344.L.str.16344.L.str.6344.L.str.15344.L.str.5344.L.str.14344.L.str.4344.L.str.13344.L.str.3344.L.str.12344.L.str.2344.L.str.11344.L.str.1344.L.str.10344.L.str.344.L.str.19244.L.str.9244.L.str.18244.L.str.8244.L.str.17244.L.str.7244.L.str.16244.L.str.6244.L.str.15244.L.str.5244.L.str.14244.L.str.4244.L.str.13244.L.str.3244.L.str.12244.L.str.2244.L.str.11244.L.str.1244.L.str.10244.L.str.244.L.str.19144.L.str.9144.L.str.18144.L.str.8144.L.str.17144.L.str.7144.L.str.16144.L.str.6144.L.str.15144.L.str.5144.L.str.14144.L.str.4144.L.str.13144.L.str.3144.L.str.12144.L.str.2144.L.str.11144.L.str.1144.L.str.10144.L.str.144.L.str.19044.L.str.9044.L.str.18044.L.str.8044.L.str.17044.L.str.7044.L.str.16044.L.str.6044.L.str.15044.L.str.5044.L.str.14044.L.str.4044.L.str.13044.L.str.3044.L.str.12044.L.str.2044.L.str.11044.L.str.1044.L.str.10044.L.str.44.L.str.9934.L.str.18934.L.str.8934.L.str.17934.L.str.7934.L.str.16934.L.str.6934.L.str.15934.L.str.5934.L.str.14934.L.str.4934.L.str.13934.L.str.3934.L.str.12934.L.str.2934.L.str.11934.L.str.1934.L.str.10934.L.str.934.L.str.19834.L.str.9834.L.str.18834.L.str.8834.L.str.17834.L.str.7834.L.str.16834.L.str.6834.L.str.15834.L.str.5834.L.str.14834.L.str.4834.L.str.13834.L.str.3834.L.str.12834.L.str.2834.L.str.11834.L.str.1834.L.str.10834.L.str.834.L.str.19734.L.str.9734.L.str.18734.L.str.8734.L.str.17734.L.str.7734.L.str.16734.L.str.6734.L.str.15734.L.str.5734.L.str.14734.L.str.4734.L.str.13734.L.str.3734.L.str.12734.L.str.2734.L.str.11734.L.str.1734.L.str.10734.L.str.734.L.str.19634.L.str.9634.L.str.18634.L.str.8634.L.str.17634.L.str.7634.L.str.16634.L.str.6634.L.str.15634.L.str.5634.L.str.14634.L.str.4634.L.str.13634.L.str.3634.L.str.12634.L.str.2634.L.str.11634.L.str.1634.L.str.10634.L.str.634.L.str.19534.L.str.9534.L.str.18534.L.str.8534.L.str.17534.L.str.7534.L.str.16534.L.str.6534.L.str.15534.L.str.5534.L.str.14534.L.str.4534.L.str.13534.L.str.3534.L.str.12534.L.str.2534.L.str.11534.L.str.1534.L.str.10534.L.str.534.L.str.19434.L.str.9434.L.str.18434.L.str.8434.L.str.17434.L.str.7434.L.str.16434.L.str.6434.L.str.15434.L.str.5434.L.str.14434.L.str.4434.L.str.13434.L.str.3434.L.str.12434.L.str.2434.L.str.11434.L.str.1434.L.str.10434.L.str.434.L.str.19334.L.str.9334.L.str.18334.L.str.8334.L.str.17334.L.str.7334.L.str.16334.L.str.6334.L.str.15334.L.str.5334.L.str.14334.L.str.4334.L.str.13334.L.str.3334.L.str.12334.L.str.2334.L.str.11334.L.str.1334.L.str.10334.L.str.334.L.str.19234.L.str.9234.L.str.18234.L.str.8234.L.str.17234.L.str.7234.L.str.16234.L.str.6234.L.str.15234.L.str.5234.L.str.14234.L.str.4234.L.str.13234.L.str.3234.L.str.12234.L.str.2234.L.str.11234.L.str.1234.L.str.10234.L.str.234.L.str.19134.L.str.9134.L.str.18134.L.str.8134.L.str.17134.L.str.7134.L.str.16134.L.str.6134.L.str.15134.L.str.5134.L.str.14134.L.str.4134.L.str.13134.L.str.3134.L.str.12134.L.str.2134.L.str.11134.L.str.1134.L.str.10134.L.str.134.L.str.19034.L.str.9034.L.str.18034.L.str.8034.L.str.17034.L.str.7034.L.str.16034.L.str.6034.L.str.15034.L.str.5034.L.str.14034.L.str.4034.L.str.13034.L.str.3034.L.str.12034.L.str.2034.L.str.11034.L.str.1034.L.str.10034.L.str.34.L.str.9924.L.str.18924.L.str.8924.L.str.17924.L.str.7924.L.str.16924.L.str.6924.L.str.15924.L.str.5924.L.str.14924.L.str.4924.L.str.13924.L.str.3924.L.str.12924.L.str.2924.L.str.11924.L.str.1924.L.str.10924.L.str.924.L.str.19824.L.str.9824.L.str.18824.L.str.8824.L.str.17824.L.str.7824.L.str.16824.L.str.6824.L.str.15824.L.str.5824.L.str.14824.L.str.4824.L.str.13824.L.str.3824.L.str.12824.L.str.2824.L.str.11824.L.str.1824.L.str.10824.L.str.824.L.str.19724.L.str.9724.L.str.18724.L.str.8724.L.str.17724.L.str.7724.L.str.16724.L.str.6724.L.str.15724.L.str.5724.L.str.14724.L.str.4724.L.str.13724.L.str.3724.L.str.12724.L.str.2724.L.str.11724.L.str.1724.L.str.10724.L.str.724.L.str.19624.L.str.9624.L.str.18624.L.str.8624.L.str.17624.L.str.7624.L.str.16624.L.str.6624.L.str.15624.L.str.5624.L.str.14624.L.str.4624.L.str.13624.L.str.3624.L.str.12624.L.str.2624.L.str.11624.L.str.1624.L.str.10624.L.str.624.L.str.19524.L.str.9524.L.str.18524.L.str.8524.L.str.17524.L.str.7524.L.str.16524.L.str.6524.L.str.15524.L.str.5524.L.str.14524.L.str.4524.L.str.13524.L.str.3524.L.str.12524.L.str.2524.L.str.11524.L.str.1524.L.str.10524.L.str.524.L.str.19424.L.str.9424.L.str.18424.L.str.8424.L.str.17424.L.str.7424.L.str.16424.L.str.6424.L.str.15424.L.str.5424.L.str.14424.L.str.4424.L.str.13424.L.str.3424.L.str.12424.L.str.2424.L.str.11424.L.str.1424.L.str.10424.L.str.424.L.str.19324.L.str.9324.L.str.18324.L.str.8324.L.str.17324.L.str.7324.L.str.16324.L.str.6324.L.str.15324.L.str.5324.L.str.14324.L.str.4324.L.str.13324.L.str.3324.L.str.12324.L.str.2324.L.str.11324.L.str.1324.L.str.10324.L.str.324.L.str.19224.L.str.9224.L.str.18224.L.str.8224.L.str.17224.L.str.7224.L.str.16224.L.str.6224.L.str.15224.L.str.5224.L.str.14224.L.str.4224.L.str.13224.L.str.3224.L.str.12224.L.str.2224.L.str.11224.L.str.1224.L.str.10224.L.str.224.L.str.19124.L.str.9124.L.str.18124.L.str.8124.L.str.17124.L.str.7124.L.str.16124.L.str.6124.L.str.15124.L.str.5124.L.str.14124.L.str.4124.L.str.13124.L.str.3124.L.str.12124.L.str.2124.L.str.11124.L.str.1124.L.str.10124.L.str.124.L.str.19024.L.str.9024.L.str.18024.L.str.8024.L.str.17024.L.str.7024.L.str.16024.L.str.6024.L.str.15024.L.str.5024.L.str.14024.L.str.4024.L.str.13024.L.str.3024.L.str.12024.L.str.2024.L.str.11024.L.str.1024.L.str.10024.L.str.24.L.str.9914.L.str.18914.L.str.8914.L.str.17914.L.str.7914.L.str.16914.L.str.6914.L.str.15914.L.str.5914.L.str.14914.L.str.4914.L.str.13914.L.str.3914.L.str.12914.L.str.2914.L.str.11914.L.str.1914.L.str.10914.L.str.914.L.str.19814.L.str.9814.L.str.18814.L.str.8814.L.str.17814.L.str.7814.L.str.16814.L.str.6814.L.str.15814.L.str.5814.L.str.14814.L.str.4814.L.str.13814.L.str.3814.L.str.12814.L.str.2814.L.str.11814.L.str.1814.L.str.10814.L.str.814.L.str.19714.L.str.9714.L.str.18714.L.str.8714.L.str.17714.L.str.7714.L.str.16714.L.str.6714.L.str.15714.L.str.5714.L.str.14714.L.str.4714.L.str.13714.L.str.3714.L.str.12714.L.str.2714.L.str.11714.L.str.1714.L.str.10714.L.str.714.L.str.19614.L.str.9614.L.str.18614.L.str.8614.L.str.17614.L.str.7614.L.str.16614.L.str.6614.L.str.15614.L.str.5614.L.str.14614.L.str.4614.L.str.13614.L.str.3614.L.str.12614.L.str.2614.L.str.11614.L.str.1614.L.str.10614.L.str.614.L.str.19514.L.str.9514.L.str.18514.L.str.8514.L.str.17514.L.str.7514.L.str.16514.L.str.6514.L.str.15514.L.str.5514.L.str.14514.L.str.4514.L.str.13514.L.str.3514.L.str.12514.L.str.2514.L.str.11514.L.str.1514.L.str.10514.L.str.514.L.str.19414.L.str.9414.L.str.18414.L.str.8414.L.str.17414.L.str.7414.L.str.16414.L.str.6414.L.str.15414.L.str.5414.L.str.14414.L.str.4414.L.str.13414.L.str.3414.L.str.12414.L.str.2414.L.str.11414.L.str.1414.L.str.10414.L.str.414.L.str.19314.L.str.9314.L.str.18314.L.str.8314.L.str.17314.L.str.7314.L.str.16314.L.str.6314.L.str.15314.L.str.5314.L.str.14314.L.str.4314.L.str.13314.L.str.3314.L.str.12314.L.str.2314.L.str.11314.L.str.1314.L.str.10314.L.str.314.L.str.19214.L.str.9214.L.str.18214.L.str.8214.L.str.17214.L.str.7214.L.str.16214.L.str.6214.L.str.15214.L.str.5214.L.str.14214.L.str.4214.L.str.13214.L.str.3214.L.str.12214.L.str.2214.L.str.11214.L.str.1214.L.str.10214.L.str.214.L.str.19114.L.str.9114.L.str.18114.L.str.8114.L.str.17114.L.str.7114.L.str.16114.L.str.6114.L.str.15114.L.str.5114.L.str.14114.L.str.4114.L.str.13114.L.str.3114.L.str.12114.L.str.2114.L.str.11114.L.str.1114.L.str.10114.L.str.114.L.str.19014.L.str.9014.L.str.18014.L.str.8014.L.str.17014.L.str.7014.L.str.16014.L.str.6014.L.str.15014.L.str.5014.L.str.14014.L.str.4014.L.str.13014.L.str.3014.L.str.12014.L.str.2014.L.str.11014.L.str.1014.L.str.10014.L.str.14.L.str.9904.L.str.18904.L.str.8904.L.str.17904.L.str.7904.L.str.16904.L.str.6904.L.str.15904.L.str.5904.L.str.14904.L.str.4904.L.str.13904.L.str.3904.L.str.12904.L.str.2904.L.str.11904.L.str.1904.L.str.10904.L.str.904.L.str.19804.L.str.9804.L.str.18804.L.str.8804.L.str.17804.L.str.7804.L.str.16804.L.str.6804.L.str.15804.L.str.5804.L.str.14804.L.str.4804.L.str.13804.L.str.3804.L.str.12804.L.str.2804.L.str.11804.L.str.1804.L.str.10804.L.str.804.L.str.19704.L.str.9704.L.str.18704.L.str.8704.L.str.17704.L.str.7704.L.str.16704.L.str.6704.L.str.15704.L.str.5704.L.str.14704.L.str.4704.L.str.13704.L.str.3704.L.str.12704.L.str.2704.L.str.11704.L.str.1704.L.str.10704.L.str.704.L.str.19604.L.str.9604.L.str.18604.L.str.8604.L.str.17604.L.str.7604.L.str.16604.L.str.6604.L.str.15604.L.str.5604.L.str.14604.L.str.4604.L.str.13604.L.str.3604.L.str.12604.L.str.2604.L.str.11604.L.str.1604.L.str.10604.L.str.604.L.str.19504.L.str.9504.L.str.18504.L.str.8504.L.str.17504.L.str.7504.L.str.16504.L.str.6504.L.str.15504.L.str.5504.L.str.14504.L.str.4504.L.str.13504.L.str.3504.L.str.12504.L.str.2504.L.str.11504.L.str.1504.L.str.10504.L.str.504.L.str.19404.L.str.9404.L.str.18404.L.str.8404.L.str.17404.L.str.7404.L.str.16404.L.str.6404.L.str.15404.L.str.5404.L.str.14404.L.str.4404.L.str.13404.L.str.3404.L.str.12404.L.str.2404.L.str.11404.L.str.1404.L.str.10404.L.str.404.L.str.19304.L.str.9304.L.str.18304.L.str.8304.L.str.17304.L.str.7304.L.str.16304.L.str.6304.L.str.15304.L.str.5304.L.str.14304.L.str.4304.L.str.13304.L.str.3304.L.str.12304.L.str.2304.L.str.11304.L.str.1304.L.str.10304.L.str.304.L.str.19204.L.str.9204.L.str.18204.L.str.8204.L.str.17204.L.str.7204.L.str.16204.L.str.6204.L.str.15204.L.str.5204.L.str.14204.L.str.4204.L.str.13204.L.str.3204.L.str.12204.L.str.2204.L.str.11204.L.str.1204.L.str.10204.L.str.204.L.str.19104.L.str.9104.L.str.18104.L.str.8104.L.str.17104.L.str.7104.L.str.16104.L.str.6104.L.str.15104.L.str.5104.L.str.14104.L.str.4104.L.str.13104.L.str.3104.L.str.12104.L.str.2104.L.str.11104.L.str.1104.L.str.10104.L.str.104.L.str.19004.L.str.9004.L.str.18004.L.str.8004.L.str.17004.L.str.7004.L.str.16004.L.str.6004.L.str.15004.L.str.5004.L.str.14004.L.str.4004.L.str.13004.L.str.3004.L.str.12004.L.str.2004.L.str.11004.L.str.1004.L.str.10004.L.str.4.L.str.9993.L.str.18993.L.str.8993.L.str.17993.L.str.7993.L.str.16993.L.str.6993.L.str.15993.L.str.5993.L.str.14993.L.str.4993.L.str.13993.L.str.3993.L.str.12993.L.str.2993.L.str.11993.L.str.1993.L.str.10993.L.str.993.L.str.9893.L.str.18893.L.str.8893.L.str.17893.L.str.7893.L.str.16893.L.str.6893.L.str.15893.L.str.5893.L.str.14893.L.str.4893.L.str.13893.L.str.3893.L.str.12893.L.str.2893.L.str.11893.L.str.1893.L.str.10893.L.str.893.L.str.19793.L.str.9793.L.str.18793.L.str.8793.L.str.17793.L.str.7793.L.str.16793.L.str.6793.L.str.15793.L.str.5793.L.str.14793.L.str.4793.L.str.13793.L.str.3793.L.str.12793.L.str.2793.L.str.11793.L.str.1793.L.str.10793.L.str.793.L.str.19693.L.str.9693.L.str.18693.L.str.8693.L.str.17693.L.str.7693.L.str.16693.L.str.6693.L.str.15693.L.str.5693.L.str.14693.L.str.4693.L.str.13693.L.str.3693.L.str.12693.L.str.2693.L.str.11693.L.str.1693.L.str.10693.L.str.693.L.str.19593.L.str.9593.L.str.18593.L.str.8593.L.str.17593.L.str.7593.L.str.16593.L.str.6593.L.str.15593.L.str.5593.L.str.14593.L.str.4593.L.str.13593.L.str.3593.L.str.12593.L.str.2593.L.str.11593.L.str.1593.L.str.10593.L.str.593.L.str.19493.L.str.9493.L.str.18493.L.str.8493.L.str.17493.L.str.7493.L.str.16493.L.str.6493.L.str.15493.L.str.5493.L.str.14493.L.str.4493.L.str.13493.L.str.3493.L.str.12493.L.str.2493.L.str.11493.L.str.1493.L.str.10493.L.str.493.L.str.19393.L.str.9393.L.str.18393.L.str.8393.L.str.17393.L.str.7393.L.str.16393.L.str.6393.L.str.15393.L.str.5393.L.str.14393.L.str.4393.L.str.13393.L.str.3393.L.str.12393.L.str.2393.L.str.11393.L.str.1393.L.str.10393.L.str.393.L.str.19293.L.str.9293.L.str.18293.L.str.8293.L.str.17293.L.str.7293.L.str.16293.L.str.6293.L.str.15293.L.str.5293.L.str.14293.L.str.4293.L.str.13293.L.str.3293.L.str.12293.L.str.2293.L.str.11293.L.str.1293.L.str.10293.L.str.293.L.str.19193.L.str.9193.L.str.18193.L.str.8193.L.str.17193.L.str.7193.L.str.16193.L.str.6193.L.str.15193.L.str.5193.L.str.14193.L.str.4193.L.str.13193.L.str.3193.L.str.12193.L.str.2193.L.str.11193.L.str.1193.L.str.10193.L.str.193.L.str.19093.L.str.9093.L.str.18093.L.str.8093.L.str.17093.L.str.7093.L.str.16093.L.str.6093.L.str.15093.L.str.5093.L.str.14093.L.str.4093.L.str.13093.L.str.3093.L.str.12093.L.str.2093.L.str.11093.L.str.1093.L.str.10093.L.str.93.L.str.9983.L.str.18983.L.str.8983.L.str.17983.L.str.7983.L.str.16983.L.str.6983.L.str.15983.L.str.5983.L.str.14983.L.str.4983.L.str.13983.L.str.3983.L.str.12983.L.str.2983.L.str.11983.L.str.1983.L.str.10983.L.str.983.L.str.9883.L.str.18883.L.str.8883.L.str.17883.L.str.7883.L.str.16883.L.str.6883.L.str.15883.L.str.5883.L.str.14883.L.str.4883.L.str.13883.L.str.3883.L.str.12883.L.str.2883.L.str.11883.L.str.1883.L.str.10883.L.str.883.L.str.19783.L.str.9783.L.str.18783.L.str.8783.L.str.17783.L.str.7783.L.str.16783.L.str.6783.L.str.15783.L.str.5783.L.str.14783.L.str.4783.L.str.13783.L.str.3783.L.str.12783.L.str.2783.L.str.11783.L.str.1783.L.str.10783.L.str.783.L.str.19683.L.str.9683.L.str.18683.L.str.8683.L.str.17683.L.str.7683.L.str.16683.L.str.6683.L.str.15683.L.str.5683.L.str.14683.L.str.4683.L.str.13683.L.str.3683.L.str.12683.L.str.2683.L.str.11683.L.str.1683.L.str.10683.L.str.683.L.str.19583.L.str.9583.L.str.18583.L.str.8583.L.str.17583.L.str.7583.L.str.16583.L.str.6583.L.str.15583.L.str.5583.L.str.14583.L.str.4583.L.str.13583.L.str.3583.L.str.12583.L.str.2583.L.str.11583.L.str.1583.L.str.10583.L.str.583.L.str.19483.L.str.9483.L.str.18483.L.str.8483.L.str.17483.L.str.7483.L.str.16483.L.str.6483.L.str.15483.L.str.5483.L.str.14483.L.str.4483.L.str.13483.L.str.3483.L.str.12483.L.str.2483.L.str.11483.L.str.1483.L.str.10483.L.str.483.L.str.19383.L.str.9383.L.str.18383.L.str.8383.L.str.17383.L.str.7383.L.str.16383.L.str.6383.L.str.15383.L.str.5383.L.str.14383.L.str.4383.L.str.13383.L.str.3383.L.str.12383.L.str.2383.L.str.11383.L.str.1383.L.str.10383.L.str.383.L.str.19283.L.str.9283.L.str.18283.L.str.8283.L.str.17283.L.str.7283.L.str.16283.L.str.6283.L.str.15283.L.str.5283.L.str.14283.L.str.4283.L.str.13283.L.str.3283.L.str.12283.L.str.2283.L.str.11283.L.str.1283.L.str.10283.L.str.283.L.str.19183.L.str.9183.L.str.18183.L.str.8183.L.str.17183.L.str.7183.L.str.16183.L.str.6183.L.str.15183.L.str.5183.L.str.14183.L.str.4183.L.str.13183.L.str.3183.L.str.12183.L.str.2183.L.str.11183.L.str.1183.L.str.10183.L.str.183.L.str.19083.L.str.9083.L.str.18083.L.str.8083.L.str.17083.L.str.7083.L.str.16083.L.str.6083.L.str.15083.L.str.5083.L.str.14083.L.str.4083.L.str.13083.L.str.3083.L.str.12083.L.str.2083.L.str.11083.L.str.1083.L.str.10083.L.str.83.L.str.9973.L.str.18973.L.str.8973.L.str.17973.L.str.7973.L.str.16973.L.str.6973.L.str.15973.L.str.5973.L.str.14973.L.str.4973.L.str.13973.L.str.3973.L.str.12973.L.str.2973.L.str.11973.L.str.1973.L.str.10973.L.str.973.L.str.9873.L.str.18873.L.str.8873.L.str.17873.L.str.7873.L.str.16873.L.str.6873.L.str.15873.L.str.5873.L.str.14873.L.str.4873.L.str.13873.L.str.3873.L.str.12873.L.str.2873.L.str.11873.L.str.1873.L.str.10873.L.str.873.L.str.19773.L.str.9773.L.str.18773.L.str.8773.L.str.17773.L.str.7773.L.str.16773.L.str.6773.L.str.15773.L.str.5773.L.str.14773.L.str.4773.L.str.13773.L.str.3773.L.str.12773.L.str.2773.L.str.11773.L.str.1773.L.str.10773.L.str.773.L.str.19673.L.str.9673.L.str.18673.L.str.8673.L.str.17673.L.str.7673.L.str.16673.L.str.6673.L.str.15673.L.str.5673.L.str.14673.L.str.4673.L.str.13673.L.str.3673.L.str.12673.L.str.2673.L.str.11673.L.str.1673.L.str.10673.L.str.673.L.str.19573.L.str.9573.L.str.18573.L.str.8573.L.str.17573.L.str.7573.L.str.16573.L.str.6573.L.str.15573.L.str.5573.L.str.14573.L.str.4573.L.str.13573.L.str.3573.L.str.12573.L.str.2573.L.str.11573.L.str.1573.L.str.10573.L.str.573.L.str.19473.L.str.9473.L.str.18473.L.str.8473.L.str.17473.L.str.7473.L.str.16473.L.str.6473.L.str.15473.L.str.5473.L.str.14473.L.str.4473.L.str.13473.L.str.3473.L.str.12473.L.str.2473.L.str.11473.L.str.1473.L.str.10473.L.str.473.L.str.19373.L.str.9373.L.str.18373.L.str.8373.L.str.17373.L.str.7373.L.str.16373.L.str.6373.L.str.15373.L.str.5373.L.str.14373.L.str.4373.L.str.13373.L.str.3373.L.str.12373.L.str.2373.L.str.11373.L.str.1373.L.str.10373.L.str.373.L.str.19273.L.str.9273.L.str.18273.L.str.8273.L.str.17273.L.str.7273.L.str.16273.L.str.6273.L.str.15273.L.str.5273.L.str.14273.L.str.4273.L.str.13273.L.str.3273.L.str.12273.L.str.2273.L.str.11273.L.str.1273.L.str.10273.L.str.273.L.str.19173.L.str.9173.L.str.18173.L.str.8173.L.str.17173.L.str.7173.L.str.16173.L.str.6173.L.str.15173.L.str.5173.L.str.14173.L.str.4173.L.str.13173.L.str.3173.L.str.12173.L.str.2173.L.str.11173.L.str.1173.L.str.10173.L.str.173.L.str.19073.L.str.9073.L.str.18073.L.str.8073.L.str.17073.L.str.7073.L.str.16073.L.str.6073.L.str.15073.L.str.5073.L.str.14073.L.str.4073.L.str.13073.L.str.3073.L.str.12073.L.str.2073.L.str.11073.L.str.1073.L.str.10073.L.str.73.L.str.9963.L.str.18963.L.str.8963.L.str.17963.L.str.7963.L.str.16963.L.str.6963.L.str.15963.L.str.5963.L.str.14963.L.str.4963.L.str.13963.L.str.3963.L.str.12963.L.str.2963.L.str.11963.L.str.1963.L.str.10963.L.str.963.L.str.19863.L.str.9863.L.str.18863.L.str.8863.L.str.17863.L.str.7863.L.str.16863.L.str.6863.L.str.15863.L.str.5863.L.str.14863.L.str.4863.L.str.13863.L.str.3863.L.str.12863.L.str.2863.L.str.11863.L.str.1863.L.str.10863.L.str.863.L.str.19763.L.str.9763.L.str.18763.L.str.8763.L.str.17763.L.str.7763.L.str.16763.L.str.6763.L.str.15763.L.str.5763.L.str.14763.L.str.4763.L.str.13763.L.str.3763.L.str.12763.L.str.2763.L.str.11763.L.str.1763.L.str.10763.L.str.763.L.str.19663.L.str.9663.L.str.18663.L.str.8663.L.str.17663.L.str.7663.L.str.16663.L.str.6663.L.str.15663.L.str.5663.L.str.14663.L.str.4663.L.str.13663.L.str.3663.L.str.12663.L.str.2663.L.str.11663.L.str.1663.L.str.10663.L.str.663.L.str.19563.L.str.9563.L.str.18563.L.str.8563.L.str.17563.L.str.7563.L.str.16563.L.str.6563.L.str.15563.L.str.5563.L.str.14563.L.str.4563.L.str.13563.L.str.3563.L.str.12563.L.str.2563.L.str.11563.L.str.1563.L.str.10563.L.str.563.L.str.19463.L.str.9463.L.str.18463.L.str.8463.L.str.17463.L.str.7463.L.str.16463.L.str.6463.L.str.15463.L.str.5463.L.str.14463.L.str.4463.L.str.13463.L.str.3463.L.str.12463.L.str.2463.L.str.11463.L.str.1463.L.str.10463.L.str.463.L.str.19363.L.str.9363.L.str.18363.L.str.8363.L.str.17363.L.str.7363.L.str.16363.L.str.6363.L.str.15363.L.str.5363.L.str.14363.L.str.4363.L.str.13363.L.str.3363.L.str.12363.L.str.2363.L.str.11363.L.str.1363.L.str.10363.L.str.363.L.str.19263.L.str.9263.L.str.18263.L.str.8263.L.str.17263.L.str.7263.L.str.16263.L.str.6263.L.str.15263.L.str.5263.L.str.14263.L.str.4263.L.str.13263.L.str.3263.L.str.12263.L.str.2263.L.str.11263.L.str.1263.L.str.10263.L.str.263.L.str.19163.L.str.9163.L.str.18163.L.str.8163.L.str.17163.L.str.7163.L.str.16163.L.str.6163.L.str.15163.L.str.5163.L.str.14163.L.str.4163.L.str.13163.L.str.3163.L.str.12163.L.str.2163.L.str.11163.L.str.1163.L.str.10163.L.str.163.L.str.19063.L.str.9063.L.str.18063.L.str.8063.L.str.17063.L.str.7063.L.str.16063.L.str.6063.L.str.15063.L.str.5063.L.str.14063.L.str.4063.L.str.13063.L.str.3063.L.str.12063.L.str.2063.L.str.11063.L.str.1063.L.str.10063.L.str.63.L.str.9953.L.str.18953.L.str.8953.L.str.17953.L.str.7953.L.str.16953.L.str.6953.L.str.15953.L.str.5953.L.str.14953.L.str.4953.L.str.13953.L.str.3953.L.str.12953.L.str.2953.L.str.11953.L.str.1953.L.str.10953.L.str.953.L.str.19853.L.str.9853.L.str.18853.L.str.8853.L.str.17853.L.str.7853.L.str.16853.L.str.6853.L.str.15853.L.str.5853.L.str.14853.L.str.4853.L.str.13853.L.str.3853.L.str.12853.L.str.2853.L.str.11853.L.str.1853.L.str.10853.L.str.853.L.str.19753.L.str.9753.L.str.18753.L.str.8753.L.str.17753.L.str.7753.L.str.16753.L.str.6753.L.str.15753.L.str.5753.L.str.14753.L.str.4753.L.str.13753.L.str.3753.L.str.12753.L.str.2753.L.str.11753.L.str.1753.L.str.10753.L.str.753.L.str.19653.L.str.9653.L.str.18653.L.str.8653.L.str.17653.L.str.7653.L.str.16653.L.str.6653.L.str.15653.L.str.5653.L.str.14653.L.str.4653.L.str.13653.L.str.3653.L.str.12653.L.str.2653.L.str.11653.L.str.1653.L.str.10653.L.str.653.L.str.19553.L.str.9553.L.str.18553.L.str.8553.L.str.17553.L.str.7553.L.str.16553.L.str.6553.L.str.15553.L.str.5553.L.str.14553.L.str.4553.L.str.13553.L.str.3553.L.str.12553.L.str.2553.L.str.11553.L.str.1553.L.str.10553.L.str.553.L.str.19453.L.str.9453.L.str.18453.L.str.8453.L.str.17453.L.str.7453.L.str.16453.L.str.6453.L.str.15453.L.str.5453.L.str.14453.L.str.4453.L.str.13453.L.str.3453.L.str.12453.L.str.2453.L.str.11453.L.str.1453.L.str.10453.L.str.453.L.str.19353.L.str.9353.L.str.18353.L.str.8353.L.str.17353.L.str.7353.L.str.16353.L.str.6353.L.str.15353.L.str.5353.L.str.14353.L.str.4353.L.str.13353.L.str.3353.L.str.12353.L.str.2353.L.str.11353.L.str.1353.L.str.10353.L.str.353.L.str.19253.L.str.9253.L.str.18253.L.str.8253.L.str.17253.L.str.7253.L.str.16253.L.str.6253.L.str.15253.L.str.5253.L.str.14253.L.str.4253.L.str.13253.L.str.3253.L.str.12253.L.str.2253.L.str.11253.L.str.1253.L.str.10253.L.str.253.L.str.19153.L.str.9153.L.str.18153.L.str.8153.L.str.17153.L.str.7153.L.str.16153.L.str.6153.L.str.15153.L.str.5153.L.str.14153.L.str.4153.L.str.13153.L.str.3153.L.str.12153.L.str.2153.L.str.11153.L.str.1153.L.str.10153.L.str.153.L.str.19053.L.str.9053.L.str.18053.L.str.8053.L.str.17053.L.str.7053.L.str.16053.L.str.6053.L.str.15053.L.str.5053.L.str.14053.L.str.4053.L.str.13053.L.str.3053.L.str.12053.L.str.2053.L.str.11053.L.str.1053.L.str.10053.L.str.53.L.str.9943.L.str.18943.L.str.8943.L.str.17943.L.str.7943.L.str.16943.L.str.6943.L.str.15943.L.str.5943.L.str.14943.L.str.4943.L.str.13943.L.str.3943.L.str.12943.L.str.2943.L.str.11943.L.str.1943.L.str.10943.L.str.943.L.str.19843.L.str.9843.L.str.18843.L.str.8843.L.str.17843.L.str.7843.L.str.16843.L.str.6843.L.str.15843.L.str.5843.L.str.14843.L.str.4843.L.str.13843.L.str.3843.L.str.12843.L.str.2843.L.str.11843.L.str.1843.L.str.10843.L.str.843.L.str.19743.L.str.9743.L.str.18743.L.str.8743.L.str.17743.L.str.7743.L.str.16743.L.str.6743.L.str.15743.L.str.5743.L.str.14743.L.str.4743.L.str.13743.L.str.3743.L.str.12743.L.str.2743.L.str.11743.L.str.1743.L.str.10743.L.str.743.L.str.19643.L.str.9643.L.str.18643.L.str.8643.L.str.17643.L.str.7643.L.str.16643.L.str.6643.L.str.15643.L.str.5643.L.str.14643.L.str.4643.L.str.13643.L.str.3643.L.str.12643.L.str.2643.L.str.11643.L.str.1643.L.str.10643.L.str.643.L.str.19543.L.str.9543.L.str.18543.L.str.8543.L.str.17543.L.str.7543.L.str.16543.L.str.6543.L.str.15543.L.str.5543.L.str.14543.L.str.4543.L.str.13543.L.str.3543.L.str.12543.L.str.2543.L.str.11543.L.str.1543.L.str.10543.L.str.543.L.str.19443.L.str.9443.L.str.18443.L.str.8443.L.str.17443.L.str.7443.L.str.16443.L.str.6443.L.str.15443.L.str.5443.L.str.14443.L.str.4443.L.str.13443.L.str.3443.L.str.12443.L.str.2443.L.str.11443.L.str.1443.L.str.10443.L.str.443.L.str.19343.L.str.9343.L.str.18343.L.str.8343.L.str.17343.L.str.7343.L.str.16343.L.str.6343.L.str.15343.L.str.5343.L.str.14343.L.str.4343.L.str.13343.L.str.3343.L.str.12343.L.str.2343.L.str.11343.L.str.1343.L.str.10343.L.str.343.L.str.19243.L.str.9243.L.str.18243.L.str.8243.L.str.17243.L.str.7243.L.str.16243.L.str.6243.L.str.15243.L.str.5243.L.str.14243.L.str.4243.L.str.13243.L.str.3243.L.str.12243.L.str.2243.L.str.11243.L.str.1243.L.str.10243.L.str.243.L.str.19143.L.str.9143.L.str.18143.L.str.8143.L.str.17143.L.str.7143.L.str.16143.L.str.6143.L.str.15143.L.str.5143.L.str.14143.L.str.4143.L.str.13143.L.str.3143.L.str.12143.L.str.2143.L.str.11143.L.str.1143.L.str.10143.L.str.143.L.str.19043.L.str.9043.L.str.18043.L.str.8043.L.str.17043.L.str.7043.L.str.16043.L.str.6043.L.str.15043.L.str.5043.L.str.14043.L.str.4043.L.str.13043.L.str.3043.L.str.12043.L.str.2043.L.str.11043.L.str.1043.L.str.10043.L.str.43.L.str.9933.L.str.18933.L.str.8933.L.str.17933.L.str.7933.L.str.16933.L.str.6933.L.str.15933.L.str.5933.L.str.14933.L.str.4933.L.str.13933.L.str.3933.L.str.12933.L.str.2933.L.str.11933.L.str.1933.L.str.10933.L.str.933.L.str.19833.L.str.9833.L.str.18833.L.str.8833.L.str.17833.L.str.7833.L.str.16833.L.str.6833.L.str.15833.L.str.5833.L.str.14833.L.str.4833.L.str.13833.L.str.3833.L.str.12833.L.str.2833.L.str.11833.L.str.1833.L.str.10833.L.str.833.L.str.19733.L.str.9733.L.str.18733.L.str.8733.L.str.17733.L.str.7733.L.str.16733.L.str.6733.L.str.15733.L.str.5733.L.str.14733.L.str.4733.L.str.13733.L.str.3733.L.str.12733.L.str.2733.L.str.11733.L.str.1733.L.str.10733.L.str.733.L.str.19633.L.str.9633.L.str.18633.L.str.8633.L.str.17633.L.str.7633.L.str.16633.L.str.6633.L.str.15633.L.str.5633.L.str.14633.L.str.4633.L.str.13633.L.str.3633.L.str.12633.L.str.2633.L.str.11633.L.str.1633.L.str.10633.L.str.633.L.str.19533.L.str.9533.L.str.18533.L.str.8533.L.str.17533.L.str.7533.L.str.16533.L.str.6533.L.str.15533.L.str.5533.L.str.14533.L.str.4533.L.str.13533.L.str.3533.L.str.12533.L.str.2533.L.str.11533.L.str.1533.L.str.10533.L.str.533.L.str.19433.L.str.9433.L.str.18433.L.str.8433.L.str.17433.L.str.7433.L.str.16433.L.str.6433.L.str.15433.L.str.5433.L.str.14433.L.str.4433.L.str.13433.L.str.3433.L.str.12433.L.str.2433.L.str.11433.L.str.1433.L.str.10433.L.str.433.L.str.19333.L.str.9333.L.str.18333.L.str.8333.L.str.17333.L.str.7333.L.str.16333.L.str.6333.L.str.15333.L.str.5333.L.str.14333.L.str.4333.L.str.13333.L.str.3333.L.str.12333.L.str.2333.L.str.11333.L.str.1333.L.str.10333.L.str.333.L.str.19233.L.str.9233.L.str.18233.L.str.8233.L.str.17233.L.str.7233.L.str.16233.L.str.6233.L.str.15233.L.str.5233.L.str.14233.L.str.4233.L.str.13233.L.str.3233.L.str.12233.L.str.2233.L.str.11233.L.str.1233.L.str.10233.L.str.233.L.str.19133.L.str.9133.L.str.18133.L.str.8133.L.str.17133.L.str.7133.L.str.16133.L.str.6133.L.str.15133.L.str.5133.L.str.14133.L.str.4133.L.str.13133.L.str.3133.L.str.12133.L.str.2133.L.str.11133.L.str.1133.L.str.10133.L.str.133.L.str.19033.L.str.9033.L.str.18033.L.str.8033.L.str.17033.L.str.7033.L.str.16033.L.str.6033.L.str.15033.L.str.5033.L.str.14033.L.str.4033.L.str.13033.L.str.3033.L.str.12033.L.str.2033.L.str.11033.L.str.1033.L.str.10033.L.str.33.L.str.9923.L.str.18923.L.str.8923.L.str.17923.L.str.7923.L.str.16923.L.str.6923.L.str.15923.L.str.5923.L.str.14923.L.str.4923.L.str.13923.L.str.3923.L.str.12923.L.str.2923.L.str.11923.L.str.1923.L.str.10923.L.str.923.L.str.19823.L.str.9823.L.str.18823.L.str.8823.L.str.17823.L.str.7823.L.str.16823.L.str.6823.L.str.15823.L.str.5823.L.str.14823.L.str.4823.L.str.13823.L.str.3823.L.str.12823.L.str.2823.L.str.11823.L.str.1823.L.str.10823.L.str.823.L.str.19723.L.str.9723.L.str.18723.L.str.8723.L.str.17723.L.str.7723.L.str.16723.L.str.6723.L.str.15723.L.str.5723.L.str.14723.L.str.4723.L.str.13723.L.str.3723.L.str.12723.L.str.2723.L.str.11723.L.str.1723.L.str.10723.L.str.723.L.str.19623.L.str.9623.L.str.18623.L.str.8623.L.str.17623.L.str.7623.L.str.16623.L.str.6623.L.str.15623.L.str.5623.L.str.14623.L.str.4623.L.str.13623.L.str.3623.L.str.12623.L.str.2623.L.str.11623.L.str.1623.L.str.10623.L.str.623.L.str.19523.L.str.9523.L.str.18523.L.str.8523.L.str.17523.L.str.7523.L.str.16523.L.str.6523.L.str.15523.L.str.5523.L.str.14523.L.str.4523.L.str.13523.L.str.3523.L.str.12523.L.str.2523.L.str.11523.L.str.1523.L.str.10523.L.str.523.L.str.19423.L.str.9423.L.str.18423.L.str.8423.L.str.17423.L.str.7423.L.str.16423.L.str.6423.L.str.15423.L.str.5423.L.str.14423.L.str.4423.L.str.13423.L.str.3423.L.str.12423.L.str.2423.L.str.11423.L.str.1423.L.str.10423.L.str.423.L.str.19323.L.str.9323.L.str.18323.L.str.8323.L.str.17323.L.str.7323.L.str.16323.L.str.6323.L.str.15323.L.str.5323.L.str.14323.L.str.4323.L.str.13323.L.str.3323.L.str.12323.L.str.2323.L.str.11323.L.str.1323.L.str.10323.L.str.323.L.str.19223.L.str.9223.L.str.18223.L.str.8223.L.str.17223.L.str.7223.L.str.16223.L.str.6223.L.str.15223.L.str.5223.L.str.14223.L.str.4223.L.str.13223.L.str.3223.L.str.12223.L.str.2223.L.str.11223.L.str.1223.L.str.10223.L.str.223.L.str.19123.L.str.9123.L.str.18123.L.str.8123.L.str.17123.L.str.7123.L.str.16123.L.str.6123.L.str.15123.L.str.5123.L.str.14123.L.str.4123.L.str.13123.L.str.3123.L.str.12123.L.str.2123.L.str.11123.L.str.1123.L.str.10123.L.str.123.L.str.19023.L.str.9023.L.str.18023.L.str.8023.L.str.17023.L.str.7023.L.str.16023.L.str.6023.L.str.15023.L.str.5023.L.str.14023.L.str.4023.L.str.13023.L.str.3023.L.str.12023.L.str.2023.L.str.11023.L.str.1023.L.str.10023.L.str.23.L.str.9913.L.str.18913.L.str.8913.L.str.17913.L.str.7913.L.str.16913.L.str.6913.L.str.15913.L.str.5913.L.str.14913.L.str.4913.L.str.13913.L.str.3913.L.str.12913.L.str.2913.L.str.11913.L.str.1913.L.str.10913.L.str.913.L.str.19813.L.str.9813.L.str.18813.L.str.8813.L.str.17813.L.str.7813.L.str.16813.L.str.6813.L.str.15813.L.str.5813.L.str.14813.L.str.4813.L.str.13813.L.str.3813.L.str.12813.L.str.2813.L.str.11813.L.str.1813.L.str.10813.L.str.813.L.str.19713.L.str.9713.L.str.18713.L.str.8713.L.str.17713.L.str.7713.L.str.16713.L.str.6713.L.str.15713.L.str.5713.L.str.14713.L.str.4713.L.str.13713.L.str.3713.L.str.12713.L.str.2713.L.str.11713.L.str.1713.L.str.10713.L.str.713.L.str.19613.L.str.9613.L.str.18613.L.str.8613.L.str.17613.L.str.7613.L.str.16613.L.str.6613.L.str.15613.L.str.5613.L.str.14613.L.str.4613.L.str.13613.L.str.3613.L.str.12613.L.str.2613.L.str.11613.L.str.1613.L.str.10613.L.str.613.L.str.19513.L.str.9513.L.str.18513.L.str.8513.L.str.17513.L.str.7513.L.str.16513.L.str.6513.L.str.15513.L.str.5513.L.str.14513.L.str.4513.L.str.13513.L.str.3513.L.str.12513.L.str.2513.L.str.11513.L.str.1513.L.str.10513.L.str.513.L.str.19413.L.str.9413.L.str.18413.L.str.8413.L.str.17413.L.str.7413.L.str.16413.L.str.6413.L.str.15413.L.str.5413.L.str.14413.L.str.4413.L.str.13413.L.str.3413.L.str.12413.L.str.2413.L.str.11413.L.str.1413.L.str.10413.L.str.413.L.str.19313.L.str.9313.L.str.18313.L.str.8313.L.str.17313.L.str.7313.L.str.16313.L.str.6313.L.str.15313.L.str.5313.L.str.14313.L.str.4313.L.str.13313.L.str.3313.L.str.12313.L.str.2313.L.str.11313.L.str.1313.L.str.10313.L.str.313.L.str.19213.L.str.9213.L.str.18213.L.str.8213.L.str.17213.L.str.7213.L.str.16213.L.str.6213.L.str.15213.L.str.5213.L.str.14213.L.str.4213.L.str.13213.L.str.3213.L.str.12213.L.str.2213.L.str.11213.L.str.1213.L.str.10213.L.str.213.L.str.19113.L.str.9113.L.str.18113.L.str.8113.L.str.17113.L.str.7113.L.str.16113.L.str.6113.L.str.15113.L.str.5113.L.str.14113.L.str.4113.L.str.13113.L.str.3113.L.str.12113.L.str.2113.L.str.11113.L.str.1113.L.str.10113.L.str.113.L.str.19013.L.str.9013.L.str.18013.L.str.8013.L.str.17013.L.str.7013.L.str.16013.L.str.6013.L.str.15013.L.str.5013.L.str.14013.L.str.4013.L.str.13013.L.str.3013.L.str.12013.L.str.2013.L.str.11013.L.str.1013.L.str.10013.L.str.13.L.str.9903.L.str.18903.L.str.8903.L.str.17903.L.str.7903.L.str.16903.L.str.6903.L.str.15903.L.str.5903.L.str.14903.L.str.4903.L.str.13903.L.str.3903.L.str.12903.L.str.2903.L.str.11903.L.str.1903.L.str.10903.L.str.903.L.str.19803.L.str.9803.L.str.18803.L.str.8803.L.str.17803.L.str.7803.L.str.16803.L.str.6803.L.str.15803.L.str.5803.L.str.14803.L.str.4803.L.str.13803.L.str.3803.L.str.12803.L.str.2803.L.str.11803.L.str.1803.L.str.10803.L.str.803.L.str.19703.L.str.9703.L.str.18703.L.str.8703.L.str.17703.L.str.7703.L.str.16703.L.str.6703.L.str.15703.L.str.5703.L.str.14703.L.str.4703.L.str.13703.L.str.3703.L.str.12703.L.str.2703.L.str.11703.L.str.1703.L.str.10703.L.str.703.L.str.19603.L.str.9603.L.str.18603.L.str.8603.L.str.17603.L.str.7603.L.str.16603.L.str.6603.L.str.15603.L.str.5603.L.str.14603.L.str.4603.L.str.13603.L.str.3603.L.str.12603.L.str.2603.L.str.11603.L.str.1603.L.str.10603.L.str.603.L.str.19503.L.str.9503.L.str.18503.L.str.8503.L.str.17503.L.str.7503.L.str.16503.L.str.6503.L.str.15503.L.str.5503.L.str.14503.L.str.4503.L.str.13503.L.str.3503.L.str.12503.L.str.2503.L.str.11503.L.str.1503.L.str.10503.L.str.503.L.str.19403.L.str.9403.L.str.18403.L.str.8403.L.str.17403.L.str.7403.L.str.16403.L.str.6403.L.str.15403.L.str.5403.L.str.14403.L.str.4403.L.str.13403.L.str.3403.L.str.12403.L.str.2403.L.str.11403.L.str.1403.L.str.10403.L.str.403.L.str.19303.L.str.9303.L.str.18303.L.str.8303.L.str.17303.L.str.7303.L.str.16303.L.str.6303.L.str.15303.L.str.5303.L.str.14303.L.str.4303.L.str.13303.L.str.3303.L.str.12303.L.str.2303.L.str.11303.L.str.1303.L.str.10303.L.str.303.L.str.19203.L.str.9203.L.str.18203.L.str.8203.L.str.17203.L.str.7203.L.str.16203.L.str.6203.L.str.15203.L.str.5203.L.str.14203.L.str.4203.L.str.13203.L.str.3203.L.str.12203.L.str.2203.L.str.11203.L.str.1203.L.str.10203.L.str.203.L.str.19103.L.str.9103.L.str.18103.L.str.8103.L.str.17103.L.str.7103.L.str.16103.L.str.6103.L.str.15103.L.str.5103.L.str.14103.L.str.4103.L.str.13103.L.str.3103.L.str.12103.L.str.2103.L.str.11103.L.str.1103.L.str.10103.L.str.103.L.str.19003.L.str.9003.L.str.18003.L.str.8003.L.str.17003.L.str.7003.L.str.16003.L.str.6003.L.str.15003.L.str.5003.L.str.14003.L.str.4003.L.str.13003.L.str.3003.L.str.12003.L.str.2003.L.str.11003.L.str.1003.L.str.10003.L.str.3pme_amdzen2.L.str.9992.L.str.18992.L.str.8992.L.str.17992.L.str.7992.L.str.16992.L.str.6992.L.str.15992.L.str.5992.L.str.14992.L.str.4992.L.str.13992.L.str.3992.L.str.12992.L.str.2992.L.str.11992.L.str.1992.L.str.10992.L.str.992.L.str.9892.L.str.18892.L.str.8892.L.str.17892.L.str.7892.L.str.16892.L.str.6892.L.str.15892.L.str.5892.L.str.14892.L.str.4892.L.str.13892.L.str.3892.L.str.12892.L.str.2892.L.str.11892.L.str.1892.L.str.10892.L.str.892.L.str.19792.L.str.9792.L.str.18792.L.str.8792.L.str.17792.L.str.7792.L.str.16792.L.str.6792.L.str.15792.L.str.5792.L.str.14792.L.str.4792.L.str.13792.L.str.3792.L.str.12792.L.str.2792.L.str.11792.L.str.1792.L.str.10792.L.str.792.L.str.19692.L.str.9692.L.str.18692.L.str.8692.L.str.17692.L.str.7692.L.str.16692.L.str.6692.L.str.15692.L.str.5692.L.str.14692.L.str.4692.L.str.13692.L.str.3692.L.str.12692.L.str.2692.L.str.11692.L.str.1692.L.str.10692.L.str.692.L.str.19592.L.str.9592.L.str.18592.L.str.8592.L.str.17592.L.str.7592.L.str.16592.L.str.6592.L.str.15592.L.str.5592.L.str.14592.L.str.4592.L.str.13592.L.str.3592.L.str.12592.L.str.2592.L.str.11592.L.str.1592.L.str.10592.L.str.592.L.str.19492.L.str.9492.L.str.18492.L.str.8492.L.str.17492.L.str.7492.L.str.16492.L.str.6492.L.str.15492.L.str.5492.L.str.14492.L.str.4492.L.str.13492.L.str.3492.L.str.12492.L.str.2492.L.str.11492.L.str.1492.L.str.10492.L.str.492.L.str.19392.L.str.9392.L.str.18392.L.str.8392.L.str.17392.L.str.7392.L.str.16392.L.str.6392.L.str.15392.L.str.5392.L.str.14392.L.str.4392.L.str.13392.L.str.3392.L.str.12392.L.str.2392.L.str.11392.L.str.1392.L.str.10392.L.str.392.L.str.19292.L.str.9292.L.str.18292.L.str.8292.L.str.17292.L.str.7292.L.str.16292.L.str.6292.L.str.15292.L.str.5292.L.str.14292.L.str.4292.L.str.13292.L.str.3292.L.str.12292.L.str.2292.L.str.11292.L.str.1292.L.str.10292.L.str.292.L.str.19192.L.str.9192.L.str.18192.L.str.8192.L.str.17192.L.str.7192.L.str.16192.L.str.6192.L.str.15192.L.str.5192.L.str.14192.L.str.4192.L.str.13192.L.str.3192.L.str.12192.L.str.2192.L.str.11192.L.str.1192.L.str.10192.L.str.192.L.str.19092.L.str.9092.L.str.18092.L.str.8092.L.str.17092.L.str.7092.L.str.16092.L.str.6092.L.str.15092.L.str.5092.L.str.14092.L.str.4092.L.str.13092.L.str.3092.L.str.12092.L.str.2092.L.str.11092.L.str.1092.L.str.10092.L.str.92.L.str.9982.L.str.18982.L.str.8982.L.str.17982.L.str.7982.L.str.16982.L.str.6982.L.str.15982.L.str.5982.L.str.14982.L.str.4982.L.str.13982.L.str.3982.L.str.12982.L.str.2982.L.str.11982.L.str.1982.L.str.10982.L.str.982.L.str.9882.L.str.18882.L.str.8882.L.str.17882.L.str.7882.L.str.16882.L.str.6882.L.str.15882.L.str.5882.L.str.14882.L.str.4882.L.str.13882.L.str.3882.L.str.12882.L.str.2882.L.str.11882.L.str.1882.L.str.10882.L.str.882.L.str.19782.L.str.9782.L.str.18782.L.str.8782.L.str.17782.L.str.7782.L.str.16782.L.str.6782.L.str.15782.L.str.5782.L.str.14782.L.str.4782.L.str.13782.L.str.3782.L.str.12782.L.str.2782.L.str.11782.L.str.1782.L.str.10782.L.str.782.L.str.19682.L.str.9682.L.str.18682.L.str.8682.L.str.17682.L.str.7682.L.str.16682.L.str.6682.L.str.15682.L.str.5682.L.str.14682.L.str.4682.L.str.13682.L.str.3682.L.str.12682.L.str.2682.L.str.11682.L.str.1682.L.str.10682.L.str.682.L.str.19582.L.str.9582.L.str.18582.L.str.8582.L.str.17582.L.str.7582.L.str.16582.L.str.6582.L.str.15582.L.str.5582.L.str.14582.L.str.4582.L.str.13582.L.str.3582.L.str.12582.L.str.2582.L.str.11582.L.str.1582.L.str.10582.L.str.582.L.str.19482.L.str.9482.L.str.18482.L.str.8482.L.str.17482.L.str.7482.L.str.16482.L.str.6482.L.str.15482.L.str.5482.L.str.14482.L.str.4482.L.str.13482.L.str.3482.L.str.12482.L.str.2482.L.str.11482.L.str.1482.L.str.10482.L.str.482.L.str.19382.L.str.9382.L.str.18382.L.str.8382.L.str.17382.L.str.7382.L.str.16382.L.str.6382.L.str.15382.L.str.5382.L.str.14382.L.str.4382.L.str.13382.L.str.3382.L.str.12382.L.str.2382.L.str.11382.L.str.1382.L.str.10382.L.str.382.L.str.19282.L.str.9282.L.str.18282.L.str.8282.L.str.17282.L.str.7282.L.str.16282.L.str.6282.L.str.15282.L.str.5282.L.str.14282.L.str.4282.L.str.13282.L.str.3282.L.str.12282.L.str.2282.L.str.11282.L.str.1282.L.str.10282.L.str.282.L.str.19182.L.str.9182.L.str.18182.L.str.8182.L.str.17182.L.str.7182.L.str.16182.L.str.6182.L.str.15182.L.str.5182.L.str.14182.L.str.4182.L.str.13182.L.str.3182.L.str.12182.L.str.2182.L.str.11182.L.str.1182.L.str.10182.L.str.182.L.str.19082.L.str.9082.L.str.18082.L.str.8082.L.str.17082.L.str.7082.L.str.16082.L.str.6082.L.str.15082.L.str.5082.L.str.14082.L.str.4082.L.str.13082.L.str.3082.L.str.12082.L.str.2082.L.str.11082.L.str.1082.L.str.10082.L.str.82.L.str.9972.L.str.18972.L.str.8972.L.str.17972.L.str.7972.L.str.16972.L.str.6972.L.str.15972.L.str.5972.L.str.14972.L.str.4972.L.str.13972.L.str.3972.L.str.12972.L.str.2972.L.str.11972.L.str.1972.L.str.10972.L.str.972.L.str.9872.L.str.18872.L.str.8872.L.str.17872.L.str.7872.L.str.16872.L.str.6872.L.str.15872.L.str.5872.L.str.14872.L.str.4872.L.str.13872.L.str.3872.L.str.12872.L.str.2872.L.str.11872.L.str.1872.L.str.10872.L.str.872.L.str.19772.L.str.9772.L.str.18772.L.str.8772.L.str.17772.L.str.7772.L.str.16772.L.str.6772.L.str.15772.L.str.5772.L.str.14772.L.str.4772.L.str.13772.L.str.3772.L.str.12772.L.str.2772.L.str.11772.L.str.1772.L.str.10772.L.str.772.L.str.19672.L.str.9672.L.str.18672.L.str.8672.L.str.17672.L.str.7672.L.str.16672.L.str.6672.L.str.15672.L.str.5672.L.str.14672.L.str.4672.L.str.13672.L.str.3672.L.str.12672.L.str.2672.L.str.11672.L.str.1672.L.str.10672.L.str.672.L.str.19572.L.str.9572.L.str.18572.L.str.8572.L.str.17572.L.str.7572.L.str.16572.L.str.6572.L.str.15572.L.str.5572.L.str.14572.L.str.4572.L.str.13572.L.str.3572.L.str.12572.L.str.2572.L.str.11572.L.str.1572.L.str.10572.L.str.572.L.str.19472.L.str.9472.L.str.18472.L.str.8472.L.str.17472.L.str.7472.L.str.16472.L.str.6472.L.str.15472.L.str.5472.L.str.14472.L.str.4472.L.str.13472.L.str.3472.L.str.12472.L.str.2472.L.str.11472.L.str.1472.L.str.10472.L.str.472.L.str.19372.L.str.9372.L.str.18372.L.str.8372.L.str.17372.L.str.7372.L.str.16372.L.str.6372.L.str.15372.L.str.5372.L.str.14372.L.str.4372.L.str.13372.L.str.3372.L.str.12372.L.str.2372.L.str.11372.L.str.1372.L.str.10372.L.str.372.L.str.19272.L.str.9272.L.str.18272.L.str.8272.L.str.17272.L.str.7272.L.str.16272.L.str.6272.L.str.15272.L.str.5272.L.str.14272.L.str.4272.L.str.13272.L.str.3272.L.str.12272.L.str.2272.L.str.11272.L.str.1272.L.str.10272.L.str.272.L.str.19172.L.str.9172.L.str.18172.L.str.8172.L.str.17172.L.str.7172.L.str.16172.L.str.6172.L.str.15172.L.str.5172.L.str.14172.L.str.4172.L.str.13172.L.str.3172.L.str.12172.L.str.2172.L.str.11172.L.str.1172.L.str.10172.L.str.172.L.str.19072.L.str.9072.L.str.18072.L.str.8072.L.str.17072.L.str.7072.L.str.16072.L.str.6072.L.str.15072.L.str.5072.L.str.14072.L.str.4072.L.str.13072.L.str.3072.L.str.12072.L.str.2072.L.str.11072.L.str.1072.L.str.10072.L.str.72.L.str.9962.L.str.18962.L.str.8962.L.str.17962.L.str.7962.L.str.16962.L.str.6962.L.str.15962.L.str.5962.L.str.14962.L.str.4962.L.str.13962.L.str.3962.L.str.12962.L.str.2962.L.str.11962.L.str.1962.L.str.10962.L.str.962.L.str.19862.L.str.9862.L.str.18862.L.str.8862.L.str.17862.L.str.7862.L.str.16862.L.str.6862.L.str.15862.L.str.5862.L.str.14862.L.str.4862.L.str.13862.L.str.3862.L.str.12862.L.str.2862.L.str.11862.L.str.1862.L.str.10862.L.str.862.L.str.19762.L.str.9762.L.str.18762.L.str.8762.L.str.17762.L.str.7762.L.str.16762.L.str.6762.L.str.15762.L.str.5762.L.str.14762.L.str.4762.L.str.13762.L.str.3762.L.str.12762.L.str.2762.L.str.11762.L.str.1762.L.str.10762.L.str.762.L.str.19662.L.str.9662.L.str.18662.L.str.8662.L.str.17662.L.str.7662.L.str.16662.L.str.6662.L.str.15662.L.str.5662.L.str.14662.L.str.4662.L.str.13662.L.str.3662.L.str.12662.L.str.2662.L.str.11662.L.str.1662.L.str.10662.L.str.662.L.str.19562.L.str.9562.L.str.18562.L.str.8562.L.str.17562.L.str.7562.L.str.16562.L.str.6562.L.str.15562.L.str.5562.L.str.14562.L.str.4562.L.str.13562.L.str.3562.L.str.12562.L.str.2562.L.str.11562.L.str.1562.L.str.10562.L.str.562.L.str.19462.L.str.9462.L.str.18462.L.str.8462.L.str.17462.L.str.7462.L.str.16462.L.str.6462.L.str.15462.L.str.5462.L.str.14462.L.str.4462.L.str.13462.L.str.3462.L.str.12462.L.str.2462.L.str.11462.L.str.1462.L.str.10462.L.str.462.L.str.19362.L.str.9362.L.str.18362.L.str.8362.L.str.17362.L.str.7362.L.str.16362.L.str.6362.L.str.15362.L.str.5362.L.str.14362.L.str.4362.L.str.13362.L.str.3362.L.str.12362.L.str.2362.L.str.11362.L.str.1362.L.str.10362.L.str.362.L.str.19262.L.str.9262.L.str.18262.L.str.8262.L.str.17262.L.str.7262.L.str.16262.L.str.6262.L.str.15262.L.str.5262.L.str.14262.L.str.4262.L.str.13262.L.str.3262.L.str.12262.L.str.2262.L.str.11262.L.str.1262.L.str.10262.L.str.262.L.str.19162.L.str.9162.L.str.18162.L.str.8162.L.str.17162.L.str.7162.L.str.16162.L.str.6162.L.str.15162.L.str.5162.L.str.14162.L.str.4162.L.str.13162.L.str.3162.L.str.12162.L.str.2162.L.str.11162.L.str.1162.L.str.10162.L.str.162.L.str.19062.L.str.9062.L.str.18062.L.str.8062.L.str.17062.L.str.7062.L.str.16062.L.str.6062.L.str.15062.L.str.5062.L.str.14062.L.str.4062.L.str.13062.L.str.3062.L.str.12062.L.str.2062.L.str.11062.L.str.1062.L.str.10062.L.str.62.L.str.9952.L.str.18952.L.str.8952.L.str.17952.L.str.7952.L.str.16952.L.str.6952.L.str.15952.L.str.5952.L.str.14952.L.str.4952.L.str.13952.L.str.3952.L.str.12952.L.str.2952.L.str.11952.L.str.1952.L.str.10952.L.str.952.L.str.19852.L.str.9852.L.str.18852.L.str.8852.L.str.17852.L.str.7852.L.str.16852.L.str.6852.L.str.15852.L.str.5852.L.str.14852.L.str.4852.L.str.13852.L.str.3852.L.str.12852.L.str.2852.L.str.11852.L.str.1852.L.str.10852.L.str.852.L.str.19752.L.str.9752.L.str.18752.L.str.8752.L.str.17752.L.str.7752.L.str.16752.L.str.6752.L.str.15752.L.str.5752.L.str.14752.L.str.4752.L.str.13752.L.str.3752.L.str.12752.L.str.2752.L.str.11752.L.str.1752.L.str.10752.L.str.752.L.str.19652.L.str.9652.L.str.18652.L.str.8652.L.str.17652.L.str.7652.L.str.16652.L.str.6652.L.str.15652.L.str.5652.L.str.14652.L.str.4652.L.str.13652.L.str.3652.L.str.12652.L.str.2652.L.str.11652.L.str.1652.L.str.10652.L.str.652.L.str.19552.L.str.9552.L.str.18552.L.str.8552.L.str.17552.L.str.7552.L.str.16552.L.str.6552.L.str.15552.L.str.5552.L.str.14552.L.str.4552.L.str.13552.L.str.3552.L.str.12552.L.str.2552.L.str.11552.L.str.1552.L.str.10552.L.str.552.L.str.19452.L.str.9452.L.str.18452.L.str.8452.L.str.17452.L.str.7452.L.str.16452.L.str.6452.L.str.15452.L.str.5452.L.str.14452.L.str.4452.L.str.13452.L.str.3452.L.str.12452.L.str.2452.L.str.11452.L.str.1452.L.str.10452.L.str.452.L.str.19352.L.str.9352.L.str.18352.L.str.8352.L.str.17352.L.str.7352.L.str.16352.L.str.6352.L.str.15352.L.str.5352.L.str.14352.L.str.4352.L.str.13352.L.str.3352.L.str.12352.L.str.2352.L.str.11352.L.str.1352.L.str.10352.L.str.352.L.str.19252.L.str.9252.L.str.18252.L.str.8252.L.str.17252.L.str.7252.L.str.16252.L.str.6252.L.str.15252.L.str.5252.L.str.14252.L.str.4252.L.str.13252.L.str.3252.L.str.12252.L.str.2252.L.str.11252.L.str.1252.L.str.10252.L.str.252.L.str.19152.L.str.9152.L.str.18152.L.str.8152.L.str.17152.L.str.7152.L.str.16152.L.str.6152.L.str.15152.L.str.5152.L.str.14152.L.str.4152.L.str.13152.L.str.3152.L.str.12152.L.str.2152.L.str.11152.L.str.1152.L.str.10152.L.str.152.L.str.19052.L.str.9052.L.str.18052.L.str.8052.L.str.17052.L.str.7052.L.str.16052.L.str.6052.L.str.15052.L.str.5052.L.str.14052.L.str.4052.L.str.13052.L.str.3052.L.str.12052.L.str.2052.L.str.11052.L.str.1052.L.str.10052.L.str.52.L.str.9942.L.str.18942.L.str.8942.L.str.17942.L.str.7942.L.str.16942.L.str.6942.L.str.15942.L.str.5942.L.str.14942.L.str.4942.L.str.13942.L.str.3942.L.str.12942.L.str.2942.L.str.11942.L.str.1942.L.str.10942.L.str.942.L.str.19842.L.str.9842.L.str.18842.L.str.8842.L.str.17842.L.str.7842.L.str.16842.L.str.6842.L.str.15842.L.str.5842.L.str.14842.L.str.4842.L.str.13842.L.str.3842.L.str.12842.L.str.2842.L.str.11842.L.str.1842.L.str.10842.L.str.842.L.str.19742.L.str.9742.L.str.18742.L.str.8742.L.str.17742.L.str.7742.L.str.16742.L.str.6742.L.str.15742.L.str.5742.L.str.14742.L.str.4742.L.str.13742.L.str.3742.L.str.12742.L.str.2742.L.str.11742.L.str.1742.L.str.10742.L.str.742.L.str.19642.L.str.9642.L.str.18642.L.str.8642.L.str.17642.L.str.7642.L.str.16642.L.str.6642.L.str.15642.L.str.5642.L.str.14642.L.str.4642.L.str.13642.L.str.3642.L.str.12642.L.str.2642.L.str.11642.L.str.1642.L.str.10642.L.str.642.L.str.19542.L.str.9542.L.str.18542.L.str.8542.L.str.17542.L.str.7542.L.str.16542.L.str.6542.L.str.15542.L.str.5542.L.str.14542.L.str.4542.L.str.13542.L.str.3542.L.str.12542.L.str.2542.L.str.11542.L.str.1542.L.str.10542.L.str.542.L.str.19442.L.str.9442.L.str.18442.L.str.8442.L.str.17442.L.str.7442.L.str.16442.L.str.6442.L.str.15442.L.str.5442.L.str.14442.L.str.4442.L.str.13442.L.str.3442.L.str.12442.L.str.2442.L.str.11442.L.str.1442.L.str.10442.L.str.442.L.str.19342.L.str.9342.L.str.18342.L.str.8342.L.str.17342.L.str.7342.L.str.16342.L.str.6342.L.str.15342.L.str.5342.L.str.14342.L.str.4342.L.str.13342.L.str.3342.L.str.12342.L.str.2342.L.str.11342.L.str.1342.L.str.10342.L.str.342.L.str.19242.L.str.9242.L.str.18242.L.str.8242.L.str.17242.L.str.7242.L.str.16242.L.str.6242.L.str.15242.L.str.5242.L.str.14242.L.str.4242.L.str.13242.L.str.3242.L.str.12242.L.str.2242.L.str.11242.L.str.1242.L.str.10242.L.str.242.L.str.19142.L.str.9142.L.str.18142.L.str.8142.L.str.17142.L.str.7142.L.str.16142.L.str.6142.L.str.15142.L.str.5142.L.str.14142.L.str.4142.L.str.13142.L.str.3142.L.str.12142.L.str.2142.L.str.11142.L.str.1142.L.str.10142.L.str.142.L.str.19042.L.str.9042.L.str.18042.L.str.8042.L.str.17042.L.str.7042.L.str.16042.L.str.6042.L.str.15042.L.str.5042.L.str.14042.L.str.4042.L.str.13042.L.str.3042.L.str.12042.L.str.2042.L.str.11042.L.str.1042.L.str.10042.L.str.42.L.str.9932.L.str.18932.L.str.8932.L.str.17932.L.str.7932.L.str.16932.L.str.6932.L.str.15932.L.str.5932.L.str.14932.L.str.4932.L.str.13932.L.str.3932.L.str.12932.L.str.2932.L.str.11932.L.str.1932.L.str.10932.L.str.932.L.str.19832.L.str.9832.L.str.18832.L.str.8832.L.str.17832.L.str.7832.L.str.16832.L.str.6832.L.str.15832.L.str.5832.L.str.14832.L.str.4832.L.str.13832.L.str.3832.L.str.12832.L.str.2832.L.str.11832.L.str.1832.L.str.10832.L.str.832.L.str.19732.L.str.9732.L.str.18732.L.str.8732.L.str.17732.L.str.7732.L.str.16732.L.str.6732.L.str.15732.L.str.5732.L.str.14732.L.str.4732.L.str.13732.L.str.3732.L.str.12732.L.str.2732.L.str.11732.L.str.1732.L.str.10732.L.str.732.L.str.19632.L.str.9632.L.str.18632.L.str.8632.L.str.17632.L.str.7632.L.str.16632.L.str.6632.L.str.15632.L.str.5632.L.str.14632.L.str.4632.L.str.13632.L.str.3632.L.str.12632.L.str.2632.L.str.11632.L.str.1632.L.str.10632.L.str.632.L.str.19532.L.str.9532.L.str.18532.L.str.8532.L.str.17532.L.str.7532.L.str.16532.L.str.6532.L.str.15532.L.str.5532.L.str.14532.L.str.4532.L.str.13532.L.str.3532.L.str.12532.L.str.2532.L.str.11532.L.str.1532.L.str.10532.L.str.532.L.str.19432.L.str.9432.L.str.18432.L.str.8432.L.str.17432.L.str.7432.L.str.16432.L.str.6432.L.str.15432.L.str.5432.L.str.14432.L.str.4432.L.str.13432.L.str.3432.L.str.12432.L.str.2432.L.str.11432.L.str.1432.L.str.10432.L.str.432.L.str.19332.L.str.9332.L.str.18332.L.str.8332.L.str.17332.L.str.7332.L.str.16332.L.str.6332.L.str.15332.L.str.5332.L.str.14332.L.str.4332.L.str.13332.L.str.3332.L.str.12332.L.str.2332.L.str.11332.L.str.1332.L.str.10332.L.str.332.L.str.19232.L.str.9232.L.str.18232.L.str.8232.L.str.17232.L.str.7232.L.str.16232.L.str.6232.L.str.15232.L.str.5232.L.str.14232.L.str.4232.L.str.13232.L.str.3232.L.str.12232.L.str.2232.L.str.11232.L.str.1232.L.str.10232.L.str.232.L.str.19132.L.str.9132.L.str.18132.L.str.8132.L.str.17132.L.str.7132.L.str.16132.L.str.6132.L.str.15132.L.str.5132.L.str.14132.L.str.4132.L.str.13132.L.str.3132.L.str.12132.L.str.2132.L.str.11132.L.str.1132.L.str.10132.L.str.132.L.str.19032.L.str.9032.L.str.18032.L.str.8032.L.str.17032.L.str.7032.L.str.16032.L.str.6032.L.str.15032.L.str.5032.L.str.14032.L.str.4032.L.str.13032.L.str.3032.L.str.12032.L.str.2032.L.str.11032.L.str.1032.L.str.10032.L.str.32.L.str.9922.L.str.18922.L.str.8922.L.str.17922.L.str.7922.L.str.16922.L.str.6922.L.str.15922.L.str.5922.L.str.14922.L.str.4922.L.str.13922.L.str.3922.L.str.12922.L.str.2922.L.str.11922.L.str.1922.L.str.10922.L.str.922.L.str.19822.L.str.9822.L.str.18822.L.str.8822.L.str.17822.L.str.7822.L.str.16822.L.str.6822.L.str.15822.L.str.5822.L.str.14822.L.str.4822.L.str.13822.L.str.3822.L.str.12822.L.str.2822.L.str.11822.L.str.1822.L.str.10822.L.str.822.L.str.19722.L.str.9722.L.str.18722.L.str.8722.L.str.17722.L.str.7722.L.str.16722.L.str.6722.L.str.15722.L.str.5722.L.str.14722.L.str.4722.L.str.13722.L.str.3722.L.str.12722.L.str.2722.L.str.11722.L.str.1722.L.str.10722.L.str.722.L.str.19622.L.str.9622.L.str.18622.L.str.8622.L.str.17622.L.str.7622.L.str.16622.L.str.6622.L.str.15622.L.str.5622.L.str.14622.L.str.4622.L.str.13622.L.str.3622.L.str.12622.L.str.2622.L.str.11622.L.str.1622.L.str.10622.L.str.622.L.str.19522.L.str.9522.L.str.18522.L.str.8522.L.str.17522.L.str.7522.L.str.16522.L.str.6522.L.str.15522.L.str.5522.L.str.14522.L.str.4522.L.str.13522.L.str.3522.L.str.12522.L.str.2522.L.str.11522.L.str.1522.L.str.10522.L.str.522.L.str.19422.L.str.9422.L.str.18422.L.str.8422.L.str.17422.L.str.7422.L.str.16422.L.str.6422.L.str.15422.L.str.5422.L.str.14422.L.str.4422.L.str.13422.L.str.3422.L.str.12422.L.str.2422.L.str.11422.L.str.1422.L.str.10422.L.str.422.L.str.19322.L.str.9322.L.str.18322.L.str.8322.L.str.17322.L.str.7322.L.str.16322.L.str.6322.L.str.15322.L.str.5322.L.str.14322.L.str.4322.L.str.13322.L.str.3322.L.str.12322.L.str.2322.L.str.11322.L.str.1322.L.str.10322.L.str.322.L.str.19222.L.str.9222.L.str.18222.L.str.8222.L.str.17222.L.str.7222.L.str.16222.L.str.6222.L.str.15222.L.str.5222.L.str.14222.L.str.4222.L.str.13222.L.str.3222.L.str.12222.L.str.2222.L.str.11222.L.str.1222.L.str.10222.L.str.222.L.str.19122.L.str.9122.L.str.18122.L.str.8122.L.str.17122.L.str.7122.L.str.16122.L.str.6122.L.str.15122.L.str.5122.L.str.14122.L.str.4122.L.str.13122.L.str.3122.L.str.12122.L.str.2122.L.str.11122.L.str.1122.L.str.10122.L.str.122.L.str.19022.L.str.9022.L.str.18022.L.str.8022.L.str.17022.L.str.7022.L.str.16022.L.str.6022.L.str.15022.L.str.5022.L.str.14022.L.str.4022.L.str.13022.L.str.3022.L.str.12022.L.str.2022.L.str.11022.L.str.1022.L.str.10022.L.str.22.L.str.9912.L.str.18912.L.str.8912.L.str.17912.L.str.7912.L.str.16912.L.str.6912.L.str.15912.L.str.5912.L.str.14912.L.str.4912.L.str.13912.L.str.3912.L.str.12912.L.str.2912.L.str.11912.L.str.1912.L.str.10912.L.str.912.L.str.19812.L.str.9812.L.str.18812.L.str.8812.L.str.17812.L.str.7812.L.str.16812.L.str.6812.L.str.15812.L.str.5812.L.str.14812.L.str.4812.L.str.13812.L.str.3812.L.str.12812.L.str.2812.L.str.11812.L.str.1812.L.str.10812.L.str.812.L.str.19712.L.str.9712.L.str.18712.L.str.8712.L.str.17712.L.str.7712.L.str.16712.L.str.6712.L.str.15712.L.str.5712.L.str.14712.L.str.4712.L.str.13712.L.str.3712.L.str.12712.L.str.2712.L.str.11712.L.str.1712.L.str.10712.L.str.712.L.str.19612.L.str.9612.L.str.18612.L.str.8612.L.str.17612.L.str.7612.L.str.16612.L.str.6612.L.str.15612.L.str.5612.L.str.14612.L.str.4612.L.str.13612.L.str.3612.L.str.12612.L.str.2612.L.str.11612.L.str.1612.L.str.10612.L.str.612.L.str.19512.L.str.9512.L.str.18512.L.str.8512.L.str.17512.L.str.7512.L.str.16512.L.str.6512.L.str.15512.L.str.5512.L.str.14512.L.str.4512.L.str.13512.L.str.3512.L.str.12512.L.str.2512.L.str.11512.L.str.1512.L.str.10512.L.str.512.L.str.19412.L.str.9412.L.str.18412.L.str.8412.L.str.17412.L.str.7412.L.str.16412.L.str.6412.L.str.15412.L.str.5412.L.str.14412.L.str.4412.L.str.13412.L.str.3412.L.str.12412.L.str.2412.L.str.11412.L.str.1412.L.str.10412.L.str.412.L.str.19312.L.str.9312.L.str.18312.L.str.8312.L.str.17312.L.str.7312.L.str.16312.L.str.6312.L.str.15312.L.str.5312.L.str.14312.L.str.4312.L.str.13312.L.str.3312.L.str.12312.L.str.2312.L.str.11312.L.str.1312.L.str.10312.L.str.312.L.str.19212.L.str.9212.L.str.18212.L.str.8212.L.str.17212.L.str.7212.L.str.16212.L.str.6212.L.str.15212.L.str.5212.L.str.14212.L.str.4212.L.str.13212.L.str.3212.L.str.12212.L.str.2212.L.str.11212.L.str.1212.L.str.10212.L.str.212.L.str.19112.L.str.9112.L.str.18112.L.str.8112.L.str.17112.L.str.7112.L.str.16112.L.str.6112.L.str.15112.L.str.5112.L.str.14112.L.str.4112.L.str.13112.L.str.3112.L.str.12112.L.str.2112.L.str.11112.L.str.1112.L.str.10112.L.str.112.L.str.19012.L.str.9012.L.str.18012.L.str.8012.L.str.17012.L.str.7012.L.str.16012.L.str.6012.L.str.15012.L.str.5012.L.str.14012.L.str.4012.L.str.13012.L.str.3012.L.str.12012.L.str.2012.L.str.11012.L.str.1012.L.str.10012.L.str.12.L.str.9902.L.str.18902.L.str.8902.L.str.17902.L.str.7902.L.str.16902.L.str.6902.L.str.15902.L.str.5902.L.str.14902.L.str.4902.L.str.13902.L.str.3902.L.str.12902.L.str.2902.L.str.11902.L.str.1902.L.str.10902.L.str.902.L.str.19802.L.str.9802.L.str.18802.L.str.8802.L.str.17802.L.str.7802.L.str.16802.L.str.6802.L.str.15802.L.str.5802.L.str.14802.L.str.4802.L.str.13802.L.str.3802.L.str.12802.L.str.2802.L.str.11802.L.str.1802.L.str.10802.L.str.802.L.str.19702.L.str.9702.L.str.18702.L.str.8702.L.str.17702.L.str.7702.L.str.16702.L.str.6702.L.str.15702.L.str.5702.L.str.14702.L.str.4702.L.str.13702.L.str.3702.L.str.12702.L.str.2702.L.str.11702.L.str.1702.L.str.10702.L.str.702.L.str.19602.L.str.9602.L.str.18602.L.str.8602.L.str.17602.L.str.7602.L.str.16602.L.str.6602.L.str.15602.L.str.5602.L.str.14602.L.str.4602.L.str.13602.L.str.3602.L.str.12602.L.str.2602.L.str.11602.L.str.1602.L.str.10602.L.str.602.L.str.19502.L.str.9502.L.str.18502.L.str.8502.L.str.17502.L.str.7502.L.str.16502.L.str.6502.L.str.15502.L.str.5502.L.str.14502.L.str.4502.L.str.13502.L.str.3502.L.str.12502.L.str.2502.L.str.11502.L.str.1502.L.str.10502.L.str.502.L.str.19402.L.str.9402.L.str.18402.L.str.8402.L.str.17402.L.str.7402.L.str.16402.L.str.6402.L.str.15402.L.str.5402.L.str.14402.L.str.4402.L.str.13402.L.str.3402.L.str.12402.L.str.2402.L.str.11402.L.str.1402.L.str.10402.L.str.402.L.str.19302.L.str.9302.L.str.18302.L.str.8302.L.str.17302.L.str.7302.L.str.16302.L.str.6302.L.str.15302.L.str.5302.L.str.14302.L.str.4302.L.str.13302.L.str.3302.L.str.12302.L.str.2302.L.str.11302.L.str.1302.L.str.10302.L.str.302.L.str.19202.L.str.9202.L.str.18202.L.str.8202.L.str.17202.L.str.7202.L.str.16202.L.str.6202.L.str.15202.L.str.5202.L.str.14202.L.str.4202.L.str.13202.L.str.3202.L.str.12202.L.str.2202.L.str.11202.L.str.1202.L.str.10202.L.str.202.L.str.19102.L.str.9102.L.str.18102.L.str.8102.L.str.17102.L.str.7102.L.str.16102.L.str.6102.L.str.15102.L.str.5102.L.str.14102.L.str.4102.L.str.13102.L.str.3102.L.str.12102.L.str.2102.L.str.11102.L.str.1102.L.str.10102.L.str.102.L.str.19002.L.str.9002.L.str.18002.L.str.8002.L.str.17002.L.str.7002.L.str.16002.L.str.6002.L.str.15002.L.str.5002.L.str.14002.L.str.4002.L.str.13002.L.str.3002.L.str.12002.L.str.2002.L.str.11002.L.str.1002.L.str.10002.L.str.2pme_amdzen1.L.str.9991.L.str.18991.L.str.8991.L.str.17991.L.str.7991.L.str.16991.L.str.6991.L.str.15991.L.str.5991.L.str.14991.L.str.4991.L.str.13991.L.str.3991.L.str.12991.L.str.2991.L.str.11991.L.str.1991.L.str.10991.L.str.991.L.str.9891.L.str.18891.L.str.8891.L.str.17891.L.str.7891.L.str.16891.L.str.6891.L.str.15891.L.str.5891.L.str.14891.L.str.4891.L.str.13891.L.str.3891.L.str.12891.L.str.2891.L.str.11891.L.str.1891.L.str.10891.L.str.891.L.str.19791.L.str.9791.L.str.18791.L.str.8791.L.str.17791.L.str.7791.L.str.16791.L.str.6791.L.str.15791.L.str.5791.L.str.14791.L.str.4791.L.str.13791.L.str.3791.L.str.12791.L.str.2791.L.str.11791.L.str.1791.L.str.10791.L.str.791.L.str.19691.L.str.9691.L.str.18691.L.str.8691.L.str.17691.L.str.7691.L.str.16691.L.str.6691.L.str.15691.L.str.5691.L.str.14691.L.str.4691.L.str.13691.L.str.3691.L.str.12691.L.str.2691.L.str.11691.L.str.1691.L.str.10691.L.str.691.L.str.19591.L.str.9591.L.str.18591.L.str.8591.L.str.17591.L.str.7591.L.str.16591.L.str.6591.L.str.15591.L.str.5591.L.str.14591.L.str.4591.L.str.13591.L.str.3591.L.str.12591.L.str.2591.L.str.11591.L.str.1591.L.str.10591.L.str.591.L.str.19491.L.str.9491.L.str.18491.L.str.8491.L.str.17491.L.str.7491.L.str.16491.L.str.6491.L.str.15491.L.str.5491.L.str.14491.L.str.4491.L.str.13491.L.str.3491.L.str.12491.L.str.2491.L.str.11491.L.str.1491.L.str.10491.L.str.491.L.str.19391.L.str.9391.L.str.18391.L.str.8391.L.str.17391.L.str.7391.L.str.16391.L.str.6391.L.str.15391.L.str.5391.L.str.14391.L.str.4391.L.str.13391.L.str.3391.L.str.12391.L.str.2391.L.str.11391.L.str.1391.L.str.10391.L.str.391.L.str.19291.L.str.9291.L.str.18291.L.str.8291.L.str.17291.L.str.7291.L.str.16291.L.str.6291.L.str.15291.L.str.5291.L.str.14291.L.str.4291.L.str.13291.L.str.3291.L.str.12291.L.str.2291.L.str.11291.L.str.1291.L.str.10291.L.str.291.L.str.19191.L.str.9191.L.str.18191.L.str.8191.L.str.17191.L.str.7191.L.str.16191.L.str.6191.L.str.15191.L.str.5191.L.str.14191.L.str.4191.L.str.13191.L.str.3191.L.str.12191.L.str.2191.L.str.11191.L.str.1191.L.str.10191.L.str.191.L.str.19091.L.str.9091.L.str.18091.L.str.8091.L.str.17091.L.str.7091.L.str.16091.L.str.6091.L.str.15091.L.str.5091.L.str.14091.L.str.4091.L.str.13091.L.str.3091.L.str.12091.L.str.2091.L.str.11091.L.str.1091.L.str.10091.L.str.91.L.str.9981.L.str.18981.L.str.8981.L.str.17981.L.str.7981.L.str.16981.L.str.6981.L.str.15981.L.str.5981.L.str.14981.L.str.4981.L.str.13981.L.str.3981.L.str.12981.L.str.2981.L.str.11981.L.str.1981.L.str.10981.L.str.981.L.str.9881.L.str.18881.L.str.8881.L.str.17881.L.str.7881.L.str.16881.L.str.6881.L.str.15881.L.str.5881.L.str.14881.L.str.4881.L.str.13881.L.str.3881.L.str.12881.L.str.2881.L.str.11881.L.str.1881.L.str.10881.L.str.881.L.str.19781.L.str.9781.L.str.18781.L.str.8781.L.str.17781.L.str.7781.L.str.16781.L.str.6781.L.str.15781.L.str.5781.L.str.14781.L.str.4781.L.str.13781.L.str.3781.L.str.12781.L.str.2781.L.str.11781.L.str.1781.L.str.10781.L.str.781.L.str.19681.L.str.9681.L.str.18681.L.str.8681.L.str.17681.L.str.7681.L.str.16681.L.str.6681.L.str.15681.L.str.5681.L.str.14681.L.str.4681.L.str.13681.L.str.3681.L.str.12681.L.str.2681.L.str.11681.L.str.1681.L.str.10681.L.str.681.L.str.19581.L.str.9581.L.str.18581.L.str.8581.L.str.17581.L.str.7581.L.str.16581.L.str.6581.L.str.15581.L.str.5581.L.str.14581.L.str.4581.L.str.13581.L.str.3581.L.str.12581.L.str.2581.L.str.11581.L.str.1581.L.str.10581.L.str.581.L.str.19481.L.str.9481.L.str.18481.L.str.8481.L.str.17481.L.str.7481.L.str.16481.L.str.6481.L.str.15481.L.str.5481.L.str.14481.L.str.4481.L.str.13481.L.str.3481.L.str.12481.L.str.2481.L.str.11481.L.str.1481.L.str.10481.L.str.481.L.str.19381.L.str.9381.L.str.18381.L.str.8381.L.str.17381.L.str.7381.L.str.16381.L.str.6381.L.str.15381.L.str.5381.L.str.14381.L.str.4381.L.str.13381.L.str.3381.L.str.12381.L.str.2381.L.str.11381.L.str.1381.L.str.10381.L.str.381.L.str.19281.L.str.9281.L.str.18281.L.str.8281.L.str.17281.L.str.7281.L.str.16281.L.str.6281.L.str.15281.L.str.5281.L.str.14281.L.str.4281.L.str.13281.L.str.3281.L.str.12281.L.str.2281.L.str.11281.L.str.1281.L.str.10281.L.str.281.L.str.19181.L.str.9181.L.str.18181.L.str.8181.L.str.17181.L.str.7181.L.str.16181.L.str.6181.L.str.15181.L.str.5181.L.str.14181.L.str.4181.L.str.13181.L.str.3181.L.str.12181.L.str.2181.L.str.11181.L.str.1181.L.str.10181.L.str.181.L.str.19081.L.str.9081.L.str.18081.L.str.8081.L.str.17081.L.str.7081.L.str.16081.L.str.6081.L.str.15081.L.str.5081.L.str.14081.L.str.4081.L.str.13081.L.str.3081.L.str.12081.L.str.2081.L.str.11081.L.str.1081.L.str.10081.L.str.81.L.str.9971.L.str.18971.L.str.8971.L.str.17971.L.str.7971.L.str.16971.L.str.6971.L.str.15971.L.str.5971.L.str.14971.L.str.4971.L.str.13971.L.str.3971.L.str.12971.L.str.2971.L.str.11971.L.str.1971.L.str.10971.L.str.971.L.str.9871.L.str.18871.L.str.8871.L.str.17871.L.str.7871.L.str.16871.L.str.6871.L.str.15871.L.str.5871.L.str.14871.L.str.4871.L.str.13871.L.str.3871.L.str.12871.L.str.2871.L.str.11871.L.str.1871.L.str.10871.L.str.871.L.str.19771.L.str.9771.L.str.18771.L.str.8771.L.str.17771.L.str.7771.L.str.16771.L.str.6771.L.str.15771.L.str.5771.L.str.14771.L.str.4771.L.str.13771.L.str.3771.L.str.12771.L.str.2771.L.str.11771.L.str.1771.L.str.10771.L.str.771.L.str.19671.L.str.9671.L.str.18671.L.str.8671.L.str.17671.L.str.7671.L.str.16671.L.str.6671.L.str.15671.L.str.5671.L.str.14671.L.str.4671.L.str.13671.L.str.3671.L.str.12671.L.str.2671.L.str.11671.L.str.1671.L.str.10671.L.str.671.L.str.19571.L.str.9571.L.str.18571.L.str.8571.L.str.17571.L.str.7571.L.str.16571.L.str.6571.L.str.15571.L.str.5571.L.str.14571.L.str.4571.L.str.13571.L.str.3571.L.str.12571.L.str.2571.L.str.11571.L.str.1571.L.str.10571.L.str.571.L.str.19471.L.str.9471.L.str.18471.L.str.8471.L.str.17471.L.str.7471.L.str.16471.L.str.6471.L.str.15471.L.str.5471.L.str.14471.L.str.4471.L.str.13471.L.str.3471.L.str.12471.L.str.2471.L.str.11471.L.str.1471.L.str.10471.L.str.471.L.str.19371.L.str.9371.L.str.18371.L.str.8371.L.str.17371.L.str.7371.L.str.16371.L.str.6371.L.str.15371.L.str.5371.L.str.14371.L.str.4371.L.str.13371.L.str.3371.L.str.12371.L.str.2371.L.str.11371.L.str.1371.L.str.10371.L.str.371.L.str.19271.L.str.9271.L.str.18271.L.str.8271.L.str.17271.L.str.7271.L.str.16271.L.str.6271.L.str.15271.L.str.5271.L.str.14271.L.str.4271.L.str.13271.L.str.3271.L.str.12271.L.str.2271.L.str.11271.L.str.1271.L.str.10271.L.str.271.L.str.19171.L.str.9171.L.str.18171.L.str.8171.L.str.17171.L.str.7171.L.str.16171.L.str.6171.L.str.15171.L.str.5171.L.str.14171.L.str.4171.L.str.13171.L.str.3171.L.str.12171.L.str.2171.L.str.11171.L.str.1171.L.str.10171.L.str.171.L.str.19071.L.str.9071.L.str.18071.L.str.8071.L.str.17071.L.str.7071.L.str.16071.L.str.6071.L.str.15071.L.str.5071.L.str.14071.L.str.4071.L.str.13071.L.str.3071.L.str.12071.L.str.2071.L.str.11071.L.str.1071.L.str.10071.L.str.71.L.str.9961.L.str.18961.L.str.8961.L.str.17961.L.str.7961.L.str.16961.L.str.6961.L.str.15961.L.str.5961.L.str.14961.L.str.4961.L.str.13961.L.str.3961.L.str.12961.L.str.2961.L.str.11961.L.str.1961.L.str.10961.L.str.961.L.str.19861.L.str.9861.L.str.18861.L.str.8861.L.str.17861.L.str.7861.L.str.16861.L.str.6861.L.str.15861.L.str.5861.L.str.14861.L.str.4861.L.str.13861.L.str.3861.L.str.12861.L.str.2861.L.str.11861.L.str.1861.L.str.10861.L.str.861.L.str.19761.L.str.9761.L.str.18761.L.str.8761.L.str.17761.L.str.7761.L.str.16761.L.str.6761.L.str.15761.L.str.5761.L.str.14761.L.str.4761.L.str.13761.L.str.3761.L.str.12761.L.str.2761.L.str.11761.L.str.1761.L.str.10761.L.str.761.L.str.19661.L.str.9661.L.str.18661.L.str.8661.L.str.17661.L.str.7661.L.str.16661.L.str.6661.L.str.15661.L.str.5661.L.str.14661.L.str.4661.L.str.13661.L.str.3661.L.str.12661.L.str.2661.L.str.11661.L.str.1661.L.str.10661.L.str.661.L.str.19561.L.str.9561.L.str.18561.L.str.8561.L.str.17561.L.str.7561.L.str.16561.L.str.6561.L.str.15561.L.str.5561.L.str.14561.L.str.4561.L.str.13561.L.str.3561.L.str.12561.L.str.2561.L.str.11561.L.str.1561.L.str.10561.L.str.561.L.str.19461.L.str.9461.L.str.18461.L.str.8461.L.str.17461.L.str.7461.L.str.16461.L.str.6461.L.str.15461.L.str.5461.L.str.14461.L.str.4461.L.str.13461.L.str.3461.L.str.12461.L.str.2461.L.str.11461.L.str.1461.L.str.10461.L.str.461.L.str.19361.L.str.9361.L.str.18361.L.str.8361.L.str.17361.L.str.7361.L.str.16361.L.str.6361.L.str.15361.L.str.5361.L.str.14361.L.str.4361.L.str.13361.L.str.3361.L.str.12361.L.str.2361.L.str.11361.L.str.1361.L.str.10361.L.str.361.L.str.19261.L.str.9261.L.str.18261.L.str.8261.L.str.17261.L.str.7261.L.str.16261.L.str.6261.L.str.15261.L.str.5261.L.str.14261.L.str.4261.L.str.13261.L.str.3261.L.str.12261.L.str.2261.L.str.11261.L.str.1261.L.str.10261.L.str.261.L.str.19161.L.str.9161.L.str.18161.L.str.8161.L.str.17161.L.str.7161.L.str.16161.L.str.6161.L.str.15161.L.str.5161.L.str.14161.L.str.4161.L.str.13161.L.str.3161.L.str.12161.L.str.2161.L.str.11161.L.str.1161.L.str.10161.L.str.161.L.str.19061.L.str.9061.L.str.18061.L.str.8061.L.str.17061.L.str.7061.L.str.16061.L.str.6061.L.str.15061.L.str.5061.L.str.14061.L.str.4061.L.str.13061.L.str.3061.L.str.12061.L.str.2061.L.str.11061.L.str.1061.L.str.10061.L.str.61.L.str.9951.L.str.18951.L.str.8951.L.str.17951.L.str.7951.L.str.16951.L.str.6951.L.str.15951.L.str.5951.L.str.14951.L.str.4951.L.str.13951.L.str.3951.L.str.12951.L.str.2951.L.str.11951.L.str.1951.L.str.10951.L.str.951.L.str.19851.L.str.9851.L.str.18851.L.str.8851.L.str.17851.L.str.7851.L.str.16851.L.str.6851.L.str.15851.L.str.5851.L.str.14851.L.str.4851.L.str.13851.L.str.3851.L.str.12851.L.str.2851.L.str.11851.L.str.1851.L.str.10851.L.str.851.L.str.19751.L.str.9751.L.str.18751.L.str.8751.L.str.17751.L.str.7751.L.str.16751.L.str.6751.L.str.15751.L.str.5751.L.str.14751.L.str.4751.L.str.13751.L.str.3751.L.str.12751.L.str.2751.L.str.11751.L.str.1751.L.str.10751.L.str.751.L.str.19651.L.str.9651.L.str.18651.L.str.8651.L.str.17651.L.str.7651.L.str.16651.L.str.6651.L.str.15651.L.str.5651.L.str.14651.L.str.4651.L.str.13651.L.str.3651.L.str.12651.L.str.2651.L.str.11651.L.str.1651.L.str.10651.L.str.651.L.str.19551.L.str.9551.L.str.18551.L.str.8551.L.str.17551.L.str.7551.L.str.16551.L.str.6551.L.str.15551.L.str.5551.L.str.14551.L.str.4551.L.str.13551.L.str.3551.L.str.12551.L.str.2551.L.str.11551.L.str.1551.L.str.10551.L.str.551.L.str.19451.L.str.9451.L.str.18451.L.str.8451.L.str.17451.L.str.7451.L.str.16451.L.str.6451.L.str.15451.L.str.5451.L.str.14451.L.str.4451.L.str.13451.L.str.3451.L.str.12451.L.str.2451.L.str.11451.L.str.1451.L.str.10451.L.str.451.L.str.19351.L.str.9351.L.str.18351.L.str.8351.L.str.17351.L.str.7351.L.str.16351.L.str.6351.L.str.15351.L.str.5351.L.str.14351.L.str.4351.L.str.13351.L.str.3351.L.str.12351.L.str.2351.L.str.11351.L.str.1351.L.str.10351.L.str.351.L.str.19251.L.str.9251.L.str.18251.L.str.8251.L.str.17251.L.str.7251.L.str.16251.L.str.6251.L.str.15251.L.str.5251.L.str.14251.L.str.4251.L.str.13251.L.str.3251.L.str.12251.L.str.2251.L.str.11251.L.str.1251.L.str.10251.L.str.251.L.str.19151.L.str.9151.L.str.18151.L.str.8151.L.str.17151.L.str.7151.L.str.16151.L.str.6151.L.str.15151.L.str.5151.L.str.14151.L.str.4151.L.str.13151.L.str.3151.L.str.12151.L.str.2151.L.str.11151.L.str.1151.L.str.10151.L.str.151.L.str.19051.L.str.9051.L.str.18051.L.str.8051.L.str.17051.L.str.7051.L.str.16051.L.str.6051.L.str.15051.L.str.5051.L.str.14051.L.str.4051.L.str.13051.L.str.3051.L.str.12051.L.str.2051.L.str.11051.L.str.1051.L.str.10051.L.str.51.L.str.9941.L.str.18941.L.str.8941.L.str.17941.L.str.7941.L.str.16941.L.str.6941.L.str.15941.L.str.5941.L.str.14941.L.str.4941.L.str.13941.L.str.3941.L.str.12941.L.str.2941.L.str.11941.L.str.1941.L.str.10941.L.str.941.L.str.19841.L.str.9841.L.str.18841.L.str.8841.L.str.17841.L.str.7841.L.str.16841.L.str.6841.L.str.15841.L.str.5841.L.str.14841.L.str.4841.L.str.13841.L.str.3841.L.str.12841.L.str.2841.L.str.11841.L.str.1841.L.str.10841.L.str.841.L.str.19741.L.str.9741.L.str.18741.L.str.8741.L.str.17741.L.str.7741.L.str.16741.L.str.6741.L.str.15741.L.str.5741.L.str.14741.L.str.4741.L.str.13741.L.str.3741.L.str.12741.L.str.2741.L.str.11741.L.str.1741.L.str.10741.L.str.741.L.str.19641.L.str.9641.L.str.18641.L.str.8641.L.str.17641.L.str.7641.L.str.16641.L.str.6641.L.str.15641.L.str.5641.L.str.14641.L.str.4641.L.str.13641.L.str.3641.L.str.12641.L.str.2641.L.str.11641.L.str.1641.L.str.10641.L.str.641.L.str.19541.L.str.9541.L.str.18541.L.str.8541.L.str.17541.L.str.7541.L.str.16541.L.str.6541.L.str.15541.L.str.5541.L.str.14541.L.str.4541.L.str.13541.L.str.3541.L.str.12541.L.str.2541.L.str.11541.L.str.1541.L.str.10541.L.str.541.L.str.19441.L.str.9441.L.str.18441.L.str.8441.L.str.17441.L.str.7441.L.str.16441.L.str.6441.L.str.15441.L.str.5441.L.str.14441.L.str.4441.L.str.13441.L.str.3441.L.str.12441.L.str.2441.L.str.11441.L.str.1441.L.str.10441.L.str.441.L.str.19341.L.str.9341.L.str.18341.L.str.8341.L.str.17341.L.str.7341.L.str.16341.L.str.6341.L.str.15341.L.str.5341.L.str.14341.L.str.4341.L.str.13341.L.str.3341.L.str.12341.L.str.2341.L.str.11341.L.str.1341.L.str.10341.L.str.341.L.str.19241.L.str.9241.L.str.18241.L.str.8241.L.str.17241.L.str.7241.L.str.16241.L.str.6241.L.str.15241.L.str.5241.L.str.14241.L.str.4241.L.str.13241.L.str.3241.L.str.12241.L.str.2241.L.str.11241.L.str.1241.L.str.10241.L.str.241.L.str.19141.L.str.9141.L.str.18141.L.str.8141.L.str.17141.L.str.7141.L.str.16141.L.str.6141.L.str.15141.L.str.5141.L.str.14141.L.str.4141.L.str.13141.L.str.3141.L.str.12141.L.str.2141.L.str.11141.L.str.1141.L.str.10141.L.str.141.L.str.19041.L.str.9041.L.str.18041.L.str.8041.L.str.17041.L.str.7041.L.str.16041.L.str.6041.L.str.15041.L.str.5041.L.str.14041.L.str.4041.L.str.13041.L.str.3041.L.str.12041.L.str.2041.L.str.11041.L.str.1041.L.str.10041.L.str.41.L.str.9931.L.str.18931.L.str.8931.L.str.17931.L.str.7931.L.str.16931.L.str.6931.L.str.15931.L.str.5931.L.str.14931.L.str.4931.L.str.13931.L.str.3931.L.str.12931.L.str.2931.L.str.11931.L.str.1931.L.str.10931.L.str.931.L.str.19831.L.str.9831.L.str.18831.L.str.8831.L.str.17831.L.str.7831.L.str.16831.L.str.6831.L.str.15831.L.str.5831.L.str.14831.L.str.4831.L.str.13831.L.str.3831.L.str.12831.L.str.2831.L.str.11831.L.str.1831.L.str.10831.L.str.831.L.str.19731.L.str.9731.L.str.18731.L.str.8731.L.str.17731.L.str.7731.L.str.16731.L.str.6731.L.str.15731.L.str.5731.L.str.14731.L.str.4731.L.str.13731.L.str.3731.L.str.12731.L.str.2731.L.str.11731.L.str.1731.L.str.10731.L.str.731.L.str.19631.L.str.9631.L.str.18631.L.str.8631.L.str.17631.L.str.7631.L.str.16631.L.str.6631.L.str.15631.L.str.5631.L.str.14631.L.str.4631.L.str.13631.L.str.3631.L.str.12631.L.str.2631.L.str.11631.L.str.1631.L.str.10631.L.str.631.L.str.19531.L.str.9531.L.str.18531.L.str.8531.L.str.17531.L.str.7531.L.str.16531.L.str.6531.L.str.15531.L.str.5531.L.str.14531.L.str.4531.L.str.13531.L.str.3531.L.str.12531.L.str.2531.L.str.11531.L.str.1531.L.str.10531.L.str.531.L.str.19431.L.str.9431.L.str.18431.L.str.8431.L.str.17431.L.str.7431.L.str.16431.L.str.6431.L.str.15431.L.str.5431.L.str.14431.L.str.4431.L.str.13431.L.str.3431.L.str.12431.L.str.2431.L.str.11431.L.str.1431.L.str.10431.L.str.431.L.str.19331.L.str.9331.L.str.18331.L.str.8331.L.str.17331.L.str.7331.L.str.16331.L.str.6331.L.str.15331.L.str.5331.L.str.14331.L.str.4331.L.str.13331.L.str.3331.L.str.12331.L.str.2331.L.str.11331.L.str.1331.L.str.10331.L.str.331.L.str.19231.L.str.9231.L.str.18231.L.str.8231.L.str.17231.L.str.7231.L.str.16231.L.str.6231.L.str.15231.L.str.5231.L.str.14231.L.str.4231.L.str.13231.L.str.3231.L.str.12231.L.str.2231.L.str.11231.L.str.1231.L.str.10231.L.str.231.L.str.19131.L.str.9131.L.str.18131.L.str.8131.L.str.17131.L.str.7131.L.str.16131.L.str.6131.L.str.15131.L.str.5131.L.str.14131.L.str.4131.L.str.13131.L.str.3131.L.str.12131.L.str.2131.L.str.11131.L.str.1131.L.str.10131.L.str.131.L.str.19031.L.str.9031.L.str.18031.L.str.8031.L.str.17031.L.str.7031.L.str.16031.L.str.6031.L.str.15031.L.str.5031.L.str.14031.L.str.4031.L.str.13031.L.str.3031.L.str.12031.L.str.2031.L.str.11031.L.str.1031.L.str.10031.L.str.31.L.str.9921.L.str.18921.L.str.8921.L.str.17921.L.str.7921.L.str.16921.L.str.6921.L.str.15921.L.str.5921.L.str.14921.L.str.4921.L.str.13921.L.str.3921.L.str.12921.L.str.2921.L.str.11921.L.str.1921.L.str.10921.L.str.921.L.str.19821.L.str.9821.L.str.18821.L.str.8821.L.str.17821.L.str.7821.L.str.16821.L.str.6821.L.str.15821.L.str.5821.L.str.14821.L.str.4821.L.str.13821.L.str.3821.L.str.12821.L.str.2821.L.str.11821.L.str.1821.L.str.10821.L.str.821.L.str.19721.L.str.9721.L.str.18721.L.str.8721.L.str.17721.L.str.7721.L.str.16721.L.str.6721.L.str.15721.L.str.5721.L.str.14721.L.str.4721.L.str.13721.L.str.3721.L.str.12721.L.str.2721.L.str.11721.L.str.1721.L.str.10721.L.str.721.L.str.19621.L.str.9621.L.str.18621.L.str.8621.L.str.17621.L.str.7621.L.str.16621.L.str.6621.L.str.15621.L.str.5621.L.str.14621.L.str.4621.L.str.13621.L.str.3621.L.str.12621.L.str.2621.L.str.11621.L.str.1621.L.str.10621.L.str.621.L.str.19521.L.str.9521.L.str.18521.L.str.8521.L.str.17521.L.str.7521.L.str.16521.L.str.6521.L.str.15521.L.str.5521.L.str.14521.L.str.4521.L.str.13521.L.str.3521.L.str.12521.L.str.2521.L.str.11521.L.str.1521.L.str.10521.L.str.521.L.str.19421.L.str.9421.L.str.18421.L.str.8421.L.str.17421.L.str.7421.L.str.16421.L.str.6421.L.str.15421.L.str.5421.L.str.14421.L.str.4421.L.str.13421.L.str.3421.L.str.12421.L.str.2421.L.str.11421.L.str.1421.L.str.10421.L.str.421.L.str.19321.L.str.9321.L.str.18321.L.str.8321.L.str.17321.L.str.7321.L.str.16321.L.str.6321.L.str.15321.L.str.5321.L.str.14321.L.str.4321.L.str.13321.L.str.3321.L.str.12321.L.str.2321.L.str.11321.L.str.1321.L.str.10321.L.str.321.L.str.19221.L.str.9221.L.str.18221.L.str.8221.L.str.17221.L.str.7221.L.str.16221.L.str.6221.L.str.15221.L.str.5221.L.str.14221.L.str.4221.L.str.13221.L.str.3221.L.str.12221.L.str.2221.L.str.11221.L.str.1221.L.str.10221.L.str.221.L.str.19121.L.str.9121.L.str.18121.L.str.8121.L.str.17121.L.str.7121.L.str.16121.L.str.6121.L.str.15121.L.str.5121.L.str.14121.L.str.4121.L.str.13121.L.str.3121.L.str.12121.L.str.2121.L.str.11121.L.str.1121.L.str.10121.L.str.121.L.str.19021.L.str.9021.L.str.18021.L.str.8021.L.str.17021.L.str.7021.L.str.16021.L.str.6021.L.str.15021.L.str.5021.L.str.14021.L.str.4021.L.str.13021.L.str.3021.L.str.12021.L.str.2021.L.str.11021.L.str.1021.L.str.10021.L.str.21.L.str.9911.L.str.18911.L.str.8911.L.str.17911.L.str.7911.L.str.16911.L.str.6911.L.str.15911.L.str.5911.L.str.14911.L.str.4911.L.str.13911.L.str.3911.L.str.12911.L.str.2911.L.str.11911.L.str.1911.L.str.10911.L.str.911.L.str.19811.L.str.9811.L.str.18811.L.str.8811.L.str.17811.L.str.7811.L.str.16811.L.str.6811.L.str.15811.L.str.5811.L.str.14811.L.str.4811.L.str.13811.L.str.3811.L.str.12811.L.str.2811.L.str.11811.L.str.1811.L.str.10811.L.str.811.L.str.19711.L.str.9711.L.str.18711.L.str.8711.L.str.17711.L.str.7711.L.str.16711.L.str.6711.L.str.15711.L.str.5711.L.str.14711.L.str.4711.L.str.13711.L.str.3711.L.str.12711.L.str.2711.L.str.11711.L.str.1711.L.str.10711.L.str.711.L.str.19611.L.str.9611.L.str.18611.L.str.8611.L.str.17611.L.str.7611.L.str.16611.L.str.6611.L.str.15611.L.str.5611.L.str.14611.L.str.4611.L.str.13611.L.str.3611.L.str.12611.L.str.2611.L.str.11611.L.str.1611.L.str.10611.L.str.611.L.str.19511.L.str.9511.L.str.18511.L.str.8511.L.str.17511.L.str.7511.L.str.16511.L.str.6511.L.str.15511.L.str.5511.L.str.14511.L.str.4511.L.str.13511.L.str.3511.L.str.12511.L.str.2511.L.str.11511.L.str.1511.L.str.10511.L.str.511.L.str.19411.L.str.9411.L.str.18411.L.str.8411.L.str.17411.L.str.7411.L.str.16411.L.str.6411.L.str.15411.L.str.5411.L.str.14411.L.str.4411.L.str.13411.L.str.3411.L.str.12411.L.str.2411.L.str.11411.L.str.1411.L.str.10411.L.str.411.L.str.19311.L.str.9311.L.str.18311.L.str.8311.L.str.17311.L.str.7311.L.str.16311.L.str.6311.L.str.15311.L.str.5311.L.str.14311.L.str.4311.L.str.13311.L.str.3311.L.str.12311.L.str.2311.L.str.11311.L.str.1311.L.str.10311.L.str.311.L.str.19211.L.str.9211.L.str.18211.L.str.8211.L.str.17211.L.str.7211.L.str.16211.L.str.6211.L.str.15211.L.str.5211.L.str.14211.L.str.4211.L.str.13211.L.str.3211.L.str.12211.L.str.2211.L.str.11211.L.str.1211.L.str.10211.L.str.211.L.str.19111.L.str.9111.L.str.18111.L.str.8111.L.str.17111.L.str.7111.L.str.16111.L.str.6111.L.str.15111.L.str.5111.L.str.14111.L.str.4111.L.str.13111.L.str.3111.L.str.12111.L.str.2111.L.str.11111.L.str.1111.L.str.10111.L.str.111.L.str.19011.L.str.9011.L.str.18011.L.str.8011.L.str.17011.L.str.7011.L.str.16011.L.str.6011.L.str.15011.L.str.5011.L.str.14011.L.str.4011.L.str.13011.L.str.3011.L.str.12011.L.str.2011.L.str.11011.L.str.1011.L.str.10011.L.str.11.L.str.9901.L.str.18901.L.str.8901.L.str.17901.L.str.7901.L.str.16901.L.str.6901.L.str.15901.L.str.5901.L.str.14901.L.str.4901.L.str.13901.L.str.3901.L.str.12901.L.str.2901.L.str.11901.L.str.1901.L.str.10901.L.str.901.L.str.19801.L.str.9801.L.str.18801.L.str.8801.L.str.17801.L.str.7801.L.str.16801.L.str.6801.L.str.15801.L.str.5801.L.str.14801.L.str.4801.L.str.13801.L.str.3801.L.str.12801.L.str.2801.L.str.11801.L.str.1801.L.str.10801.L.str.801.L.str.19701.L.str.9701.L.str.18701.L.str.8701.L.str.17701.L.str.7701.L.str.16701.L.str.6701.L.str.15701.L.str.5701.L.str.14701.L.str.4701.L.str.13701.L.str.3701.L.str.12701.L.str.2701.L.str.11701.L.str.1701.L.str.10701.L.str.701.L.str.19601.L.str.9601.L.str.18601.L.str.8601.L.str.17601.L.str.7601.L.str.16601.L.str.6601.L.str.15601.L.str.5601.L.str.14601.L.str.4601.L.str.13601.L.str.3601.L.str.12601.L.str.2601.L.str.11601.L.str.1601.L.str.10601.L.str.601.L.str.19501.L.str.9501.L.str.18501.L.str.8501.L.str.17501.L.str.7501.L.str.16501.L.str.6501.L.str.15501.L.str.5501.L.str.14501.L.str.4501.L.str.13501.L.str.3501.L.str.12501.L.str.2501.L.str.11501.L.str.1501.L.str.10501.L.str.501.L.str.19401.L.str.9401.L.str.18401.L.str.8401.L.str.17401.L.str.7401.L.str.16401.L.str.6401.L.str.15401.L.str.5401.L.str.14401.L.str.4401.L.str.13401.L.str.3401.L.str.12401.L.str.2401.L.str.11401.L.str.1401.L.str.10401.L.str.401.L.str.19301.L.str.9301.L.str.18301.L.str.8301.L.str.17301.L.str.7301.L.str.16301.L.str.6301.L.str.15301.L.str.5301.L.str.14301.L.str.4301.L.str.13301.L.str.3301.L.str.12301.L.str.2301.L.str.11301.L.str.1301.L.str.10301.L.str.301.L.str.19201.L.str.9201.L.str.18201.L.str.8201.L.str.17201.L.str.7201.L.str.16201.L.str.6201.L.str.15201.L.str.5201.L.str.14201.L.str.4201.L.str.13201.L.str.3201.L.str.12201.L.str.2201.L.str.11201.L.str.1201.L.str.10201.L.str.201.L.str.19101.L.str.9101.L.str.18101.L.str.8101.L.str.17101.L.str.7101.L.str.16101.L.str.6101.L.str.15101.L.str.5101.L.str.14101.L.str.4101.L.str.13101.L.str.3101.L.str.12101.L.str.2101.L.str.11101.L.str.1101.L.str.10101.L.str.101.L.str.19001.L.str.9001.L.str.18001.L.str.8001.L.str.17001.L.str.7001.L.str.16001.L.str.6001.L.str.15001.L.str.5001.L.str.14001.L.str.4001.L.str.13001.L.str.3001.L.str.12001.L.str.2001.L.str.11001.L.str.1001.L.str.10001.L.str.1.rodata.str1.1.L.str.9990.L.str.18990.L.str.8990.L.str.17990.L.str.7990.L.str.16990.L.str.6990.L.str.15990.L.str.5990.L.str.14990.L.str.4990.L.str.13990.L.str.3990.L.str.12990.L.str.2990.L.str.11990.L.str.1990.L.str.10990.L.str.990.L.str.9890.L.str.18890.L.str.8890.L.str.17890.L.str.7890.L.str.16890.L.str.6890.L.str.15890.L.str.5890.L.str.14890.L.str.4890.L.str.13890.L.str.3890.L.str.12890.L.str.2890.L.str.11890.L.str.1890.L.str.10890.L.str.890.L.str.19790.L.str.9790.L.str.18790.L.str.8790.L.str.17790.L.str.7790.L.str.16790.L.str.6790.L.str.15790.L.str.5790.L.str.14790.L.str.4790.L.str.13790.L.str.3790.L.str.12790.L.str.2790.L.str.11790.L.str.1790.L.str.10790.L.str.790.L.str.19690.L.str.9690.L.str.18690.L.str.8690.L.str.17690.L.str.7690.L.str.16690.L.str.6690.L.str.15690.L.str.5690.L.str.14690.L.str.4690.L.str.13690.L.str.3690.L.str.12690.L.str.2690.L.str.11690.L.str.1690.L.str.10690.L.str.690.L.str.19590.L.str.9590.L.str.18590.L.str.8590.L.str.17590.L.str.7590.L.str.16590.L.str.6590.L.str.15590.L.str.5590.L.str.14590.L.str.4590.L.str.13590.L.str.3590.L.str.12590.L.str.2590.L.str.11590.L.str.1590.L.str.10590.L.str.590.L.str.19490.L.str.9490.L.str.18490.L.str.8490.L.str.17490.L.str.7490.L.str.16490.L.str.6490.L.str.15490.L.str.5490.L.str.14490.L.str.4490.L.str.13490.L.str.3490.L.str.12490.L.str.2490.L.str.11490.L.str.1490.L.str.10490.L.str.490.L.str.19390.L.str.9390.L.str.18390.L.str.8390.L.str.17390.L.str.7390.L.str.16390.L.str.6390.L.str.15390.L.str.5390.L.str.14390.L.str.4390.L.str.13390.L.str.3390.L.str.12390.L.str.2390.L.str.11390.L.str.1390.L.str.10390.L.str.390.L.str.19290.L.str.9290.L.str.18290.L.str.8290.L.str.17290.L.str.7290.L.str.16290.L.str.6290.L.str.15290.L.str.5290.L.str.14290.L.str.4290.L.str.13290.L.str.3290.L.str.12290.L.str.2290.L.str.11290.L.str.1290.L.str.10290.L.str.290.L.str.19190.L.str.9190.L.str.18190.L.str.8190.L.str.17190.L.str.7190.L.str.16190.L.str.6190.L.str.15190.L.str.5190.L.str.14190.L.str.4190.L.str.13190.L.str.3190.L.str.12190.L.str.2190.L.str.11190.L.str.1190.L.str.10190.L.str.190.L.str.19090.L.str.9090.L.str.18090.L.str.8090.L.str.17090.L.str.7090.L.str.16090.L.str.6090.L.str.15090.L.str.5090.L.str.14090.L.str.4090.L.str.13090.L.str.3090.L.str.12090.L.str.2090.L.str.11090.L.str.1090.L.str.10090.L.str.90.L.str.9980.L.str.18980.L.str.8980.L.str.17980.L.str.7980.L.str.16980.L.str.6980.L.str.15980.L.str.5980.L.str.14980.L.str.4980.L.str.13980.L.str.3980.L.str.12980.L.str.2980.L.str.11980.L.str.1980.L.str.10980.L.str.980.L.str.9880.L.str.18880.L.str.8880.L.str.17880.L.str.7880.L.str.16880.L.str.6880.L.str.15880.L.str.5880.L.str.14880.L.str.4880.L.str.13880.L.str.3880.L.str.12880.L.str.2880.L.str.11880.L.str.1880.L.str.10880.L.str.880.L.str.19780.L.str.9780.L.str.18780.L.str.8780.L.str.17780.L.str.7780.L.str.16780.L.str.6780.L.str.15780.L.str.5780.L.str.14780.L.str.4780.L.str.13780.L.str.3780.L.str.12780.L.str.2780.L.str.11780.L.str.1780.L.str.10780.L.str.780.L.str.19680.L.str.9680.L.str.18680.L.str.8680.L.str.17680.L.str.7680.L.str.16680.L.str.6680.L.str.15680.L.str.5680.L.str.14680.L.str.4680.L.str.13680.L.str.3680.L.str.12680.L.str.2680.L.str.11680.L.str.1680.L.str.10680.L.str.680.L.str.19580.L.str.9580.L.str.18580.L.str.8580.L.str.17580.L.str.7580.L.str.16580.L.str.6580.L.str.15580.L.str.5580.L.str.14580.L.str.4580.L.str.13580.L.str.3580.L.str.12580.L.str.2580.L.str.11580.L.str.1580.L.str.10580.L.str.580.L.str.19480.L.str.9480.L.str.18480.L.str.8480.L.str.17480.L.str.7480.L.str.16480.L.str.6480.L.str.15480.L.str.5480.L.str.14480.L.str.4480.L.str.13480.L.str.3480.L.str.12480.L.str.2480.L.str.11480.L.str.1480.L.str.10480.L.str.480.L.str.19380.L.str.9380.L.str.18380.L.str.8380.L.str.17380.L.str.7380.L.str.16380.L.str.6380.L.str.15380.L.str.5380.L.str.14380.L.str.4380.L.str.13380.L.str.3380.L.str.12380.L.str.2380.L.str.11380.L.str.1380.L.str.10380.L.str.380.L.str.19280.L.str.9280.L.str.18280.L.str.8280.L.str.17280.L.str.7280.L.str.16280.L.str.6280.L.str.15280.L.str.5280.L.str.14280.L.str.4280.L.str.13280.L.str.3280.L.str.12280.L.str.2280.L.str.11280.L.str.1280.L.str.10280.L.str.280.L.str.19180.L.str.9180.L.str.18180.L.str.8180.L.str.17180.L.str.7180.L.str.16180.L.str.6180.L.str.15180.L.str.5180.L.str.14180.L.str.4180.L.str.13180.L.str.3180.L.str.12180.L.str.2180.L.str.11180.L.str.1180.L.str.10180.L.str.180.L.str.19080.L.str.9080.L.str.18080.L.str.8080.L.str.17080.L.str.7080.L.str.16080.L.str.6080.L.str.15080.L.str.5080.L.str.14080.L.str.4080.L.str.13080.L.str.3080.L.str.12080.L.str.2080.L.str.11080.L.str.1080.L.str.10080.L.str.80.L.str.9970.L.str.18970.L.str.8970.L.str.17970.L.str.7970.L.str.16970.L.str.6970.L.str.15970.L.str.5970.L.str.14970.L.str.4970.L.str.13970.L.str.3970.L.str.12970.L.str.2970.L.str.11970.L.str.1970.L.str.10970.L.str.970.L.str.19870.L.str.9870.L.str.18870.L.str.8870.L.str.17870.L.str.7870.L.str.16870.L.str.6870.L.str.15870.L.str.5870.L.str.14870.L.str.4870.L.str.13870.L.str.3870.L.str.12870.L.str.2870.L.str.11870.L.str.1870.L.str.10870.L.str.870.L.str.19770.L.str.9770.L.str.18770.L.str.8770.L.str.17770.L.str.7770.L.str.16770.L.str.6770.L.str.15770.L.str.5770.L.str.14770.L.str.4770.L.str.13770.L.str.3770.L.str.12770.L.str.2770.L.str.11770.L.str.1770.L.str.10770.L.str.770.L.str.19670.L.str.9670.L.str.18670.L.str.8670.L.str.17670.L.str.7670.L.str.16670.L.str.6670.L.str.15670.L.str.5670.L.str.14670.L.str.4670.L.str.13670.L.str.3670.L.str.12670.L.str.2670.L.str.11670.L.str.1670.L.str.10670.L.str.670.L.str.19570.L.str.9570.L.str.18570.L.str.8570.L.str.17570.L.str.7570.L.str.16570.L.str.6570.L.str.15570.L.str.5570.L.str.14570.L.str.4570.L.str.13570.L.str.3570.L.str.12570.L.str.2570.L.str.11570.L.str.1570.L.str.10570.L.str.570.L.str.19470.L.str.9470.L.str.18470.L.str.8470.L.str.17470.L.str.7470.L.str.16470.L.str.6470.L.str.15470.L.str.5470.L.str.14470.L.str.4470.L.str.13470.L.str.3470.L.str.12470.L.str.2470.L.str.11470.L.str.1470.L.str.10470.L.str.470.L.str.19370.L.str.9370.L.str.18370.L.str.8370.L.str.17370.L.str.7370.L.str.16370.L.str.6370.L.str.15370.L.str.5370.L.str.14370.L.str.4370.L.str.13370.L.str.3370.L.str.12370.L.str.2370.L.str.11370.L.str.1370.L.str.10370.L.str.370.L.str.19270.L.str.9270.L.str.18270.L.str.8270.L.str.17270.L.str.7270.L.str.16270.L.str.6270.L.str.15270.L.str.5270.L.str.14270.L.str.4270.L.str.13270.L.str.3270.L.str.12270.L.str.2270.L.str.11270.L.str.1270.L.str.10270.L.str.270.L.str.19170.L.str.9170.L.str.18170.L.str.8170.L.str.17170.L.str.7170.L.str.16170.L.str.6170.L.str.15170.L.str.5170.L.str.14170.L.str.4170.L.str.13170.L.str.3170.L.str.12170.L.str.2170.L.str.11170.L.str.1170.L.str.10170.L.str.170.L.str.19070.L.str.9070.L.str.18070.L.str.8070.L.str.17070.L.str.7070.L.str.16070.L.str.6070.L.str.15070.L.str.5070.L.str.14070.L.str.4070.L.str.13070.L.str.3070.L.str.12070.L.str.2070.L.str.11070.L.str.1070.L.str.10070.L.str.70.L.str.9960.L.str.18960.L.str.8960.L.str.17960.L.str.7960.L.str.16960.L.str.6960.L.str.15960.L.str.5960.L.str.14960.L.str.4960.L.str.13960.L.str.3960.L.str.12960.L.str.2960.L.str.11960.L.str.1960.L.str.10960.L.str.960.L.str.19860.L.str.9860.L.str.18860.L.str.8860.L.str.17860.L.str.7860.L.str.16860.L.str.6860.L.str.15860.L.str.5860.L.str.14860.L.str.4860.L.str.13860.L.str.3860.L.str.12860.L.str.2860.L.str.11860.L.str.1860.L.str.10860.L.str.860.L.str.19760.L.str.9760.L.str.18760.L.str.8760.L.str.17760.L.str.7760.L.str.16760.L.str.6760.L.str.15760.L.str.5760.L.str.14760.L.str.4760.L.str.13760.L.str.3760.L.str.12760.L.str.2760.L.str.11760.L.str.1760.L.str.10760.L.str.760.L.str.19660.L.str.9660.L.str.18660.L.str.8660.L.str.17660.L.str.7660.L.str.16660.L.str.6660.L.str.15660.L.str.5660.L.str.14660.L.str.4660.L.str.13660.L.str.3660.L.str.12660.L.str.2660.L.str.11660.L.str.1660.L.str.10660.L.str.660.L.str.19560.L.str.9560.L.str.18560.L.str.8560.L.str.17560.L.str.7560.L.str.16560.L.str.6560.L.str.15560.L.str.5560.L.str.14560.L.str.4560.L.str.13560.L.str.3560.L.str.12560.L.str.2560.L.str.11560.L.str.1560.L.str.10560.L.str.560.L.str.19460.L.str.9460.L.str.18460.L.str.8460.L.str.17460.L.str.7460.L.str.16460.L.str.6460.L.str.15460.L.str.5460.L.str.14460.L.str.4460.L.str.13460.L.str.3460.L.str.12460.L.str.2460.L.str.11460.L.str.1460.L.str.10460.L.str.460.L.str.19360.L.str.9360.L.str.18360.L.str.8360.L.str.17360.L.str.7360.L.str.16360.L.str.6360.L.str.15360.L.str.5360.L.str.14360.L.str.4360.L.str.13360.L.str.3360.L.str.12360.L.str.2360.L.str.11360.L.str.1360.L.str.10360.L.str.360.L.str.19260.L.str.9260.L.str.18260.L.str.8260.L.str.17260.L.str.7260.L.str.16260.L.str.6260.L.str.15260.L.str.5260.L.str.14260.L.str.4260.L.str.13260.L.str.3260.L.str.12260.L.str.2260.L.str.11260.L.str.1260.L.str.10260.L.str.260.L.str.19160.L.str.9160.L.str.18160.L.str.8160.L.str.17160.L.str.7160.L.str.16160.L.str.6160.L.str.15160.L.str.5160.L.str.14160.L.str.4160.L.str.13160.L.str.3160.L.str.12160.L.str.2160.L.str.11160.L.str.1160.L.str.10160.L.str.160.L.str.19060.L.str.9060.L.str.18060.L.str.8060.L.str.17060.L.str.7060.L.str.16060.L.str.6060.L.str.15060.L.str.5060.L.str.14060.L.str.4060.L.str.13060.L.str.3060.L.str.12060.L.str.2060.L.str.11060.L.str.1060.L.str.10060.L.str.60.L.str.9950.L.str.18950.L.str.8950.L.str.17950.L.str.7950.L.str.16950.L.str.6950.L.str.15950.L.str.5950.L.str.14950.L.str.4950.L.str.13950.L.str.3950.L.str.12950.L.str.2950.L.str.11950.L.str.1950.L.str.10950.L.str.950.L.str.19850.L.str.9850.L.str.18850.L.str.8850.L.str.17850.L.str.7850.L.str.16850.L.str.6850.L.str.15850.L.str.5850.L.str.14850.L.str.4850.L.str.13850.L.str.3850.L.str.12850.L.str.2850.L.str.11850.L.str.1850.L.str.10850.L.str.850.L.str.19750.L.str.9750.L.str.18750.L.str.8750.L.str.17750.L.str.7750.L.str.16750.L.str.6750.L.str.15750.L.str.5750.L.str.14750.L.str.4750.L.str.13750.L.str.3750.L.str.12750.L.str.2750.L.str.11750.L.str.1750.L.str.10750.L.str.750.L.str.19650.L.str.9650.L.str.18650.L.str.8650.L.str.17650.L.str.7650.L.str.16650.L.str.6650.L.str.15650.L.str.5650.L.str.14650.L.str.4650.L.str.13650.L.str.3650.L.str.12650.L.str.2650.L.str.11650.L.str.1650.L.str.10650.L.str.650.L.str.19550.L.str.9550.L.str.18550.L.str.8550.L.str.17550.L.str.7550.L.str.16550.L.str.6550.L.str.15550.L.str.5550.L.str.14550.L.str.4550.L.str.13550.L.str.3550.L.str.12550.L.str.2550.L.str.11550.L.str.1550.L.str.10550.L.str.550.L.str.19450.L.str.9450.L.str.18450.L.str.8450.L.str.17450.L.str.7450.L.str.16450.L.str.6450.L.str.15450.L.str.5450.L.str.14450.L.str.4450.L.str.13450.L.str.3450.L.str.12450.L.str.2450.L.str.11450.L.str.1450.L.str.10450.L.str.450.L.str.19350.L.str.9350.L.str.18350.L.str.8350.L.str.17350.L.str.7350.L.str.16350.L.str.6350.L.str.15350.L.str.5350.L.str.14350.L.str.4350.L.str.13350.L.str.3350.L.str.12350.L.str.2350.L.str.11350.L.str.1350.L.str.10350.L.str.350.L.str.19250.L.str.9250.L.str.18250.L.str.8250.L.str.17250.L.str.7250.L.str.16250.L.str.6250.L.str.15250.L.str.5250.L.str.14250.L.str.4250.L.str.13250.L.str.3250.L.str.12250.L.str.2250.L.str.11250.L.str.1250.L.str.10250.L.str.250.L.str.19150.L.str.9150.L.str.18150.L.str.8150.L.str.17150.L.str.7150.L.str.16150.L.str.6150.L.str.15150.L.str.5150.L.str.14150.L.str.4150.L.str.13150.L.str.3150.L.str.12150.L.str.2150.L.str.11150.L.str.1150.L.str.10150.L.str.150.L.str.19050.L.str.9050.L.str.18050.L.str.8050.L.str.17050.L.str.7050.L.str.16050.L.str.6050.L.str.15050.L.str.5050.L.str.14050.L.str.4050.L.str.13050.L.str.3050.L.str.12050.L.str.2050.L.str.11050.L.str.1050.L.str.10050.L.str.50.L.str.9940.L.str.18940.L.str.8940.L.str.17940.L.str.7940.L.str.16940.L.str.6940.L.str.15940.L.str.5940.L.str.14940.L.str.4940.L.str.13940.L.str.3940.L.str.12940.L.str.2940.L.str.11940.L.str.1940.L.str.10940.L.str.940.L.str.19840.L.str.9840.L.str.18840.L.str.8840.L.str.17840.L.str.7840.L.str.16840.L.str.6840.L.str.15840.L.str.5840.L.str.14840.L.str.4840.L.str.13840.L.str.3840.L.str.12840.L.str.2840.L.str.11840.L.str.1840.L.str.10840.L.str.840.L.str.19740.L.str.9740.L.str.18740.L.str.8740.L.str.17740.L.str.7740.L.str.16740.L.str.6740.L.str.15740.L.str.5740.L.str.14740.L.str.4740.L.str.13740.L.str.3740.L.str.12740.L.str.2740.L.str.11740.L.str.1740.L.str.10740.L.str.740.L.str.19640.L.str.9640.L.str.18640.L.str.8640.L.str.17640.L.str.7640.L.str.16640.L.str.6640.L.str.15640.L.str.5640.L.str.14640.L.str.4640.L.str.13640.L.str.3640.L.str.12640.L.str.2640.L.str.11640.L.str.1640.L.str.10640.L.str.640.L.str.19540.L.str.9540.L.str.18540.L.str.8540.L.str.17540.L.str.7540.L.str.16540.L.str.6540.L.str.15540.L.str.5540.L.str.14540.L.str.4540.L.str.13540.L.str.3540.L.str.12540.L.str.2540.L.str.11540.L.str.1540.L.str.10540.L.str.540.L.str.19440.L.str.9440.L.str.18440.L.str.8440.L.str.17440.L.str.7440.L.str.16440.L.str.6440.L.str.15440.L.str.5440.L.str.14440.L.str.4440.L.str.13440.L.str.3440.L.str.12440.L.str.2440.L.str.11440.L.str.1440.L.str.10440.L.str.440.L.str.19340.L.str.9340.L.str.18340.L.str.8340.L.str.17340.L.str.7340.L.str.16340.L.str.6340.L.str.15340.L.str.5340.L.str.14340.L.str.4340.L.str.13340.L.str.3340.L.str.12340.L.str.2340.L.str.11340.L.str.1340.L.str.10340.L.str.340.L.str.19240.L.str.9240.L.str.18240.L.str.8240.L.str.17240.L.str.7240.L.str.16240.L.str.6240.L.str.15240.L.str.5240.L.str.14240.L.str.4240.L.str.13240.L.str.3240.L.str.12240.L.str.2240.L.str.11240.L.str.1240.L.str.10240.L.str.240.L.str.19140.L.str.9140.L.str.18140.L.str.8140.L.str.17140.L.str.7140.L.str.16140.L.str.6140.L.str.15140.L.str.5140.L.str.14140.L.str.4140.L.str.13140.L.str.3140.L.str.12140.L.str.2140.L.str.11140.L.str.1140.L.str.10140.L.str.140.L.str.19040.L.str.9040.L.str.18040.L.str.8040.L.str.17040.L.str.7040.L.str.16040.L.str.6040.L.str.15040.L.str.5040.L.str.14040.L.str.4040.L.str.13040.L.str.3040.L.str.12040.L.str.2040.L.str.11040.L.str.1040.L.str.10040.L.str.40.L.str.9930.L.str.18930.L.str.8930.L.str.17930.L.str.7930.L.str.16930.L.str.6930.L.str.15930.L.str.5930.L.str.14930.L.str.4930.L.str.13930.L.str.3930.L.str.12930.L.str.2930.L.str.11930.L.str.1930.L.str.10930.L.str.930.L.str.19830.L.str.9830.L.str.18830.L.str.8830.L.str.17830.L.str.7830.L.str.16830.L.str.6830.L.str.15830.L.str.5830.L.str.14830.L.str.4830.L.str.13830.L.str.3830.L.str.12830.L.str.2830.L.str.11830.L.str.1830.L.str.10830.L.str.830.L.str.19730.L.str.9730.L.str.18730.L.str.8730.L.str.17730.L.str.7730.L.str.16730.L.str.6730.L.str.15730.L.str.5730.L.str.14730.L.str.4730.L.str.13730.L.str.3730.L.str.12730.L.str.2730.L.str.11730.L.str.1730.L.str.10730.L.str.730.L.str.19630.L.str.9630.L.str.18630.L.str.8630.L.str.17630.L.str.7630.L.str.16630.L.str.6630.L.str.15630.L.str.5630.L.str.14630.L.str.4630.L.str.13630.L.str.3630.L.str.12630.L.str.2630.L.str.11630.L.str.1630.L.str.10630.L.str.630.L.str.19530.L.str.9530.L.str.18530.L.str.8530.L.str.17530.L.str.7530.L.str.16530.L.str.6530.L.str.15530.L.str.5530.L.str.14530.L.str.4530.L.str.13530.L.str.3530.L.str.12530.L.str.2530.L.str.11530.L.str.1530.L.str.10530.L.str.530.L.str.19430.L.str.9430.L.str.18430.L.str.8430.L.str.17430.L.str.7430.L.str.16430.L.str.6430.L.str.15430.L.str.5430.L.str.14430.L.str.4430.L.str.13430.L.str.3430.L.str.12430.L.str.2430.L.str.11430.L.str.1430.L.str.10430.L.str.430.L.str.19330.L.str.9330.L.str.18330.L.str.8330.L.str.17330.L.str.7330.L.str.16330.L.str.6330.L.str.15330.L.str.5330.L.str.14330.L.str.4330.L.str.13330.L.str.3330.L.str.12330.L.str.2330.L.str.11330.L.str.1330.L.str.10330.L.str.330.L.str.19230.L.str.9230.L.str.18230.L.str.8230.L.str.17230.L.str.7230.L.str.16230.L.str.6230.L.str.15230.L.str.5230.L.str.14230.L.str.4230.L.str.13230.L.str.3230.L.str.12230.L.str.2230.L.str.11230.L.str.1230.L.str.10230.L.str.230.L.str.19130.L.str.9130.L.str.18130.L.str.8130.L.str.17130.L.str.7130.L.str.16130.L.str.6130.L.str.15130.L.str.5130.L.str.14130.L.str.4130.L.str.13130.L.str.3130.L.str.12130.L.str.2130.L.str.11130.L.str.1130.L.str.10130.L.str.130.L.str.19030.L.str.9030.L.str.18030.L.str.8030.L.str.17030.L.str.7030.L.str.16030.L.str.6030.L.str.15030.L.str.5030.L.str.14030.L.str.4030.L.str.13030.L.str.3030.L.str.12030.L.str.2030.L.str.11030.L.str.1030.L.str.10030.L.str.30.L.str.9920.L.str.18920.L.str.8920.L.str.17920.L.str.7920.L.str.16920.L.str.6920.L.str.15920.L.str.5920.L.str.14920.L.str.4920.L.str.13920.L.str.3920.L.str.12920.L.str.2920.L.str.11920.L.str.1920.L.str.10920.L.str.920.L.str.19820.L.str.9820.L.str.18820.L.str.8820.L.str.17820.L.str.7820.L.str.16820.L.str.6820.L.str.15820.L.str.5820.L.str.14820.L.str.4820.L.str.13820.L.str.3820.L.str.12820.L.str.2820.L.str.11820.L.str.1820.L.str.10820.L.str.820.L.str.19720.L.str.9720.L.str.18720.L.str.8720.L.str.17720.L.str.7720.L.str.16720.L.str.6720.L.str.15720.L.str.5720.L.str.14720.L.str.4720.L.str.13720.L.str.3720.L.str.12720.L.str.2720.L.str.11720.L.str.1720.L.str.10720.L.str.720.L.str.19620.L.str.9620.L.str.18620.L.str.8620.L.str.17620.L.str.7620.L.str.16620.L.str.6620.L.str.15620.L.str.5620.L.str.14620.L.str.4620.L.str.13620.L.str.3620.L.str.12620.L.str.2620.L.str.11620.L.str.1620.L.str.10620.L.str.620.L.str.19520.L.str.9520.L.str.18520.L.str.8520.L.str.17520.L.str.7520.L.str.16520.L.str.6520.L.str.15520.L.str.5520.L.str.14520.L.str.4520.L.str.13520.L.str.3520.L.str.12520.L.str.2520.L.str.11520.L.str.1520.L.str.10520.L.str.520.L.str.19420.L.str.9420.L.str.18420.L.str.8420.L.str.17420.L.str.7420.L.str.16420.L.str.6420.L.str.15420.L.str.5420.L.str.14420.L.str.4420.L.str.13420.L.str.3420.L.str.12420.L.str.2420.L.str.11420.L.str.1420.L.str.10420.L.str.420.L.str.19320.L.str.9320.L.str.18320.L.str.8320.L.str.17320.L.str.7320.L.str.16320.L.str.6320.L.str.15320.L.str.5320.L.str.14320.L.str.4320.L.str.13320.L.str.3320.L.str.12320.L.str.2320.L.str.11320.L.str.1320.L.str.10320.L.str.320.L.str.19220.L.str.9220.L.str.18220.L.str.8220.L.str.17220.L.str.7220.L.str.16220.L.str.6220.L.str.15220.L.str.5220.L.str.14220.L.str.4220.L.str.13220.L.str.3220.L.str.12220.L.str.2220.L.str.11220.L.str.1220.L.str.10220.L.str.220.L.str.19120.L.str.9120.L.str.18120.L.str.8120.L.str.17120.L.str.7120.L.str.16120.L.str.6120.L.str.15120.L.str.5120.L.str.14120.L.str.4120.L.str.13120.L.str.3120.L.str.12120.L.str.2120.L.str.11120.L.str.1120.L.str.10120.L.str.120.L.str.19020.L.str.9020.L.str.18020.L.str.8020.L.str.17020.L.str.7020.L.str.16020.L.str.6020.L.str.15020.L.str.5020.L.str.14020.L.str.4020.L.str.13020.L.str.3020.L.str.12020.L.str.2020.L.str.11020.L.str.1020.L.str.10020.L.str.20.L.str.9910.L.str.18910.L.str.8910.L.str.17910.L.str.7910.L.str.16910.L.str.6910.L.str.15910.L.str.5910.L.str.14910.L.str.4910.L.str.13910.L.str.3910.L.str.12910.L.str.2910.L.str.11910.L.str.1910.L.str.10910.L.str.910.L.str.19810.L.str.9810.L.str.18810.L.str.8810.L.str.17810.L.str.7810.L.str.16810.L.str.6810.L.str.15810.L.str.5810.L.str.14810.L.str.4810.L.str.13810.L.str.3810.L.str.12810.L.str.2810.L.str.11810.L.str.1810.L.str.10810.L.str.810.L.str.19710.L.str.9710.L.str.18710.L.str.8710.L.str.17710.L.str.7710.L.str.16710.L.str.6710.L.str.15710.L.str.5710.L.str.14710.L.str.4710.L.str.13710.L.str.3710.L.str.12710.L.str.2710.L.str.11710.L.str.1710.L.str.10710.L.str.710.L.str.19610.L.str.9610.L.str.18610.L.str.8610.L.str.17610.L.str.7610.L.str.16610.L.str.6610.L.str.15610.L.str.5610.L.str.14610.L.str.4610.L.str.13610.L.str.3610.L.str.12610.L.str.2610.L.str.11610.L.str.1610.L.str.10610.L.str.610.L.str.19510.L.str.9510.L.str.18510.L.str.8510.L.str.17510.L.str.7510.L.str.16510.L.str.6510.L.str.15510.L.str.5510.L.str.14510.L.str.4510.L.str.13510.L.str.3510.L.str.12510.L.str.2510.L.str.11510.L.str.1510.L.str.10510.L.str.510.L.str.19410.L.str.9410.L.str.18410.L.str.8410.L.str.17410.L.str.7410.L.str.16410.L.str.6410.L.str.15410.L.str.5410.L.str.14410.L.str.4410.L.str.13410.L.str.3410.L.str.12410.L.str.2410.L.str.11410.L.str.1410.L.str.10410.L.str.410.L.str.19310.L.str.9310.L.str.18310.L.str.8310.L.str.17310.L.str.7310.L.str.16310.L.str.6310.L.str.15310.L.str.5310.L.str.14310.L.str.4310.L.str.13310.L.str.3310.L.str.12310.L.str.2310.L.str.11310.L.str.1310.L.str.10310.L.str.310.L.str.19210.L.str.9210.L.str.18210.L.str.8210.L.str.17210.L.str.7210.L.str.16210.L.str.6210.L.str.15210.L.str.5210.L.str.14210.L.str.4210.L.str.13210.L.str.3210.L.str.12210.L.str.2210.L.str.11210.L.str.1210.L.str.10210.L.str.210.L.str.19110.L.str.9110.L.str.18110.L.str.8110.L.str.17110.L.str.7110.L.str.16110.L.str.6110.L.str.15110.L.str.5110.L.str.14110.L.str.4110.L.str.13110.L.str.3110.L.str.12110.L.str.2110.L.str.11110.L.str.1110.L.str.10110.L.str.110.L.str.19010.L.str.9010.L.str.18010.L.str.8010.L.str.17010.L.str.7010.L.str.16010.L.str.6010.L.str.15010.L.str.5010.L.str.14010.L.str.4010.L.str.13010.L.str.3010.L.str.12010.L.str.2010.L.str.11010.L.str.1010.L.str.10010.L.str.10.L.str.9900.L.str.18900.L.str.8900.L.str.17900.L.str.7900.L.str.16900.L.str.6900.L.str.15900.L.str.5900.L.str.14900.L.str.4900.L.str.13900.L.str.3900.L.str.12900.L.str.2900.L.str.11900.L.str.1900.L.str.10900.L.str.900.L.str.19800.L.str.9800.L.str.18800.L.str.8800.L.str.17800.L.str.7800.L.str.16800.L.str.6800.L.str.15800.L.str.5800.L.str.14800.L.str.4800.L.str.13800.L.str.3800.L.str.12800.L.str.2800.L.str.11800.L.str.1800.L.str.10800.L.str.800.L.str.19700.L.str.9700.L.str.18700.L.str.8700.L.str.17700.L.str.7700.L.str.16700.L.str.6700.L.str.15700.L.str.5700.L.str.14700.L.str.4700.L.str.13700.L.str.3700.L.str.12700.L.str.2700.L.str.11700.L.str.1700.L.str.10700.L.str.700.L.str.19600.L.str.9600.L.str.18600.L.str.8600.L.str.17600.L.str.7600.L.str.16600.L.str.6600.L.str.15600.L.str.5600.L.str.14600.L.str.4600.L.str.13600.L.str.3600.L.str.12600.L.str.2600.L.str.11600.L.str.1600.L.str.10600.L.str.600.L.str.19500.L.str.9500.L.str.18500.L.str.8500.L.str.17500.L.str.7500.L.str.16500.L.str.6500.L.str.15500.L.str.5500.L.str.14500.L.str.4500.L.str.13500.L.str.3500.L.str.12500.L.str.2500.L.str.11500.L.str.1500.L.str.10500.L.str.500.L.str.19400.L.str.9400.L.str.18400.L.str.8400.L.str.17400.L.str.7400.L.str.16400.L.str.6400.L.str.15400.L.str.5400.L.str.14400.L.str.4400.L.str.13400.L.str.3400.L.str.12400.L.str.2400.L.str.11400.L.str.1400.L.str.10400.L.str.400.L.str.19300.L.str.9300.L.str.18300.L.str.8300.L.str.17300.L.str.7300.L.str.16300.L.str.6300.L.str.15300.L.str.5300.L.str.14300.L.str.4300.L.str.13300.L.str.3300.L.str.12300.L.str.2300.L.str.11300.L.str.1300.L.str.10300.L.str.300.L.str.19200.L.str.9200.L.str.18200.L.str.8200.L.str.17200.L.str.7200.L.str.16200.L.str.6200.L.str.15200.L.str.5200.L.str.14200.L.str.4200.L.str.13200.L.str.3200.L.str.12200.L.str.2200.L.str.11200.L.str.1200.L.str.10200.L.str.200.L.str.19100.L.str.9100.L.str.18100.L.str.8100.L.str.17100.L.str.7100.L.str.16100.L.str.6100.L.str.15100.L.str.5100.L.str.14100.L.str.4100.L.str.13100.L.str.3100.L.str.12100.L.str.2100.L.str.11100.L.str.1100.L.str.10100.L.str.100.L.str.19000.L.str.9000.L.str.18000.L.str.8000.L.str.17000.L.str.7000.L.str.16000.L.str.6000.L.str.15000.L.str.5000.L.str.14000.L.str.4000.L.str.13000.L.str.3000.L.str.12000.L.str.2000.L.str.11000.L.str.1000.L.str.10000�
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